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RTC. Code reorganization to correspond ChibiOS rules. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3356 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
barthess 2011-09-20 07:02:14 +00:00
parent be4e2ca38d
commit da3d1eae7b
7 changed files with 47 additions and 39 deletions
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45
os/hal/platforms/STM32/rtc_lld.c
View File

@ -115,23 +115,14 @@ void rtc_lld_init(void){
uint32_t preload = 0;
rccEnableBKPInterface(FALSE);
/* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling
* clocking on APB1, because these values only update when APB1 functioning.*/
RTC->CRL &= ~(RTC_CRL_RSF);
while (!(RTC->CRL & RTC_CRL_RSF))
;
//RCC->APB1ENR |= (RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN);
/* enable access to BKP registers */
PWR->CR |= PWR_CR_DBP;
/* select clock source */
RCC->BDCR |= RTC_CLOCK_SOURCE;
RCC->BDCR |= STM32_RTC;
chDbgCheck(((RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE) &&\
(RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSI) &&\
(RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_HSE)), "No clock source selected");
if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE){
#if STM32_RTC == STM32_RTC_LSE
if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){
RCC->BDCR |= RCC_BDCR_LSEON;
while(!(RCC->BDCR & RCC_BDCR_LSERDY))
@ -139,26 +130,32 @@ void rtc_lld_init(void){
RCC->BDCR |= RCC_BDCR_RTCEN;
}
preload = STM32_LSECLK - 1;
}
else if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSI){
#elif STM32_RTC == STM32_RTC_LSI
RCC->CSR |= RCC_CSR_LSION;
while(!(RCC->CSR & RCC_CSR_LSIRDY))
;
/* According to errata notes we must wait additional 100 uS for stabilization */
/* According to errata sheet we must wait additional 100 uS for stabilization */
uint32_t tmo = (STM32_SYSCLK / 1000000 ) * 100;
while(tmo--)
;
RCC->BDCR |= RCC_BDCR_RTCEN;
preload = STM32_LSICLK - 1;
}
else if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_HSE){
preload = (STM32_HSICLK / 128) - 1;
}
else{
chDbgPanic("Wrong");
}
/* Write preload register only if value changed */
#elif STM32_RTC == STM32_RTC_HSE
preload = (STM32_HSICLK / 128) - 1;
#else
#error "RTC clock source not selected"
#endif
/* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling
* clocking on APB1, because these values only update when APB1 functioning.*/
RTC->CRL &= ~(RTC_CRL_RSF);
while (!(RTC->CRL & RTC_CRL_RSF))
;
/* Write preload register only if its value changed */
if (preload != ((((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLL)){
while(!(RTC->CRL & RTC_CRL_RTOFF))
;
@ -174,7 +171,7 @@ void rtc_lld_init(void){
/* disable all interrupts and clear all even flags just to be safe */
RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE);
RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);
RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);
#if RTC_SUPPORTS_CALLBACKS
RTCD.alarm_cb = NULL;

8
os/hal/platforms/STM32/rtc_lld.h
View File

@ -47,14 +47,6 @@
#define RTC_SUPPORTS_CALLBACKS TRUE
#endif
/**
* @brief Clock source selecting. LSE by default.
*/
#if !defined(RTC_CLOCK_SOURCE) || defined(__DOXYGEN__)
#define RTC_CLOCK_SOURCE RCC_BDCR_RTCSEL_LSE
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/

7
os/hal/platforms/STM32F1xx/hal_lld_f100.h
View File

@ -228,6 +228,13 @@
#define STM32_MCO STM32_MCO_NOCLOCK
#endif
/**
* @brief Clock source selecting. LSI by default.
*/
#if !defined(STM32_RTC) || defined(__DOXYGEN__)
#define STM32_RTC STM32_RTC_LSI
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/

11
os/hal/platforms/STM32F1xx/hal_lld_f103.h
View File

@ -90,6 +90,11 @@
#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */
#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */
#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */
#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */
/*===========================================================================*/
/* Platform specific friendly IRQ names. */
/*===========================================================================*/
@ -251,6 +256,12 @@
#define STM32_MCO STM32_MCO_NOCLOCK
#endif
/**
* @brief Clock source selecting. LSI by default.
*/
#if !defined(STM32_RTC) || defined(__DOXYGEN__)
#define STM32_RTC STM32_RTC_LSI
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/

7
os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
View File

@ -317,6 +317,13 @@
#define STM32_MCO STM32_MCO_NOCLOCK
#endif
/**
* @brief Clock source selecting. LSI by default.
*/
#if !defined(STM32_RTC) || defined(__DOXYGEN__)
#define STM32_RTC STM32_RTC_LSI
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/

7
testhal/STM32F1xx/RTC/halconf.h
View File

@ -219,13 +219,6 @@
#define RTC_SUPPORTS_CALLBACKS TRUE
#endif
/**
* @brief Clock source selecting. LSE by default.
*/
#if !defined(RTC_CLOCK_SOURCE) || defined(__DOXYGEN__)
#define RTC_CLOCK_SOURCE RCC_BDCR_RTCSEL_LSE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/

1
testhal/STM32F1xx/RTC/mcuconf.h
View File

@ -43,6 +43,7 @@
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCO STM32_MCO_NOCLOCK
#define STM32_RTC STM32_RTC_LSE
/*
* ADC driver system settings.