zcy
/
tinySA
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8462 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
Giovanni Di Sirio 2015-11-10 09:52:11 +00:00
parent 1ae8efe009
commit d80425b576
3 changed files with 144 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h
View File

@ -36,28 +36,6 @@
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_ADC_CLOCK_ENABLED TRUE
#define STM32_USB_CLOCK_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_2M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLMUL_VALUE 6
#define STM32_PLLDIV_VALUE 3
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
#define STM32_RTCPRE STM32_RTCPRE_DIV2
#define STM32_VOS STM32_VOS_1P8
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
/*
* SERIAL driver system settings.

6
os/hal/ports/STM32/STM32F7xx/hal_lld.h
View File

@ -293,19 +293,19 @@
#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */
#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */
#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/
#define STM32_PLLSAIDIVR_OFF 0xFFFFFFFF /**< LCD CLK is not required. */
#define STM32_PLLSAIDIVR_OFF 0xFFFFFFFFU /**< LCD CLK is not required. */
#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
#define STM32_SAI1SEL_SAIPLL (0 << 20) /**< SAI1 source is SAIPLL. */
#define STM32_SAI1SEL_I2SPLL (1 << 20) /**< SAI1 source is I2SPLL. */
#define STM32_SAI1SEL_CKIN (2 << 20) /**< SAI1 source is I2S_CKIN. */
#define STM32_SAI1SEL_OFF 0xFFFFFFFF /**< SAI1 clock is not required.*/
#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */
#define STM32_SAI2SEL_SAIPLL (0 << 22) /**< SAI2 source is SAIPLL. */
#define STM32_SAI2SEL_I2SPLL (1 << 22) /**< SAI2 source is I2SPLL. */
#define STM32_SAI2SEL_CKIN (2 << 22) /**< SAI2 source is I2S_CKIN. */
#define STM32_SAI2SEL_OFF 0xFFFFFFFF /**< SAI2 clock is not required.*/
#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */
#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */

132
os/hal/ports/STM32/STM32L4xx/hal_lld.h
View File

@ -339,23 +339,53 @@
#endif
/**
* @brief PLL multiplier value.
* @note The allowed values are 3, 4, 6, 8, 12, 16, 32, 48.
* @note The default value is calculated for a 32MHz system clock from
* the internal 16MHz HSI clock.
* @brief PLLM divider value.
* @note The allowed values are 1..8.
* @note The default value is calculated for a 80MHz system clock from
* an external 8MHz HSE clock.
*/
#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLMUL_VALUE 6
#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLM_VALUE 4
#endif
/**
* @brief PLL divider value.
* @note The allowed values are 2, 3, 4.
* @note The default value is calculated for a 32MHz system clock from
* the internal 16MHz HSI clock.
* @brief PLLN multiplier value.
* @note The allowed values are 8..86.
* @note The default value is calculated for a 216MHz system clock from
* an external 25MHz HSE clock.
*/
#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLDIV_VALUE 3
#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLN_VALUE 40
#endif
/**
* @brief PLLP divider value.
* @note The allowed values are 7, 17.
* @note The default value is calculated for a 216MHz system clock from
* an external 25MHz HSE clock.
*/
#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLP_VALUE 2
#endif
/**
* @brief PLLQ divider value.
* @note The allowed values are 2, 4, 6, 8.
* @note The default value is calculated for a 216MHz system clock from
* an external 25MHz HSE clock.
*/
#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLQ_VALUE 9
#endif
/**
* @brief PLLR divider value.
* @note The allowed values are 2, 4, 6, 8.
* @note The default value is calculated for a 216MHz system clock from
* an external 25MHz HSE clock.
*/
#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLR_VALUE 9
#endif
/**
@ -402,12 +432,90 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#endif
/**
* @brief PLLSAI1N multiplier value.
* @note The allowed values are 8..86.
*/
#if !defined(STM32_PLLSAI1N_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1N_VALUE 40
#endif
/**
* @brief PLLSAI1P divider value.
* @note The allowed values are 7, 17.
*/
#if !defined(STM32_PLLSAI1P_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1P_VALUE 7
#endif
/**
* @brief PLLSAI1Q divider value.
* @note The allowed values are 2, 4, 6, 8.
*/
#if !defined(STM32_PLLSAI1Q_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1Q_VALUE 4
#endif
/**
* @brief PLLSAI1R divider value.
* @note The allowed values are 2, 4, 6, 8.
*/
#if !defined(STM32_PLLSAI1R_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1R_VALUE 4
#endif
/**
* @brief PLLSAI2N multiplier value.
* @note The allowed values are 8..86.
*/
#if !defined(STM32_PLLSAI2N_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2N_VALUE 40
#endif
/**
* @brief PLLSAI2P divider value.
* @note The allowed values are 7, 17.
*/
#if !defined(STM32_PLLSAI2P_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2P_VALUE 7
#endif
/**
* @brief PLLSAI2Q divider value.
* @note The allowed values are 2, 4, 6, 8.
*/
#if !defined(STM32_PLLSAI2Q_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2Q_VALUE 4
#endif
/**
* @brief PLLSAI2R divider value.
* @note The allowed values are 2, 4, 6, 8.
*/
#if !defined(STM32_PLLSAI2R_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2R_VALUE 4
#endif
/**
* @brief RTC/LCD clock source.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCSEL STM32_RTCSEL_LSE
#endif
/**
* @brief SAI1SEL value (SAI1 clock source).
*/
#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#endif
/**
* @brief SAI2SEL value (SAI2 clock source).
*/
#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#endif
/** @} */
/*===========================================================================*/