git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@457 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Generic ARM startup file for ChibiOS/RT (Atmel variant).
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*/
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.set MODE_USR, 0x10
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.set MODE_FIQ, 0x11
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.set MODE_IRQ, 0x12
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.set MODE_SVC, 0x13
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.set MODE_ABT, 0x17
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.set MODE_UND, 0x1B
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.set MODE_SYS, 0x1F
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.equ I_BIT, 0x80
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.equ F_BIT, 0x40
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.section .startup
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.code 32
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.balign 4
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/*
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* System entry points.
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*/
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_start:
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ldr pc, _reset
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ldr pc, _undefined
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ldr pc, _swi
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ldr pc, _prefetch
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ldr pc, _abort
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nop
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ldr pc, [pc,#-0xF20] /* AIC - AIC_IVR */
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ldr pc, [pc,#-0xF20] /* AIC - AIC_FVR */
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_reset:
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.word ResetHandler
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_undefined:
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.word UndHandler
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_swi:
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.word SwiHandler
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_prefetch:
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.word PrefetchHandler
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_abort:
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.word AbortHandler
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_fiq:
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.word FiqHandler
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.word 0
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.word 0
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/*
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* Reset handler.
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*/
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.text
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ResetHandler:
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/*
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* Stack pointers initialization.
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*/
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ldr r0, =__ram_end__
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/* Undefined */
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msr CPSR_c, #MODE_UND | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__und_stack_size__
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sub r0, r0, r1
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/* Abort */
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msr CPSR_c, #MODE_ABT | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__abt_stack_size__
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sub r0, r0, r1
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/* FIQ */
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msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__fiq_stack_size__
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sub r0, r0, r1
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/* IRQ */
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msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__irq_stack_size__
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sub r0, r0, r1
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/* Supervisor */
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msr CPSR_c, #MODE_SVC | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__svc_stack_size__
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sub r0, r0, r1
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/* System */
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msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
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mov sp, r0
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// ldr r1, =__sys_stack_size__
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// sub r0, r0, r1
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/*
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* Data initialization.
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* NOTE: It assumes that the DATA size is a multiple of 4.
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*/
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ldr r1, =_textdata
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ldr r2, =_data
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ldr r3, =_edata
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dataloop:
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cmp r2, r3
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ldrlo r0, [r1], #4
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strlo r0, [r2], #4
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blo dataloop
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/*
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* BSS initialization.
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* NOTE: It assumes that the BSS size is a multiple of 4.
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*/
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mov r0, #0
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ldr r1, =_bss_start
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ldr r2, =_bss_end
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bssloop:
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cmp r1, r2
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strlo r0, [r1], #4
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blo bssloop
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/*
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* Application-provided HW initialization routine.
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*/
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#ifndef THUMB_NO_INTERWORKING
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bl hwinit
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/*
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* main(0, NULL).
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*/
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mov r0, #0
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mov r1, r0
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bl main
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bl chSysHalt
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#else
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add r0, pc, #1
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bx r0
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.code 16
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bl hwinit
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mov r0, #0
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mov r1, r0
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bl main
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bl chSysHalt
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.code 32
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#endif
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.weak UndHandler
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.globl UndHandler
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UndHandler:
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.weak SwiHandler
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.globl SwiHandler
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SwiHandler:
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.weak PrefetchHandler
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.globl PrefetchHandler
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PrefetchHandler:
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.weak AbortHandler
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.globl AbortHandler
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AbortHandler:
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.weak FiqHandler
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.globl FiqHandler
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FiqHandler:
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.loop: b .loop
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@ -79,6 +79,11 @@ Win32-MinGW - ChibiOS/RT simulator and demo into a WIN32 process,
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initializaiton phase: hwinit0, the late initialization phase is now named
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initializaiton phase: hwinit0, the late initialization phase is now named
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hwinit1. The demo now initializes the PLL before initializing the BSS and
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hwinit1. The demo now initializes the PLL before initializing the BSS and
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DATA segments, this greatly optimizes the system start up time.
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DATA segments, this greatly optimizes the system start up time.
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- NEW: Unified ARM7 startup file, it is shared by the LPC and SAM7 demo
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projects. The new startup file implements early and late initialization
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phases as described above for the CM3 startup file.
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The architecture specific vector tables are now encapsulated into the
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vectors.s file.
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- Modified the STM32 demo makefile to use the latest YAGARTO toolchain as
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- Modified the STM32 demo makefile to use the latest YAGARTO toolchain as
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default (arm-elf-gcc).
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default (arm-elf-gcc).
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