diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld
index 79acb2048..62c991c4a 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld
@@ -87,7 +87,7 @@ SECTIONS
     PROVIDE(__exidx_start = .);
     *(.ARM.exidx* .gnu.linkonce.armexidx.*)
     PROVIDE(__exidx_end = .);
-   } > flash
+  } > flash
 
   .eh_frame_hdr :
   {
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/MK20DX128.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/MK20DX128.ld
new file mode 100644
index 000000000..99fefeaf7
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/MK20DX128.ld
@@ -0,0 +1,165 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+                                      ---
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes ChibiOS/RT, without being obliged to provide
+    the source code for any proprietary components. See the file exception.txt
+    for full details of how and when the exception can be applied.
+*/
+
+/*
+ * MK20DX128 memory setup.
+ */
+__main_stack_size__     = 0x0400;
+__process_stack_size__  = 0x0400;
+
+ENTRY(Reset_Handler)
+
+MEMORY
+{
+  flash0   : org = 0x00000000, len = 0xF8
+  flashcfg : org = 0x00000400, len = 0x10
+  flash    : org = 0x00000410, len = 128k - 0x410
+  ram      : org = 0x1FFFE000, len = 16k
+}
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = LENGTH(ram);
+__ram_end__             = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+  . = 0;
+
+  .isr : ALIGN(4) SUBALIGN(4)
+  {
+    KEEP(*(vectors))
+  } > flash0
+
+  .cfmprotect : ALIGN(4) SUBALIGN(4)
+  {
+    KEEP(*(.cfmconfig))
+  } > flashcfg
+
+  _text = .;
+
+  constructors : ALIGN(4) SUBALIGN(4)
+  {
+    PROVIDE(__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE(__init_array_end = .);
+  } > flash
+
+  destructors : ALIGN(4) SUBALIGN(4)
+  {
+    PROVIDE(__fini_array_start = .);
+    KEEP(*(.fini_array))
+    KEEP(*(SORT(.fini_array.*)))
+    PROVIDE(__fini_array_end = .);
+  } > flash
+
+  .text : ALIGN(4) SUBALIGN(4)
+  {
+    *(.text)
+    *(.text.*)
+    *(.rodata)
+    *(.rodata.*)
+    *(.glue_7t)
+    *(.glue_7)
+    *(.gcc*)
+  } > flash
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > flash
+
+  .ARM.exidx : {
+    PROVIDE(__exidx_start = .);
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    PROVIDE(__exidx_end = .);
+  } > flash
+
+  .eh_frame_hdr :
+  {
+    *(.eh_frame_hdr)
+  } > flash
+
+  .eh_frame : ONLY_IF_RO
+  {
+    *(.eh_frame)
+  } > flash
+
+  .textalign : ONLY_IF_RO
+  {
+    . = ALIGN(8);
+  } > flash
+
+  _etext = .;
+  _textdata = _etext;
+
+  .stacks :
+  {
+    . = ALIGN(8);
+    __main_stack_base__ = .;
+    . += __main_stack_size__;
+    . = ALIGN(8);
+    __main_stack_end__ = .;
+    __process_stack_base__ = .;
+    __main_thread_stack_base__ = .;
+    . += __process_stack_size__;
+    . = ALIGN(8);
+    __process_stack_end__ = .;
+    __main_thread_stack_end__ = .;
+  } > ram
+
+  .data :
+  {
+    . = ALIGN(4);
+    PROVIDE(_data = .);
+    *(.data)
+    . = ALIGN(4);
+    *(.data.*)
+    . = ALIGN(4);
+    *(.ramtext)
+    . = ALIGN(4);
+    PROVIDE(_edata = .);
+  } > ram AT > flash
+
+  .bss :
+  {
+    . = ALIGN(4);
+    PROVIDE(_bss_start = .);
+    *(.bss)
+    . = ALIGN(4);
+    *(.bss.*)
+    . = ALIGN(4);
+    *(COMMON)
+    . = ALIGN(4);
+    PROVIDE(_bss_end = .);
+  } > ram
+}
+
+PROVIDE(end = .);
+_end            = .;
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;
diff --git a/os/common/ports/ARMCMx/devices/K20x/cmparams.h b/os/common/ports/ARMCMx/devices/K20x/cmparams.h
new file mode 100644
index 000000000..c1589b9c2
--- /dev/null
+++ b/os/common/ports/ARMCMx/devices/K20x/cmparams.h
@@ -0,0 +1,87 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    GCC/ARMCMx/MK20Dx/cmparams.h
+ * @brief   ARM Cortex-M4 parameters for the Kinetis MK20Dx.
+ *
+ * @defgroup ARMCMx_MK20Dx Kinetis MK20Dx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ *          Kinetis MK20Dx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief   Cortex core model.
+ */
+#define CORTEX_MODEL            CORTEX_M4
+
+/**
+ * @brief   Systick unit presence.
+ */
+#define CORTEX_HAS_ST           TRUE
+
+/**
+ * @brief   Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU          FALSE
+
+/**
+ * @brief   Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU          FALSE
+
+/**
+ * @brief   Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS    4
+
+/**
+ * @brief   Number of interrupt vectors.
+ * @note    This number does not include the 16 system vectors and must be
+ *          rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS      32
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+   from this header because we need this file to be usable also from
+   assembler source files. We verify that the info matches instead.*/
+#include "mk20d5.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */