git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8212 35acf78f-673a-0410-8e92-d51de3d6d3f4
parent
a59a43bc28
commit
d46360e613
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@ -241,15 +241,21 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
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* @note On devices without data cache this function does nothing.
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* @note The function takes care of cache lines alignment.
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*
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* @param[in] addr address of the DMA buffer
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* @param[in] size size of the DMA buffer
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* @param[in] saddr start address of the DMA buffer, inclusive
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* @param[in] eaddr end address of the DMA buffer, not inclusive
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*
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* @api
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*/
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#define dmaBufferInvalidate(addr, size) { \
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uint32_t *aaddr = (uint32_t *)(((uint32_t)(addr)) & ~0x1FU); \
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uint32_t asize = (uint32_t)((((size) - 1) | 0x1FU) + 1U); \
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SCB_CleanInvalidateDCache_by_Addr(aaddr, asize); \
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#define dmaBufferInvalidate(saddr, eaddr) { \
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uint8_t *start = (uint8_t *)(((uint32_t)(saddr)) & ~0x1FU); \
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uint8_t *end = (uint8_t *)(((((uint32_t)(eaddr)) - 1U) | 0x1FU) + 1U); \
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__DSB(); \
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while (start < end) { \
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SCB->DCCIMVAC = (uint32_t)start; \
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start += 32U; \
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} \
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__DSB(); \
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__ISB(); \
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}
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#else
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#define dmaBufferInvalidate(addr, size) { \
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@ -141,10 +141,8 @@ void hal_lld_init(void) {
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0x20000000U,
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MPU_RASR_ATTR_AP_RW_RW |
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MPU_RASR_ATTR_CACHEABLE_WT_NWA |
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MPU_RNR_REGION(1) |
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MPU_RNR_REGION(5) |
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MPU_RNR_REGION(6) |
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MPU_RNR_REGION(7) |
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MPU_RASR_SRD_DISABLE_SUB0 | MPU_RASR_SRD_DISABLE_SUB5 |
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MPU_RASR_SRD_DISABLE_SUB6 | MPU_RASR_SRD_DISABLE_SUB7 |
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MPU_RASR_SIZE_512K |
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MPU_RASR_ENABLE);
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mpuEnable(MPU_CTRL_PRIVDEFENA);
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@ -49,7 +49,7 @@ static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
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(void)adcp;
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/* DMA buffer invalidation because data cache.*/
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dmaBufferInvalidate(buffer, n * ADC_GRP1_NUM_CHANNELS);
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dmaBufferInvalidate(buffer, buffer + n * ADC_GRP1_NUM_CHANNELS);
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/* Updating counters.*/
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if (samples1 == buffer) {
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