diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
index e20ebe637..ab46ecf43 100644
--- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
+++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
@@ -241,15 +241,21 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
  * @note    On devices without data cache this function does nothing.
  * @note    The function takes care of cache lines alignment.
  *
- * @param[in] addr      address of the DMA buffer
- * @param[in] size      size of the DMA buffer
+ * @param[in] saddr     start address of the DMA buffer, inclusive
+ * @param[in] eaddr     end address of the DMA buffer, not inclusive
  *
  * @api
  */
-#define dmaBufferInvalidate(addr, size) {                                   \
-  uint32_t *aaddr = (uint32_t *)(((uint32_t)(addr)) & ~0x1FU);              \
-  uint32_t asize  = (uint32_t)((((size) - 1) | 0x1FU) + 1U);                \
-  SCB_CleanInvalidateDCache_by_Addr(aaddr, asize);                          \
+#define dmaBufferInvalidate(saddr, eaddr) {                                 \
+  uint8_t *start = (uint8_t *)(((uint32_t)(saddr)) & ~0x1FU);               \
+  uint8_t *end = (uint8_t *)(((((uint32_t)(eaddr)) - 1U) | 0x1FU) + 1U);    \
+  __DSB();                                                                  \
+  while (start < end) {                                                     \
+    SCB->DCCIMVAC = (uint32_t)start;                                        \
+    start += 32U;                                                           \
+  }                                                                         \
+  __DSB();                                                                  \
+  __ISB();                                                                  \
 }
 #else
 #define dmaBufferInvalidate(addr, size) {                                   \
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
index 1c2c2e364..e5f74ed8c 100644
--- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
@@ -141,10 +141,8 @@ void hal_lld_init(void) {
                      0x20000000U,
                      MPU_RASR_ATTR_AP_RW_RW |
                      MPU_RASR_ATTR_CACHEABLE_WT_NWA |
-                     MPU_RNR_REGION(1) |
-                     MPU_RNR_REGION(5) |
-                     MPU_RNR_REGION(6) |
-                     MPU_RNR_REGION(7) |
+                     MPU_RASR_SRD_DISABLE_SUB0 | MPU_RASR_SRD_DISABLE_SUB5 |
+                     MPU_RASR_SRD_DISABLE_SUB6 | MPU_RASR_SRD_DISABLE_SUB7 |
                      MPU_RASR_SIZE_512K |
                      MPU_RASR_ENABLE);
   mpuEnable(MPU_CTRL_PRIVDEFENA);
diff --git a/testhal/STM32/STM32F7xx/GPT-ADC-SPI-PWM-ICU/main.c b/testhal/STM32/STM32F7xx/GPT-ADC-SPI-PWM-ICU/main.c
index 0ff6372bf..50b0948a7 100644
--- a/testhal/STM32/STM32F7xx/GPT-ADC-SPI-PWM-ICU/main.c
+++ b/testhal/STM32/STM32F7xx/GPT-ADC-SPI-PWM-ICU/main.c
@@ -49,7 +49,7 @@ static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
   (void)adcp;
 
   /* DMA buffer invalidation because data cache.*/
-  dmaBufferInvalidate(buffer, n * ADC_GRP1_NUM_CHANNELS);
+  dmaBufferInvalidate(buffer, buffer + n * ADC_GRP1_NUM_CHANNELS);
 
   /* Updating counters.*/
   if (samples1 == buffer) {