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Added preliminary CodeWarrior stuff. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8505 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
Giovanni Di Sirio 2015-11-17 13:41:25 +00:00
parent d8e6d79320
commit d0f1e68932
4 changed files with 468 additions and 0 deletions
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BIN
demos/SPC5/RT-SPC560D-EVB-CW/cw/ch/ch.mcp Normal file
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demos/SPC5/RT-SPC560D-EVB-CW/main.c Normal file
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void main(void) {
}

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os/common/ports/e200/compilers/CW/crt0.s Normal file
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/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file PPC/crt0.s
* @brief Generic PowerPC startup file for ChibiOS.
*
* @addtogroup PPC_CORE
* @{
*/
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
#if !defined(FALSE) || defined(__DOXYGEN__)
#define FALSE 0
#endif
#if !defined(TRUE) || defined(__DOXYGEN__)
#define TRUE 1
#endif
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/**
* @brief Stack segments initialization switch.
*/
#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
#define CRT0_STACKS_FILL_PATTERN 0x55555555
#endif
/**
* @brief Stack segments initialization switch.
*/
#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
#define CRT0_INIT_STACKS TRUE
#endif
/**
* @brief DATA segment initialization switch.
*/
#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
#define CRT0_INIT_DATA TRUE
#endif
/**
* @brief BSS segment initialization switch.
*/
#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
#define CRT0_INIT_BSS TRUE
#endif
/**
* @brief Constructors invocation switch.
*/
#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
#define CRT0_CALL_CONSTRUCTORS TRUE
#endif
/**
* @brief Destructors invocation switch.
*/
#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
#define CRT0_CALL_DESTRUCTORS TRUE
#endif
/*===========================================================================*/
/* Code section. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
.section .crt0, "ax"
.align 2
.globl _boot_address
.type _boot_address, @function
_boot_address:
/* Stack setup.*/
e_lis r1, __process_stack_end__@h
e_or2i r1, __process_stack_end__@l
se_li r0, 0
e_stwu r0, -8(r1)
/* Small sections registers initialization.*/
e_lis r2, __sdata2_start__@h
e_or2i r2, __sdata2_start__@l
e_lis r13, __sdata_start__@h
e_or2i r13, __sdata_start__@l
/* Early initialization.*/
e_bl __early_init
#if CRT0_INIT_STACKS == TRUE
/* Stacks fill pattern.*/
e_lis r7, CRT0_STACKS_FILL_PATTERN@h
e_or2i r7, CRT0_STACKS_FILL_PATTERN@l
/* IRQ Stack initialization. Note, the architecture does not use this
stack, the size is usually zero. An OS can have special SW handling
and require this. A 4 bytes alignment is assmend and required.*/
e_lis r4, __irq_stack_base__@h
e_or2i r4, __irq_stack_base__@l
e_lis r5, __irq_stack_end__@h
e_or2i r5, __irq_stack_end__@l
.irqsloop:
se_cmpl r4, r5
se_bge .irqsend
se_stw r7, 0(r4)
se_addi r4, 4
se_b .irqsloop
.irqsend:
/* Process Stack initialization. Note, does not overwrite the already
written EABI frame. A 4 bytes alignment is assmend and required.*/
e_lis r4, __process_stack_base__@h
e_or2i r4, __process_stack_base__@l
e_lis r5, (__process_stack_end__ - 8)@h
e_or2i r5, (__process_stack_end__ - 8)@l
.prcsloop:
se_cmpl r4, r5
se_bge .prcsend
se_stw r7, 0(r4)
se_addi r4, 4
se_b .prcsloop
.prcsend:
#endif
#if CRT0_INIT_BSS == TRUE
/* BSS clearing.*/
e_lis r4, __bss_start__@h
e_or2i r4, __bss_start__@l
e_lis r5, __bss_end__@h
e_or2i r5, __bss_end__@l
se_li r7, 0
.bssloop:
se_cmpl r4, r5
se_bge .bssend
se_stw r7, 0(r4)
se_addi r4, 4
se_b .bssloop
.bssend:
#endif
#if CRT0_INIT_DATA == TRUE
/* DATA initialization.*/
e_lis r4, __romdata_start__@h
e_or2i r4, __romdata_start__@l
e_lis r5, __data_start__@h
e_or2i r5, __data_start__@l
e_lis r6, __data_end__@h
e_or2i r6, __data_end__@l
.dataloop:
se_cmpl r5, r6
se_bge .dataend
se_lwz r7, 0(r4)
se_addi r4, 4
se_stw r7, 0(r5)
se_addi r5, 4
se_b .dataloop
.dataend:
#endif
/* Late initialization.*/
e_bl __late_init
#if CRT0_CALL_CONSTRUCTORS == TRUE
/* Constructors invocation.*/
e_lis r4, __init_array_start@h
e_or2i r4, __init_array_start@l
e_lis r5, __init_array_end@h
e_or2i r5, __init_array_end@l
.iniloop:
se_cmpl r4, r5
se_bge .iniend
se_lwz r6, 0(r4)
se_mtctr r6
se_addi r4, 4
se_bctrl
se_b .iniloop
.iniend:
#endif
/* Main program invocation.*/
e_bl main
#if CRT0_CALL_DESTRUCTORS == TRUE
/* Destructors invocation.*/
e_lis r4, __fini_array_start@h
e_or2i r4, __fini_array_start@l
e_lis r5, __fini_array_end@h
e_or2i r5, __fini_array_end@l
.finiloop:
se_cmpl r4, r5
se_bge .finiend
se_lwz r6, 0(r4)
se_mtctr r6
se_addi r4, 4
se_bctrl
se_b .finiloop
.finiend:
#endif
/* Branching to the defined exit handler.*/
e_b __default_exit
/* Default main exit code, infinite loop.*/
.weak __default_exit
.globl __default_exit
.type __default_exit, @function
__default_exit:
se_b __default_exit
/* Default early initialization code, none.*/
.weak __early_init
.globl __early_init
.type __early_init, @function
__early_init:
se_blr
/* Default late initialization code, none.*/
.weak __late_init
.globl __late_init
.type __late_init, @function
__late_init:
se_blr
#endif /* !defined(__DOXYGEN__) */
/** @} */

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os/common/ports/e200/devices/SPC560Dxx/boot_cw.s Normal file
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/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file SPC560Dxx/boot.s
* @brief SPC560Dxx boot-related code.
*
* @addtogroup PPC_BOOT
* @{
*/
#include "boot.h"
#if !defined(__DOXYGEN__)
/* BAM record.*/
.section .boot, "ax"
.long 0x015A0000
.long _reset_address
.align 2
.globl _reset_address
.type _reset_address, @function
_reset_address:
#if BOOT_PERFORM_CORE_INIT
se_bl _coreinit
#endif
se_bl _ivinit
#if BOOT_RELOCATE_IN_RAM
/*
* Image relocation in RAM.
*/
lis r4, __ram_reloc_start__@h
ori r4, r4, __ram_reloc_start__@l
lis r5, __ram_reloc_dest__@h
ori r5, r5, __ram_reloc_dest__@l
lis r6, __ram_reloc_end__@h
ori r6, r6, __ram_reloc_end__@l
.relloop:
cmpl cr0, r4, r6
bge cr0, .relend
lwz r7, 0(r4)
addi r4, r4, 4
stw r7, 0(r5)
addi r5, r5, 4
b .relloop
.relend:
lis r3, _boot_address@h
ori r3, r3, _boot_address@l
mtctr r3
bctrl
#else
e_b _boot_address
#endif
#if BOOT_PERFORM_CORE_INIT
.align 2
_coreinit:
/*
* RAM clearing, this device requires a write to all RAM location in
* order to initialize the ECC detection hardware, this is going to
* slow down the startup but there is no way around.
*/
xor r0, r0, r0
xor r1, r1, r1
xor r2, r2, r2
xor r3, r3, r3
xor r4, r4, r4
xor r5, r5, r5
xor r6, r6, r6
xor r7, r7, r7
xor r8, r8, r8
xor r9, r9, r9
xor r10, r10, r10
xor r11, r11, r11
xor r12, r12, r12
xor r13, r13, r13
xor r14, r14, r14
xor r15, r15, r15
xor r16, r16, r16
xor r17, r17, r17
xor r18, r18, r18
xor r19, r19, r19
xor r20, r20, r20
xor r21, r21, r21
xor r22, r22, r22
xor r23, r23, r23
xor r24, r24, r24
xor r25, r25, r25
xor r26, r26, r26
xor r27, r27, r27
xor r28, r28, r28
xor r29, r29, r29
xor r30, r30, r30
xor r31, r31, r31
e_lis r4, __ram_start__@h
e_or2i r4, __ram_start__@l
e_lis r5, __ram_end__@h
e_or2i r5, __ram_end__@l
.cleareccloop:
se_cmpl r4, r5
se_bge .cleareccend
e_stmw r16, 0(r4)
e_addi r4, r4, 64
se_b .cleareccloop
.cleareccend:
/*
* Branch prediction enabled.
*/
e_li r3, BOOT_BUCSR_DEFAULT
mtspr 1013, r3 /* BUCSR */
se_blr
#endif /* BOOT_PERFORM_CORE_INIT */
/*
* Exception vectors initialization.
*/
.align 2
_ivinit:
/* MSR initialization.*/
e_lis r3, BOOT_MSR_DEFAULT@h
e_ori r3, r3, BOOT_MSR_DEFAULT@l
mtMSR r3
/* IVPR initialization.*/
e_lis r3, __ivpr_base__@h
e_or2i r3, __ivpr_base__@l
mtIVPR r3
se_blr
.section .ivors, "ax"
.globl IVORS
IVORS:
e_b _IVOR0
.align 4
e_b _IVOR1
.align 4
e_b _IVOR2
.align 4
e_b _IVOR3
.align 4
e_b _IVOR4
.align 4
e_b _IVOR5
.align 4
e_b _IVOR6
.align 4
e_b _IVOR7
.align 4
e_b _IVOR8
.align 4
e_b _IVOR9
.align 4
e_b _IVOR10
.align 4
e_b _IVOR11
.align 4
e_b _IVOR12
.align 4
e_b _IVOR13
.align 4
e_b _IVOR14
.align 4
e_b _IVOR15
.section .handlers, "ax"
/*
* Default IVOR handlers.
*/
.align 2
.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
.weak _unhandled_exception
_IVOR0:
_IVOR1:
_IVOR2:
_IVOR3:
_IVOR5:
_IVOR6:
_IVOR7:
_IVOR8:
_IVOR9:
_IVOR11:
_IVOR12:
_IVOR13:
_IVOR14:
_IVOR15:
_unhandled_exception:
se_b _unhandled_exception
#endif /* !defined(__DOXYGEN__) */
/** @} */