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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3044 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2011-06-14 15:09:28 +00:00
parent a746de44e1
commit d0dfc3715a
6 changed files with 2208 additions and 38 deletions
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2
boards/ST_STM32L_DISCOVERY/board.h
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@ -36,7 +36,7 @@
* NOTE: The HSE crystal is not fitted by default on the board. * NOTE: The HSE crystal is not fitted by default on the board.
*/ */
#define STM32_LSECLK 32768 #define STM32_LSECLK 32768
#define STM32_HSECLK 8000000 #define STM32_HSECLK 0
/* /*
* MCU type as defined in the ST header file stm32l1xx.h. * MCU type as defined in the ST header file stm32l1xx.h.

12
demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h
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@ -35,7 +35,14 @@
/* /*
* HAL driver system settings. * HAL driver system settings.
*/ */
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_1P8 #define STM32_VOS STM32_VOS_1P8
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED TRUE
#define STM32_ADC_CLOCK_ENABLED TRUE
#define STM32_USB_CLOCK_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_2M #define STM32_MSIRANGE STM32_MSIRANGE_2M
#define STM32_SW STM32_SW_PLL #define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI #define STM32_PLLSRC STM32_PLLSRC_HSI
@ -44,7 +51,10 @@
#define STM32_HPRE STM32_HPRE_DIV1 #define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_MCO STM32_MCO_NOCLOCK #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_RTCSEL STM32_RTCSEL_LSE
#define STM32_RTCPRE STM32_RTCPRE_DIV2
/* /*
* ADC driver system settings. * ADC driver system settings.

6
os/hal/platforms/STM32/hal_lld.c
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@ -79,7 +79,7 @@ void hal_lld_init(void) {
/** /**
* @brief STM32 clocks and PLL initialization. * @brief STM32 clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h. * @note All the involved constants come from the file @p board.h.
* @note This function must be invoked only after the system reset. * @note This function should be invoked just after the system reset.
* *
* @special * @special
*/ */
@ -134,7 +134,7 @@ void stm32_clock_init(void) {
/* Flash setup and final clock selection. */ /* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
/* Switching on the configured clock source if it is different from HSI.*/ /* Switching to the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI) #if (STM32_SW != STM32_SW_HSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
@ -207,7 +207,7 @@ void stm32_clock_init(void) {
/* Flash setup and final clock selection. */ /* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
/* Switching on the configured clock source if it is different from HSI.*/ /* Switching to the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI) #if (STM32_SW != STM32_SW_HSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))

1843
os/hal/platforms/STM32L1xx/core_cm3.h Normal file
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File diff suppressed because it is too large Load Diff

83
os/hal/platforms/STM32L1xx/hal_lld.c
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@ -77,18 +77,93 @@ void hal_lld_init(void) {
} }
/** /**
* @brief STM32L1xx clocks and PLL initialization. * @brief STM32L1xx voltage, clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h. * @note All the involved constants come from the file @p board.h.
* @note This function must be invoked only after the system reset. * @note This function should be invoked just after the system reset.
* *
* @special * @special
*/ */
#if defined(STM32L1XX_MD) || defined(__DOXYGEN__) #if defined(STM32L1XX_MD) || defined(__DOXYGEN__)
/* /**
* Clocks initialization for the LD, MD and HD sub-families. * @brief Clocks and internal voltage initialization.
*/ */
void stm32_clock_init(void) { void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* Core voltage setup.*/
while ((PWR->CSR & PWR_CSR_VOSF) != 0)
; /* Waits until regulator is stable. */
PWR->CR = STM32_VOS;
while ((PWR->CSR & PWR_CSR_VOSF) != 0)
; /* Waits until regulator is stable. */
/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
always enabled because it is the fallback clock when PLL the fails.
Trim fields are not altered from reset values.*/
RCC->CFGR = 0;
RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE;
RCC->CSR = RCC_CSR_RMVF;
RCC->CR = RCC_CR_MSION;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
; /* Waits until MSI is stable. */
#if STM32_HSI_ENABLED
/* HSI activation.*/
RCC->CR |= RCC_CR_HSION;
while ((RCC->CR & RCC_CR_HSIRDY) == 0)
; /* Waits until HSI is stable. */
#endif
#if STM32_HSE_ENABLED
/* HSE activation.*/
RCC->CR |= RCC_CR_HSEON;
while ((RCC->CR & RCC_CR_HSERDY) == 0)
; /* Waits until HSE is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
; /* Waits until LSI is stable. */
#endif
#if STM32_LSE_ENABLED
/* LSE activation.*/
RCC->CSR |= RCC_CSR_LSEON;
while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL is stable. */
#endif
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CR |= STM32_RTCPRE;
RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
RCC->CSR |= STM32_RTCSEL;
/* Flash setup and final clock selection. */
#if defined(STM32_FLASHBITS1)
FLASH->ACR = STM32_FLASHBITS1;
#endif
#if defined(STM32_FLASHBITS2)
FLASH->ACR = STM32_FLASHBITS2;
#endif
/* Switching to the configured clock source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_MSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
#endif /* STM32_NO_INIT */
} }
#else #else
void stm32_clock_init(void) {} void stm32_clock_init(void) {}

300
os/hal/platforms/STM32L1xx/hal_lld.h
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@ -58,10 +58,17 @@
#define STM32_LSICLK 38000 /**< Low speed internal clock. */ #define STM32_LSICLK 38000 /**< Low speed internal clock. */
/* PWR_CR register bits definitions.*/ /* PWR_CR register bits definitions.*/
#define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */
#define STM32_VOS_1P2 (1 << 11) /**< Core voltage 1.2 Volts. */ #define STM32_VOS_1P2 (1 << 11) /**< Core voltage 1.2 Volts. */
#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */ #define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */
#define STM32_VOS_1P8 (3 << 11) /**< Core voltage 1.8 Volts. */ #define STM32_VOS_1P8 (3 << 11) /**< Core voltage 1.8 Volts. */
#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */
#define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */
#define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */
#define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */
#define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */
/* RCC_CFGR register bits definitions.*/ /* RCC_CFGR register bits definitions.*/
#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */ #define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
#define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */ #define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */
@ -93,28 +100,49 @@
#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ #define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ #define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ #define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define STM32_MCO_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */ #define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
#define STM32_MCO_HSI (2 << 24) /**< HSI clock on MCO pin. */ #define STM32_MCOSEL_HSI (2 << 24) /**< HSI clock on MCO pin. */
#define STM32_MCO_MSI (3 << 24) /**< MSI clock on MCO pin. */ #define STM32_MCOSEL_MSI (3 << 24) /**< MSI clock on MCO pin. */
#define STM32_MCO_HSE (4 << 24) /**< HSE clock on MCO pin. */ #define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCO_PLL (5 << 24) /**< PLL clock on MCO pin. */ #define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
#define STM32_MCO_LSI (6 << 24) /**< LSI clock on MCO pin. */ #define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
#define STM32_MCO_LSE (7 << 24) /**< LSE clock on MCO pin. */ #define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 1. */
#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 1. */
#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 1. */
#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 1. */
/* RCC_ICSCR register bits definitions.*/ /* RCC_ICSCR register bits definitions.*/
#define STM32_MSIRANGE_64K (0 << 13) /* 64KHz nominal. */ #define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */
#define STM32_MSIRANGE_128K (1 << 13) /* 128KHz nominal. */ #define STM32_MSIRANGE_64K (0 << 13) /**< 64KHz nominal. */
#define STM32_MSIRANGE_256K (2 << 13) /* 256KHz nominal. */ #define STM32_MSIRANGE_128K (1 << 13) /**< 128KHz nominal. */
#define STM32_MSIRANGE_512K (3 << 13) /* 512KHz nominal. */ #define STM32_MSIRANGE_256K (2 << 13) /**< 256KHz nominal. */
#define STM32_MSIRANGE_1M (4 << 13) /* 1MHz nominal. */ #define STM32_MSIRANGE_512K (3 << 13) /**< 512KHz nominal. */
#define STM32_MSIRANGE_2M (5 << 13) /* 2MHz nominal. */ #define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */
#define STM32_MSIRANGE_4M (6 << 13) /* 4MHz nominal. */ #define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */
#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */
/* RCC_CSR register bits definitions.*/
#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */
#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */
#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */
#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */
/*===========================================================================*/ /*===========================================================================*/
/* Driver pre-compile time settings. */ /* Driver pre-compile time settings. */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Disables the PWR/RCC initialization in the HAL.
*/
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
#define STM32_NO_INIT FALSE
#endif
/** /**
* @brief Core voltage selection. * @brief Core voltage selection.
* @note This setting affects all the performance and clock related * @note This setting affects all the performance and clock related
@ -125,6 +153,48 @@
#define STM32_VOS STM32_VOS_1P8 #define STM32_VOS STM32_VOS_1P8
#endif #endif
/**
* @brief Enables or disables the HSI clock source.
*/
#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
#define STM32_HSI_ENABLED TRUE
#endif
/**
* @brief Enables or disables the LSI clock source.
*/
#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
#define STM32_LSI_ENABLED TRUE
#endif
/**
* @brief Enables or disables the HSE clock source.
*/
#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
#define STM32_HSE_ENABLED FALSE
#endif
/**
* @brief Enables or disables the LSE clock source.
*/
#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
#define STM32_LSE_ENABLED FALSE
#endif
/**
* @brief ADC clock setting.
*/
#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
#define STM32_ADC_CLOCK_ENABLED TRUE
#endif
/**
* @brief USB clock setting.
*/
#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
#define STM32_USB_CLOCK_ENABLED TRUE
#endif
/** /**
* @brief MSI frequency setting. * @brief MSI frequency setting.
*/ */
@ -170,8 +240,8 @@
* @note The default value is calculated for a 32MHz system clock from * @note The default value is calculated for a 32MHz system clock from
* the internal 16MHz HSI clock. * the internal 16MHz HSI clock.
*/ */
#if !defined(STM32_DIVMUL_VALUE) || defined(__DOXYGEN__) #if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__)
#define STM32_DIVMUL_VALUE 3 #define STM32_PLLDIV_VALUE 3
#endif #endif
/** /**
@ -198,10 +268,31 @@
#endif #endif
/** /**
* @brief MCO pin setting. * @brief MCO clock source.
*/ */
#if !defined(STM32_MCO) || defined(__DOXYGEN__) #if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
#define STM32_MCO STM32_MCO_NOCLOCK #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#endif
/**
* @brief MCO divider setting.
*/
#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#endif
/**
* @brief Clock source for the RTC/LCD.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCSEL STM32_RTCSEL_LSE
#endif
/**
* @brief HSE divider toward RTC setting.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCPRE STM32_RTCPRE_DIV2
#endif #endif
/*===========================================================================*/ /*===========================================================================*/
@ -251,13 +342,77 @@
#error "invalid STM32_VOS value specified" #error "invalid STM32_VOS value specified"
#endif #endif
/* HSI related checks.*/
#if STM32_HSI_ENABLED
#if !STM32_HSI_AVAILABLE
#error "impossible to activate HSI under the current voltage settings"
#endif
#else /* !STM32_HSI_ENABLED */
#if STM32_ADC_CLOCK_ENABLED || \
(STM32_SW == STM32_SW_HSI) || \
((STM32_SW == STM32_SW_PLL) && \
(STM32_PLLSRC == STM32_PLLSRC_HSI)) || \
(STM32_MCOSEL == STM32_MCOSEL_HSI) || \
((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
(STM32_PLLSRC == STM32_PLLSRC_HSI))
#error "required HSI clock is not enabled"
#endif
#endif /* !STM32_HSI_ENABLED */
/* HSE related checks.*/
#if STM32_HSE_ENABLED
#if STM32_HSECLK == 0
#error "impossible to activate HSE"
#endif
#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX) #if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX)
#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)" #error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)"
#endif #endif
#else /* !#if STM32_HSE_ENABLED */
#if (STM32_SW == STM32_SW_HSE) || \
((STM32_SW == STM32_SW_PLL) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
(STM32_MCOSEL == STM32_MCOSEL_HSE) || \
((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
(STM_RTC_SOURCE == STM32_RTCSEL_HSEDIV)
#error "required HSE clock is not enabled"
#endif
#endif /* !#if STM32_HSE_ENABLED */
/* LSI related checks.*/
#if STM32_LSI_ENABLED
#else /* !STM32_LSI_ENABLED */
#if STM_RTCCLK == STM32_LSICLK
#error "required LSI clock is not enabled"
#endif
#endif /* !STM32_LSI_ENABLED */
/* LSE related checks.*/
#if STM32_LSE_ENABLED
#if (STM32_LSECLK == 0)
#error "impossible to activate LSE"
#endif
#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000) #if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)
#error "STM32_LSECLK outside acceptable range (1...1000KHz)" #error "STM32_LSECLK outside acceptable range (1...1000KHz)"
#endif #endif
#else /* !#if STM32_LSE_ENABLED */
#if STM_RTCCLK == STM32_LSECLK
#error "required LSE clock is not enabled"
#endif
#endif /* !#if STM32_LSE_ENABLED */
/* PLL related checks.*/
#if STM32_USB_CLOCK_ENABLED || \
(STM32_SW == STM32_SW_PLL) || \
(STM32_MCOSEL == STM32_MCOSEL_PLL) || \
defined(__DOXYGEN__)
/**
* @brief PLL activation flag.
*/
#define STM32_ACTIVATE_PLL TRUE
#else
#define STM32_ACTIVATE_PLL FALSE
#endif
/** /**
* @brief PLLMUL field. * @brief PLLMUL field.
@ -303,11 +458,6 @@
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLCLKIN STM32_HSECLK #define STM32_PLLCLKIN STM32_HSECLK
#elif STM32_PLLSRC == STM32_PLLSRC_HSI #elif STM32_PLLSRC == STM32_PLLSRC_HSI
/* Verifies the HSI clock availability if the PLL used and requires HSI as
input.*/
#if !STM32_HSI_AVAILABLE && (STM32_SW == STM32_SW_PLL)
#error "HSI clock not available in low voltage mode (1.2V)."
#endif
#define STM32_PLLCLKIN STM32_HSICLK #define STM32_PLLCLKIN STM32_HSICLK
#else #else
#error "invalid STM32_PLLSRC value specified" #error "invalid STM32_PLLSRC value specified"
@ -338,19 +488,43 @@
#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)" #error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)"
#endif #endif
/**
* @brief MSI frequency.
* @note Values are taken from the STM8Lxx datasheet.
*/
#if STM32_MSIRANGE == STM32_MSIRANGE_64K
#define STM32_MSICLK 65500
#elif STM32_MSIRANGE == STM32_MSIRANGE_128K
#define STM32_MSICLK 131000
#elif STM32_MSIRANGE == STM32_MSIRANGE_256K
#define STM32_MSICLK 262000
#elif STM32_MSIRANGE == STM32_MSIRANGE_512K
#define STM32_MSICLK 524000
#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
#define STM32_MSICLK 1050000
#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
#define STM32_MSICLK 2100000
#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
#define STM32_MSICLK 4200000
#else
#error "invalid STM32_MSIRANGE value specified"
#endif
/** /**
* @brief System clock source. * @brief System clock source.
*/ */
#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) #if STM32_NO_INIT || defined(__DOXYGEN__)
#define STM32_SYSCLK STM32_PLLCLKOUT #define STM32_SYSCLK 2100000
#elif (STM32_SW == STM32_SW_MSI) #elif (STM32_SW == STM32_SW_MSI)
#define STM32_SYSCLK STM32_MSICLK #define STM32_SYSCLK STM32_MSICLK
#elif (STM32_SW == STM32_SW_HSI) #elif (STM32_SW == STM32_SW_HSI)
#define STM32_SYSCLK STM32_HSICLK #define STM32_SYSCLK STM32_HSICLK
#elif (STM32_SW == STM32_SW_HSE) #elif (STM32_SW == STM32_SW_HSE)
#define STM32_SYSCLK STM32_HSECLK #define STM32_SYSCLK STM32_HSECLK
#elif (STM32_SW == STM32_SW_PLL)
#define STM32_SYSCLK STM32_PLLCLKOUT
#else #else
#error "invalid STM32_SYSCLK_SW value specified" #error "invalid STM32_SW value specified"
#endif #endif
/* Check on the system clock.*/ /* Check on the system clock.*/
@ -432,6 +606,74 @@
#error "STM32_PCLK2 exceeding maximum frequency (STM32_SYSCLK_MAX)" #error "STM32_PCLK2 exceeding maximum frequency (STM32_SYSCLK_MAX)"
#endif #endif
/**
* @brief MCO divider clock.
*/
#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
#define STM_MCODIVCLK 0
#elif STM32_MCOSEL == STM32_MCOSEL_HSI
#define STM_MCODIVCLK STM32_HSICLK
#elif STM32_MCOSEL == STM32_MCOSEL_MSI
#define STM_MCODIVCLK STM32_MSICLK
#elif STM32_MCOSEL == STM32_MCOSEL_HSE
#define STM_MCODIVCLK STM32_HSECLK
#elif STM32_MCOSEL == STM32_MCOSEL_PLL
#define STM_MCODIVCLK STM32_PLLCLKOUT
#elif STM32_MCOSEL == STM32_MCOSEL_LSI
#define STM_MCODIVCLK STM32_LSICLK
#elif STM32_MCOSEL == STM32_MCOSEL_LSE
#define STM_MCODIVCLK STM32_LSECLK
#else
#error "invalid STM32_MCOSEL value specified"
#endif
/**
* @brief MCO output pin clock.
*/
#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
#define STM_MCOCLK STM_MCODIVCLK
#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
#define STM_MCOCLK (STM_MCODIVCLK / 2)
#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
#define STM_MCOCLK (STM_MCODIVCLK / 4)
#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
#define STM_MCOCLK (STM_MCODIVCLK / 8)
#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
#define STM_MCOCLK (STM_MCODIVCLK / 16)
#else
#error "invalid STM32_MCOPRE value specified"
#endif
/**
* @brief HSE divider toward RTC clock.
*/
#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__)
#define STM32_HSEDIVCLK (HSECLK / 2)
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__)
#define STM32_HSEDIVCLK (HSECLK / 4)
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__)
#define STM32_HSEDIVCLK (HSECLK / 8)
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__)
#define STM32_HSEDIVCLK (HSECLK / 16)
#else
#error "invalid STM32_RTCPRE value specified"
#endif
/**
* @brief RTC/LCD clock.
*/
#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
#define STM_RTCCLK 0
#elif STM32_RTCSEL == STM32_RTCSEL_LSE
#define STM_RTCCLK STM32_LSECLK
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
#define STM_RTCCLK STM32_LSICLK
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
#define STM_RTCCLK STM32_HSEDIVCLK
#else
#error "invalid STM32_RTCSEL value specified"
#endif
/** /**
* @brief ADC frequency. * @brief ADC frequency.
*/ */
@ -467,7 +709,7 @@
#define STM32_FLASHBITS1 0x00000000 #define STM32_FLASHBITS1 0x00000000
#else #else
#define STM32_FLASHBITS1 0x00000004 #define STM32_FLASHBITS1 0x00000004
#define STM32_FLASHBITS2 0x00000003 #define STM32_FLASHBITS2 0x00000007
#endif #endif
/*===========================================================================*/ /*===========================================================================*/