Differential mode for STM32F3xx ADC driver.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8305 35acf78f-673a-0410-8e92-d51de3d6d3f4

os/hal/ports/STM32/STM32F3xx/adc_lld.c

@@ -73,6 +73,10 @@ ADCDriver ADCD3;
 /* Driver local variables and types.                                         */
 /*===========================================================================*/
 
+static const ADCConfig default_config = {
+  difsel: 0
+};
+
 /*===========================================================================*/
 /* Driver local functions.                                                   */
 /*===========================================================================*/
@@ -366,6 +370,11 @@ void adc_lld_init(void) {
  */
 void adc_lld_start(ADCDriver *adcp) {
 
+  /* Handling the default configuration.*/
+  if (adcp->config == NULL) {
+    adcp->config = &default_config;
+  }
+
   /* If in stopped state then enables the ADC and DMA clocks.*/
   if (adcp->state == ADC_STOP) {
 #if STM32_ADC_USE_ADC1
@@ -402,6 +411,15 @@ void adc_lld_start(ADCDriver *adcp) {
     /* Clock source setting.*/
     adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
 
+
+    /* Differential channels setting.*/
+#if STM32_ADC_DUAL_MODE
+    adcp->adcm->DIFSEL = adcp->config->difsel;
+    adcp->adcs->DIFSEL = adcp->config->difsel;
+#else
+    adcp->adcm->DIFSEL = adcp->config->difsel;
+#endif
+
     /* Master ADC calibration.*/
     adc_lld_vreg_on(adcp);
     adc_lld_calibrate(adcp);

os/hal/ports/STM32/STM32F3xx/adc_lld.h

@@ -452,10 +452,12 @@ typedef struct {
 
 /**
  * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
  */
 typedef struct {
-  uint32_t                  dummy;
+  /**
+   * @brief   ADC DIFSEL register initialization data.
+   */
+  uint32_t                  difsel;
 } ADCConfig;
 
 /**

readme.txt

@@ -73,6 +73,7 @@
 *****************************************************************************
 
 *** 3.1.0 ***
+- HAL: Added support for differential mode to the STM32F3xx ADC driver.
 - HAL: Experimental isochronous capability added to STM32 OTGv1 driver.
 - HAL: Modified the serial-USB driver to reject write/read attempts if the
        underlying USB is not in active state. In case of disconnection the