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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4832 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2012-11-19 12:47:33 +00:00
parent 8b97972690
commit d090b9342e
4 changed files with 22 additions and 22 deletions
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2
demos/PPC-SPC560P-GCC/mcuconf.h
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@ -140,7 +140,7 @@
SPC5_ME_LP_PC_STOP0) SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ #define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0) SPC5_ME_LP_PC_STOP0)
#define SPC5_PIT3_IRQ_PRIORITY 4 #define SPC5_PIT0_IRQ_PRIORITY 4
/* /*
* SERIAL driver system settings. * SERIAL driver system settings.

16
os/hal/platforms/SPC560BCxx/hal_lld.c
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@ -50,7 +50,7 @@
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(vector127) { CH_IRQ_HANDLER(vector59) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -59,7 +59,7 @@ CH_IRQ_HANDLER(vector127) {
chSysUnlockFromIsr(); chSysUnlockFromIsr();
/* Resets the PIT channel 3 IRQ flag.*/ /* Resets the PIT channel 3 IRQ flag.*/
PIT.CH[3].TFLG.R = 1; PIT.CH[0].TFLG.R = 1;
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
} }
@ -88,18 +88,18 @@ void hal_lld_init(void) {
INTC.CPR.R = 0; INTC.CPR.R = 0;
INTC.IACKR.R = (uint32_t)_vectors; INTC.IACKR.R = (uint32_t)_vectors;
/* PIT channel 3 initialization for Kernel ticks, the PIT is configured /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
modes.*/ modes.*/
INTC.PSR[127].R = SPC5_PIT0_IRQ_PRIORITY; INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY;
halSPCSetPeripheralClockMode(92, halSPCSetPeripheralClockMode(92,
SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
reg = halSPCGetSystemClock() / CH_FREQUENCY - 1; reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */ PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
PIT.CH[3].LDVAL.R = reg; PIT.CH[0].LDVAL.R = reg;
PIT.CH[3].CVAL.R = reg; PIT.CH[0].CVAL.R = reg;
PIT.CH[3].TFLG.R = 1; /* Interrupt flag cleared. */ PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
PIT.CH[3].TCTRL.R = 3; /* Timer active, interrupt enabled. */ PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
} }
/** /**

16
os/hal/platforms/SPC560Pxx/hal_lld.c
View File

@ -50,7 +50,7 @@
* *
* @isr * @isr
*/ */
CH_IRQ_HANDLER(vector127) { CH_IRQ_HANDLER(vector59) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -59,7 +59,7 @@ CH_IRQ_HANDLER(vector127) {
chSysUnlockFromIsr(); chSysUnlockFromIsr();
/* Resets the PIT channel 3 IRQ flag.*/ /* Resets the PIT channel 3 IRQ flag.*/
PIT.CH[3].TFLG.R = 1; PIT.CH[0].TFLG.R = 1;
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
} }
@ -88,18 +88,18 @@ void hal_lld_init(void) {
INTC.CPR.R = 0; INTC.CPR.R = 0;
INTC.IACKR.R = (uint32_t)_vectors; INTC.IACKR.R = (uint32_t)_vectors;
/* PIT channel 3 initialization for Kernel ticks, the PIT is configured /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
modes.*/ modes.*/
INTC.PSR[127].R = SPC5_PIT3_IRQ_PRIORITY; INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY;
halSPCSetPeripheralClockMode(92, halSPCSetPeripheralClockMode(92,
SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
reg = halSPCGetSystemClock() / CH_FREQUENCY - 1; reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */ PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
PIT.CH[3].LDVAL.R = reg; PIT.CH[0].LDVAL.R = reg;
PIT.CH[3].CVAL.R = reg; PIT.CH[0].CVAL.R = reg;
PIT.CH[3].TFLG.R = 1; /* Interrupt flag cleared. */ PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
PIT.CH[3].TCTRL.R = 3; /* Timer active, interrupt enabled. */ PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
} }
/** /**

6
os/hal/platforms/SPC560Pxx/hal_lld.h
View File

@ -582,12 +582,12 @@
#endif #endif
/** /**
* @brief PIT channel 3 IRQ priority. * @brief PIT channel 0 IRQ priority.
* @note This PIT channel is allocated permanently for system tick * @note This PIT channel is allocated permanently for system tick
* generation. * generation.
*/ */
#if !defined(SPC5_PIT3_IRQ_PRIORITY) || defined(__DOXYGEN__) #if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_PIT3_IRQ_PRIORITY 4 #define SPC5_PIT0_IRQ_PRIORITY 4
#endif #endif
/*===========================================================================*/ /*===========================================================================*/