diff --git a/boards/GENERIC_SPC56EL/board.c b/boards/GENERIC_SPC56EL/board.c
new file mode 100644
index 000000000..e5d7d2a83
--- /dev/null
+++ b/boards/GENERIC_SPC56EL/board.c
@@ -0,0 +1,71 @@
+/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *        http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software 
+ * distributed under the License is distributed on an "AS IS" BASIS, 
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {0, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+  {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
+  {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON1),  PAL_LOW,  PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON2),  PAL_LOW,  PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON3),  PAL_LOW,  PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON4),  PAL_LOW,  PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_LED1),     PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_D, PD_LED2),     PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_D, PD_LED3),     PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_D, PD_LED4),     PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+  {0, 0, 0}
+};
+
+/* Initialization array for the PSMI registers.*/
+static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0
+};
+
+/**
+ * @brief   PAL setup.
+ */
+const PALConfig pal_default_config = {
+  PAL_MODE_UNCONNECTED,             /* Default mode for all undefined pads. */
+  spc_siu_init,
+  spc_padsels_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  spc_clock_init();
+
+  /* SWT disabled.*/
+  SWT.SR.R = 0xC520;
+  SWT.SR.R = 0xD928;
+  SWT.CR.R = 0xFF00000A;
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
diff --git a/boards/GENERIC_SPC56EL/board.h b/boards/GENERIC_SPC56EL/board.h
new file mode 100644
index 000000000..ee4a23f95
--- /dev/null
+++ b/boards/GENERIC_SPC56EL/board.h
@@ -0,0 +1,66 @@
+/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *        http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software 
+ * distributed under the License is distributed on an "AS IS" BASIS, 
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC560Pxx proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_GENERIC_SPC56EL
+#define BOARD_NAME                  "Generic SPC56ELxx"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK               40000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define PB_LIN0_TDX     2
+#define PB_LIN0_RDX     3
+
+#define PD_BUTTON1      0
+#define PD_BUTTON2      1
+#define PD_BUTTON3      2
+#define PD_BUTTON4      3
+
+#define PD_LED1         4
+#define PD_LED2         5
+#define PD_LED3         6
+#define PD_LED4         7
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin)  (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/GENERIC_SPC56EL/board.mk b/boards/GENERIC_SPC56EL/board.mk
new file mode 100644
index 000000000..2d4706daa
--- /dev/null
+++ b/boards/GENERIC_SPC56EL/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/GENERIC_SPC56EL/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/GENERIC_SPC56EL
diff --git a/demos/PPC-SPC56EL-GCC/Makefile b/demos/PPC-SPC56EL-GCC/Makefile
index be14b2ad3..7561877cc 100644
--- a/demos/PPC-SPC56EL-GCC/Makefile
+++ b/demos/PPC-SPC56EL-GCC/Makefile
@@ -46,9 +46,9 @@ PROJECT = ch
 
 # Imported source files
 CHIBIOS = ../..
-#include $(CHIBIOS)/boards/GENERIC_SPC560EL/board.mk
-#include $(CHIBIOS)/os/hal/platforms/SPC560ELxx/platform.mk
-#include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/boards/GENERIC_SPC56EL/board.mk
+include $(CHIBIOS)/os/hal/platforms/SPC56ELxx/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/ports/GCC/PPC/SPC56ELxx/port.mk
 include $(CHIBIOS)/os/kernel/kernel.mk
 #include $(CHIBIOS)/test/test.mk
diff --git a/demos/PPC-SPC56EL-GCC/main.c b/demos/PPC-SPC56EL-GCC/main.c
index 538cfa482..890bdd9a3 100644
--- a/demos/PPC-SPC56EL-GCC/main.c
+++ b/demos/PPC-SPC56EL-GCC/main.c
@@ -19,7 +19,7 @@
 */
 
 #include "ch.h"
-//#include "hal.h"
+#include "hal.h"
 //#include "test.h"
 //#include "shell.h"
 //#include "chprintf.h"
@@ -175,7 +175,7 @@ int main(void) {
    * - Kernel initialization, the main() function becomes a thread and the
    *   RTOS is active.
    */
-//  halInit();
+  halInit();
   chSysInit();
 
   /*
diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c
index a3c66cc51..acfc175af 100644
--- a/os/hal/platforms/SPC56ELxx/hal_lld.c
+++ b/os/hal/platforms/SPC56ELxx/hal_lld.c
@@ -53,7 +53,7 @@ CH_IRQ_HANDLER(vector59) {
   chSysUnlockFromIsr();
 
   /* Resets the PIT channel 3 IRQ flag.*/
-  PIT.CH[0].TFLG.R = 1;
+  PIT.CHANNEL[0].TFLG.R = 1;
 
   CH_IRQ_EPILOGUE();
 }
@@ -90,10 +90,10 @@ void hal_lld_init(void) {
                                SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
   reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
   PIT.PITMCR.R      = 1;        /* PIT clock enabled, stop while debugging. */
-  PIT.CH[0].LDVAL.R = reg;
-  PIT.CH[0].CVAL.R  = reg;
-  PIT.CH[0].TFLG.R  = 1;        /* Interrupt flag cleared.                  */
-  PIT.CH[0].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */
+  PIT.CHANNEL[0].LDVAL.R = reg;
+  PIT.CHANNEL[0].CVAL.R  = reg;
+  PIT.CHANNEL[0].TFLG.R  = 1;   /* Interrupt flag cleared.                  */
+  PIT.CHANNEL[0].TCTRL.R = 3;   /* Timer active, interrupt enabled.         */
 }
 
 /**
@@ -107,7 +107,7 @@ void hal_lld_init(void) {
 void spc_clock_init(void) {
 
   /* Waiting for IRC stabilization before attempting anything else.*/
-  while (!ME.GS.B.S_RC)
+  while (!ME.GS.B.S_IRCOSC)
     ;
 
 #if !SPC5_NO_INIT
@@ -130,7 +130,7 @@ void spc_clock_init(void) {
 
   /* Run modes initialization.*/
   ME.MER.R          = SPC5_ME_ME_BITS;          /* Enabled run modes.       */
-  ME.TEST.R         = SPC5_ME_TEST_MC_BITS;     /* TEST run mode.           */
+//  ME.TEST.R         = SPC5_ME_TEST_MC_BITS;     /* TEST run mode.           */
   ME.SAFE.R         = SPC5_ME_SAFE_MC_BITS;     /* SAFE run mode.           */
   ME.DRUN.R         = SPC5_ME_DRUN_MC_BITS;     /* DRUN run mode.           */
   ME.RUN[0].R       = SPC5_ME_RUN0_MC_BITS;     /* RUN0 run mode.           */
@@ -164,10 +164,10 @@ void spc_clock_init(void) {
     chSysHalt();
 
   /* CFLASH settings calculated for a maximum clock of 64MHz.*/
-  CFLASH.PFCR0.B.BK0_APC  = 2;
+/*  CFLASH.PFCR0.B.BK0_APC  = 2;
   CFLASH.PFCR0.B.BK0_RWSC = 2;
   CFLASH.PFCR1.B.BK1_APC  = 2;
-  CFLASH.PFCR1.B.BK1_RWSC = 2;
+  CFLASH.PFCR1.B.BK1_RWSC = 2;*/
 
 #endif /* !SPC5_NO_INIT */
 }
@@ -196,7 +196,7 @@ bool_t halSPCSetRunMode(spc5_runmode_t mode) {
     ;
 
   /* Verifies that the mode has been effectively switched.*/
-  if (ME.GS.B.S_CURRENTMODE != mode)
+  if (ME.GS.B.S_CURRENT_MODE != mode)
     return CH_FAILED;
 
   return CH_SUCCESS;
diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.h b/os/hal/platforms/SPC56ELxx/hal_lld.h
index 4ddd73597..fbfef7294 100644
--- a/os/hal/platforms/SPC56ELxx/hal_lld.h
+++ b/os/hal/platforms/SPC56ELxx/hal_lld.h
@@ -69,7 +69,7 @@
 /**
  * @brief   Maximum FMPLLs input clock frequency.
  */
-#define SPC5_FMPLLIN_MAX            16000000
+#define SPC5_FMPLLIN_MAX            40000000
 
 /**
  * @brief   Maximum FMPLLs VCO clock frequency.
@@ -84,7 +84,7 @@
 /**
  * @brief   Maximum FMPLL0 output clock frequency.
  */
-#define SPC5_FMPLL0_CLK_MAX         64000000
+#define SPC5_FMPLL0_CLK_MAX         120000000
 
 /**
  * @brief   Maximum FMPLL1 output clock frequency.
@@ -104,6 +104,26 @@
 #define SPC5_IRC_CLK                16000000    /**< Internal RC oscillator.*/
 /** @} */
 
+/**
+ * @name    MC_CGM_AC3_SC register bits definitions
+ * @{
+ */
+#define SPC5_GCM_AC3_SC_SELCTL_MASK (15U << 24)
+#define SPC5_GCM_AC3_SC_SELCTL(n)   ((n) << 24)
+#define SPC5_GCM_AC3_SC_SELCTL_IRC  SPC5_GCM_AC3_SC_SELCTL(0)
+#define SPC5_GCM_AC3_SC_SELCTL_XOSC SPC5_GCM_AC3_SC_SELCTL(1)
+/** @} */
+
+/**
+ * @name    MC_CGM_AC4_SC register bits definitions
+ * @{
+ */
+#define SPC5_GCM_AC4_SC_SELCTL_MASK (15U << 24)
+#define SPC5_GCM_AC4_SC_SELCTL(n)   ((n) << 24)
+#define SPC5_GCM_AC4_SC_SELCTL_IRC  SPC5_GCM_AC4_SC_SELCTL(0)
+#define SPC5_GCM_AC4_SC_SELCTL_XOSC SPC5_GCM_AC4_SC_SELCTL(1)
+/** @} */
+
 /**
  * @name    FMPLL_CR register bits definitions
  * @{
@@ -230,6 +250,13 @@
 #define SPC5_ALLOW_OVERCLOCK        FALSE
 #endif
 
+/**
+ * @brief   FMPLL0 Clock source.
+ */
+#if !defined(SPC5_FMPLL0_CLOCK_SOURCE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_CLOCK_SOURCE    SPC5_GCM_AC3_SC_SELCTL_XOSC
+#endif
+
 /**
  * @brief   FMPLL0 IDF divider value.
  * @note    The default value is calculated for XOSC=40MHz and PHI=64MHz.
@@ -254,6 +281,13 @@
 #define SPC5_FMPLL0_ODF             SPC5_FMPLL_ODF_DIV4
 #endif
 
+/**
+ * @brief   FMPLL1 Clock source.
+ */
+#if !defined(SPC5_FMPLL1_CLOCK_SOURCE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_CLOCK_SOURCE    SPC5_GCM_AC4_SC_SELCTL_XOSC
+#endif
+
 /**
  * @brief   FMPLL1 IDF divider value.
  * @note    The default value is calculated for XOSC=40MHz and PHI=64MHz.
@@ -601,6 +635,15 @@
 #error "invalid SPC5_XOSC_CLK value specified"
 #endif
 
+/* Check on SPC5_FMPLL0_CLOCK_SOURCE.*/
+#if SPC5_FMPLL0_CLOCK_SOURCE == SPC5_GCM_AC3_SC_SELCTL_IRC
+#define SPC5_FMPLL0_INPUT_CLK   SPC5_IRC_CLK
+#elif SPC5_FMPLL0_CLOCK_SOURCE == SPC5_GCM_AC3_SC_SELCTL_XOSC
+#define SPC5_FMPLL0_INPUT_CLK   SPC5_XOSC_CLK
+#else
+#error "invalid SPC5_FMPLL0_CLOCK_SOURCE value specified"
+#endif
+
 /* Check on SPC5_FMPLL0_IDF_VALUE.*/
 #if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
 #error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
@@ -628,7 +671,7 @@
  * @brief   SPC5_FMPLL0_VCO_CLK clock point.
  */
 #define SPC5_FMPLL0_VCO_CLK                                                 \
-  ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
+  ((SPC5_FMPLL0_INPUT_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
 
 /* Check on FMPLL0 VCO output.*/
 #if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) ||                            \
@@ -647,6 +690,15 @@
 #error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
 #endif
 
+/* Check on SPC5_FMPLL1_CLOCK_SOURCE.*/
+#if SPC5_FMPLL1_CLOCK_SOURCE == SPC5_GCM_AC4_SC_SELCTL_IRC
+#define SPC5_FMPLL1_INPUT_CLK   SPC5_IRC_CLK
+#elif SPC5_FMPLL1_CLOCK_SOURCE == SPC5_GCM_AC4_SC_SELCTL_XOSC
+#define SPC5_FMPLL1_INPUT_CLK   SPC5_XOSC_CLK
+#else
+#error "invalid SPC5_FMPLL1_CLOCK_SOURCE value specified"
+#endif
+
 /* Check on SPC5_FMPLL1_IDF_VALUE.*/
 #if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
 #error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
@@ -674,7 +726,7 @@
  * @brief   SPC5_FMPLL1_VCO_CLK clock point.
  */
 #define SPC5_FMPLL1_VCO_CLK                                                 \
-  ((SPC5_XOSC_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)
+  ((SPC5_FMPLL1_INPUT_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)
 
 /* Check on FMPLL1 VCO output.*/
 #if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) ||                            \
diff --git a/os/hal/platforms/SPC56ELxx/platform.mk b/os/hal/platforms/SPC56ELxx/platform.mk
index 53b94c39d..61f1cf3de 100644
--- a/os/hal/platforms/SPC56ELxx/platform.mk
+++ b/os/hal/platforms/SPC56ELxx/platform.mk
@@ -1,9 +1,9 @@
-# List of all the SPC560Pxx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx/hal_lld.c \
+# List of all the SPC56ELxx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx/hal_lld.c \
               ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \
               ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
 
 # Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx \
+PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx \
               ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \
               ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1
diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h
index 22d8aed75..5e3595be0 100644
--- a/os/hal/platforms/SPC56ELxx/spc56el_registry.h
+++ b/os/hal/platforms/SPC56ELxx/spc56el_registry.h
@@ -20,8 +20,8 @@
  * @{
  */
 
-#ifndef _SPC560P_REGISTRY_H_
-#define _SPC560P_REGISTRY_H_
+#ifndef _SPC56EL_REGISTRY_H_
+#define _SPC56EL_REGISTRY_H_
 
 /*===========================================================================*/
 /* Platform capabilities.                                                    */
@@ -61,6 +61,6 @@
 #define SPC5_SIUL_NUM_PADSELS               36
 /** @} */
 
-#endif /* _SPC560P_REGISTRY_H_ */
+#endif /* _SPC56EL_REGISTRY_H_ */
 
 /** @} */