From cfdf3905dbd6af629d40096940fb2845c6ca6668 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 17 Apr 2010 12:37:00 +0000
Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1867
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/ports/GCC/ARMCMx/chcore_v7m_test.c | 28 ++++++++++++++++++---------
 readme.txt                            | 13 +++++++++++--
 2 files changed, 30 insertions(+), 11 deletions(-)

diff --git a/os/ports/GCC/ARMCMx/chcore_v7m_test.c b/os/ports/GCC/ARMCMx/chcore_v7m_test.c
index 4df46f065..09e683f00 100644
--- a/os/ports/GCC/ARMCMx/chcore_v7m_test.c
+++ b/os/ports/GCC/ARMCMx/chcore_v7m_test.c
@@ -27,6 +27,22 @@
 
 #include "ch.h"
 
+/**
+ * @brief   Internal context stacking.
+ */
+#define PUSH_CONTEXT(sp) {                                                  \
+  asm volatile ("push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}");          \
+}
+
+
+/**
+ * @brief   Internal context unstacking.
+ */
+#define POP_CONTEXT(sp) {                                                   \
+  asm volatile ("pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}"            \
+                :  : "r" (sp));                                             \
+}
+
 #if !CH_OPTIMIZE_SPEED
 void _port_lock(void) {
   register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;
@@ -87,8 +103,11 @@ void _port_irq_epilogue(void) {
     asm volatile ("msr     PSP, %0" :  : "r" (ctxp));
     ctxp->pc = _port_switch_from_isr;
     ctxp->xpsr = (regarm_t)0x01000000;
+    /* Note, returning without unlocking is intentional, this is done in
+       order to keep the rest of the context switching atomic.*/
     return;
   }
+  /* ISR exit without context switching.*/
   port_unlock_from_isr();
 }
 
@@ -105,15 +124,6 @@ void _port_switch_from_isr(void) {
   asm volatile ("svc     #0");
 }
 
-#define PUSH_CONTEXT(sp) {                                                  \
-  asm volatile ("push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}");          \
-}
-
-#define POP_CONTEXT(sp) {                                                   \
-  asm volatile ("pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}"            \
-                :  : "r" (sp));                                             \
-}
-
 /**
  * @brief   Performs a context switch between two threads.
  * @details This is the most critical code in any port, this function
diff --git a/readme.txt b/readme.txt
index c141a76f6..c55ee2e51 100644
--- a/readme.txt
+++ b/readme.txt
@@ -57,11 +57,20 @@
 *****************************************************************************
 
 *** 1.5.5 ***
-- FIX: Removed some "dead" code in the ARMv7-M files.
-- NEW: LPC13xx support, drivers (Serial, PAL, HAL) and demo.
+- FIX: Removed some "dead" code in the old ARMv7-M files (there are new
+  ones, see below).
+- NEW: LPC13xx support, drivers (Serial, PAL, HAL), demo and reports.
+- NEW: Added statistic info to the lwIP demo.
 - CHANGE: Renamed LPC111x port and platform in LPC11xx, minor fixes to the
   platform header files.
 - CHANGE: Small documentation fixes and improvements.
+- OPT: New Cortex-M3 port code, *huge* performance improvements in all the
+  context switching related benchmarks (5-15% depending on the benchmark).
+  The new code does no more require the use of the PendSV vector that is
+  thus available to the user, it also saves four RAM bytes for each thread
+  in the system. The old code is still available as a fall back option while
+  the new one is being hardened by peers review and time, the two ports are
+  perfectly interchangeable.
 
 *** 1.5.4 ***
 - FIX: Fixed broken CH_CURRP_REGISTER_CACHE option in the ARM7 port (bug