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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5157 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-02-12 12:56:05 +00:00
parent 07decf05f9
commit cf26fca282
3 changed files with 177 additions and 14 deletions
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119
demos/PPC-SPC56EL-GCC/mcuconf.h
View File

@ -28,6 +28,125 @@
/* /*
* HAL driver system settings. * HAL driver system settings.
*/ */
#define SPC5_NO_INIT FALSE
#define SPC5_ALLOW_OVERCLOCK FALSE
#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC
#define SPC5_FMPLL0_IDF_VALUE 5
#define SPC5_FMPLL0_NDIV_VALUE 60
#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC
#define SPC5_FMPLL1_IDF_VALUE 5
#define SPC5_FMPLL1_NDIV_VALUE 60
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
#define SPC5_SYSCLK_DIVIDER_VALUE 1
#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
#define SPC5_MCONTROL_DIVIDER_VALUE 2
#define SPC5_SWG_DIVIDER_VALUE 2
#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1
#define SPC5_FLEXRAY_DIVIDER_VALUE 2
#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1
#define SPC5_FLEXCAN_DIVIDER_VALUE 2
#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
SPC5_ME_ME_RUN2 | \
SPC5_ME_ME_RUN3 | \
SPC5_ME_ME_HALT0 | \
SPC5_ME_ME_STOP0)
#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_FLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_FLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_FLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_FLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_FLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_FLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_FLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_RUN_PC0_BITS 0
#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_SAFE | \
SPC5_ME_RUN_PC_DRUN | \
SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_LP_PC0_BITS 0
#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
/* /*
* SERIAL driver system settings. * SERIAL driver system settings.

37
os/hal/platforms/SPC56ELxx/hal_lld.c
View File

@ -54,8 +54,9 @@ void hal_lld_init(void) {
/* The system is switched to the RUN0 mode, the default for normal /* The system is switched to the RUN0 mode, the default for normal
operations.*/ operations.*/
if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) {
chSysHalt(); /* TODO: Add handling.*/ SPC5_CLOCK_FAILURE_HOOK();
}
/* Down-counter timer initialized for system tick use, TB enabled for debug /* Down-counter timer initialized for system tick use, TB enabled for debug
and measurements.*/ and measurements.*/
@ -75,6 +76,23 @@ void hal_lld_init(void) {
INTC.IACKR.R = (uint32_t)_vectors; INTC.IACKR.R = (uint32_t)_vectors;
} }
/**
* @brief Returns the current value of the system free running counter.
* @note This service is implemented by returning the content of the
* DWT_CYCCNT register.
*
* @return The value of the system free running counter of
* type halrtcnt_t.
*
* @notapi
*/
halrtcnt_t hal_lld_get_counter_value(void) {
halrtcnt_t cnt;
asm volatile ("mfspr %0, 284" : "=r" (cnt));
return cnt;
}
/** /**
* @brief SPC56ELxx early initialization. * @brief SPC56ELxx early initialization.
* @note All the involved constants come from the file @p board.h and * @note All the involved constants come from the file @p board.h and
@ -120,8 +138,9 @@ void spc_early_init(void) {
AIPS.OPACR88_95.R = 0; AIPS.OPACR88_95.R = 0;
/* Check on a safe condition.*/ /* Check on a safe condition.*/
if (ME.GS.B.S_CURRENT_MODE != SPC5_RUNMODE_DRUN) if (ME.GS.B.S_CURRENT_MODE != SPC5_RUNMODE_DRUN) {
chSysHalt(); /* TODO: Add handling.*/ SPC5_CLOCK_FAILURE_HOOK();
}
#if defined(SPC5_OSC_BYPASS) #if defined(SPC5_OSC_BYPASS)
/* If the board is equipped with an oscillator instead of a crystal then the /* If the board is equipped with an oscillator instead of a crystal then the
@ -143,8 +162,9 @@ void spc_early_init(void) {
/* Switches to XOSC in order to check its functionality.*/ /* Switches to XOSC in order to check its functionality.*/
ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON | SPC5_ME_MC_XOSC0ON | \ ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON | SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_FLAON_NORMAL | SPC5_ME_MC_MVRON; SPC5_ME_MC_FLAON_NORMAL | SPC5_ME_MC_MVRON;
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
chSysHalt(); /* TODO: Add handling.*/ SPC5_CLOCK_FAILURE_HOOK();
}
/* Initialization of the FMPLLs settings.*/ /* Initialization of the FMPLLs settings.*/
CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF | CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF |
@ -192,8 +212,9 @@ void spc_early_init(void) {
/* Switches again to DRUN mode (current mode) in order to update the /* Switches again to DRUN mode (current mode) in order to update the
settings.*/ settings.*/
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
chSysHalt(); /* TODO: Add handling.*/ SPC5_CLOCK_FAILURE_HOOK();
}
#endif /* !SPC5_NO_INIT */ #endif /* !SPC5_NO_INIT */
} }

35
os/hal/platforms/SPC56ELxx/hal_lld.h
View File

@ -38,7 +38,7 @@
/** /**
* @brief Defines the support for realtime counters in the HAL. * @brief Defines the support for realtime counters in the HAL.
*/ */
#define HAL_IMPLEMENTS_COUNTERS FALSE #define HAL_IMPLEMENTS_COUNTERS TRUE
/** /**
* @name Platform identification * @name Platform identification
@ -642,12 +642,12 @@
#endif #endif
/** /**
* @brief PIT channel 0 IRQ priority. * @brief Clock initialization failure hook.
* @note This PIT channel is allocated permanently for system tick * @note The default is to stop the system and let the RTC restart it.
* generation. * @note The hook code must not return.
*/ */
#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__) #if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
#define SPC5_PIT0_IRQ_PRIORITY 4 #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
#endif #endif
/*===========================================================================*/ /*===========================================================================*/
@ -913,6 +913,19 @@ _
/* Driver data structures and types. */ /* Driver data structures and types. */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Type representing a system clock frequency.
*/
typedef uint32_t halclock_t;
/**
* @brief Type of the realtime free counter value.
*/
typedef uint32_t halrtcnt_t;
/**
* @brief Run modes.
*/
typedef enum { typedef enum {
SPC5_RUNMODE_SAFE = 2, SPC5_RUNMODE_SAFE = 2,
SPC5_RUNMODE_DRUN = 3, SPC5_RUNMODE_DRUN = 3,
@ -928,6 +941,15 @@ typedef enum {
/* Driver macros. */ /* Driver macros. */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Realtime counter frequency.
*
* @return The realtime counter frequency of type halclock_t.
*
* @notapi
*/
#define hal_lld_get_counter_frequency() (halclock_t)halSPCGetSystemClock()
/*===========================================================================*/ /*===========================================================================*/
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
@ -936,6 +958,7 @@ typedef enum {
extern "C" { extern "C" {
#endif #endif
void hal_lld_init(void); void hal_lld_init(void);
halrtcnt_t hal_lld_get_counter_value(void);
void spc_early_init(void); void spc_early_init(void);
bool_t halSPCSetRunMode(spc5_runmode_t mode); bool_t halSPCSetRunMode(spc5_runmode_t mode);
void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl); void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);