Added USART6 support to STM32 UART/mcuconf.h(v1) driver.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4447 35acf78f-673a-0410-8e92-d51de3d6d3f4master
parent
5770d1835f
commit
cef1ea693e
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@ -196,18 +196,23 @@
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 TRUE
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#define STM32_UART_USE_USART2 TRUE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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/*
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/*
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@ -196,18 +196,23 @@
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 TRUE
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#define STM32_UART_USE_USART2 TRUE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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/*
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/*
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@ -196,18 +196,23 @@
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 TRUE
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#define STM32_UART_USE_USART2 TRUE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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/*
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/*
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@ -59,6 +59,14 @@
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STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \
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STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \
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STM32_USART3_TX_DMA_CHN)
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STM32_USART3_TX_DMA_CHN)
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#define USART6_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART6_RX_DMA_STREAM, \
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STM32_USART6_RX_DMA_CHN)
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#define USART6_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM, \
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STM32_USART6_TX_DMA_CHN)
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -78,6 +86,12 @@ UARTDriver UARTD2;
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UARTDriver UARTD3;
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UARTDriver UARTD3;
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#endif
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#endif
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/** @brief USART6 UART driver identifier.*/
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#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
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UARTDriver UARTD6;
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#endif
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -344,6 +358,25 @@ CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
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}
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}
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#endif /* STM32_UART_USE_USART3 */
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#endif /* STM32_UART_USE_USART3 */
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#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
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#if !defined(STM32_USART6_HANDLER)
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#error "STM32_USART6_HANDLER not defined"
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#endif
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/**
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* @brief USART6 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_USART6_HANDLER) {
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CH_IRQ_PROLOGUE();
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serve_usart_irq(&UARTD6);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_UART_USE_USART6 */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/* Driver exported functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
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UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
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UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
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UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
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#endif
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#endif
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#if STM32_UART_USE_USART6
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uartObjectInit(&UARTD6);
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UARTD6.usart = USART6;
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UARTD6.dmarx = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM);
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UARTD6.dmatx = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM);
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#endif
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}
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}
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/**
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/**
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}
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}
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#endif
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#endif
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#if STM32_UART_USE_USART6
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if (&UARTD6 == uartp) {
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bool_t b;
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b = dmaStreamAllocate(uartp->dmarx,
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STM32_UART_USART6_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated");
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b = dmaStreamAllocate(uartp->dmatx,
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STM32_UART_USART6_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
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rccEnableUSART6(FALSE);
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nvicEnableVector(STM32_USART6_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_USART6_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
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}
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#endif
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/* Static DMA setup, the transfer size depends on the USART settings,
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/* Static DMA setup, the transfer size depends on the USART settings,
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it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
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it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
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if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
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if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
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return;
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return;
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}
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}
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#endif
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#endif
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#if STM32_UART_USE_USART6
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if (&UARTD6 == uartp) {
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nvicDisableVector(STM32_USART6_NUMBER);
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rccDisableUSART6(FALSE);
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return;
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}
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#endif
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}
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}
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}
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}
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#endif
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#endif
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/**
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* @brief UART driver on USART6 enable switch.
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* @details If set to @p TRUE the support for USART6 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_UART_USE_USART6) || defined(__DOXYGEN__)
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#define STM32_UART_USE_USART6 FALSE
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#endif
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/**
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/**
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* @brief USART1 interrupt priority level setting.
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* @brief USART1 interrupt priority level setting.
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*/
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*/
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#endif
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#endif
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/**
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* @brief USART6 interrupt priority level setting.
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*/
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#if !defined(STM32_UART_USART6_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#endif
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/**
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/**
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* @brief USART1 DMA priority (0..3|lowest..highest).
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* @brief USART1 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA channels but
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* @note The priority level is used for both the TX and RX DMA channels but
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#endif
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#endif
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/**
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* @brief USART6 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA channels but
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* because of the channels ordering the RX channel has always priority
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* over the TX channel.
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*/
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#if !defined(STM32_UART_USART6_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#endif
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/**
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/**
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* @brief USART1 DMA error hook.
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* @brief USART1 DMA error hook.
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* @note The default action for DMA errors is a system halt because DMA
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* @note The default action for DMA errors is a system halt because DMA
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#endif
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#endif
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/**
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* @brief DMA stream used for USART6 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_USART6_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#endif
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/**
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* @brief DMA stream used for USART6 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_USART6_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#endif
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#else /* !STM32_ADVANCED_DMA */
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#else /* !STM32_ADVANCED_DMA */
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/* Fixed streams for platforms using the old DMA peripheral, the values are
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/* Fixed streams for platforms using the old DMA peripheral, the values are
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#error "USART3 not present in the selected device"
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#error "USART3 not present in the selected device"
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#endif
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#endif
|
||||||
|
|
||||||
|
#if STM32_UART_USE_USART6 && !STM32_HAS_USART6
|
||||||
|
#error "USART6 not present in the selected device"
|
||||||
|
#endif
|
||||||
|
|
||||||
#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \
|
#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \
|
||||||
!STM32_UART_USE_USART3
|
!STM32_UART_USE_USART3 && !STM32_UART_USE_USART6
|
||||||
#error "UART driver activated but no USART/UART peripheral assigned"
|
#error "UART driver activated but no USART/UART peripheral assigned"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -230,6 +276,11 @@
|
||||||
#error "Invalid IRQ priority assigned to USART3"
|
#error "Invalid IRQ priority assigned to USART3"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if STM32_UART_USE_USART6 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to USART6"
|
||||||
|
#endif
|
||||||
|
|
||||||
#if STM32_UART_USE_USART1 && \
|
#if STM32_UART_USE_USART1 && \
|
||||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
|
||||||
#error "Invalid DMA priority assigned to USART1"
|
#error "Invalid DMA priority assigned to USART1"
|
||||||
|
@ -245,6 +296,11 @@
|
||||||
#error "Invalid DMA priority assigned to USART3"
|
#error "Invalid DMA priority assigned to USART3"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if STM32_UART_USE_USART6 && \
|
||||||
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART6_DMA_PRIORITY)
|
||||||
|
#error "Invalid DMA priority assigned to USART6"
|
||||||
|
#endif
|
||||||
|
|
||||||
#if STM32_UART_USE_USART1 && \
|
#if STM32_UART_USE_USART1 && \
|
||||||
!STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \
|
!STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \
|
||||||
STM32_USART1_RX_DMA_MSK)
|
STM32_USART1_RX_DMA_MSK)
|
||||||
|
@ -281,6 +337,18 @@
|
||||||
#error "invalid DMA stream associated to USART3 TX"
|
#error "invalid DMA stream associated to USART3 TX"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if STM32_UART_USE_USART6 && \
|
||||||
|
!STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM, \
|
||||||
|
STM32_USART6_RX_DMA_MSK)
|
||||||
|
#error "invalid DMA stream associated to USART6 RX"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_UART_USE_USART6 && \
|
||||||
|
!STM32_DMA_IS_VALID_ID(STM32_UART_USART6_TX_DMA_STREAM, \
|
||||||
|
STM32_USART6_TX_DMA_MSK)
|
||||||
|
#error "invalid DMA stream associated to USART6 TX"
|
||||||
|
#endif
|
||||||
|
|
||||||
#if !defined(STM32_DMA_REQUIRED)
|
#if !defined(STM32_DMA_REQUIRED)
|
||||||
#define STM32_DMA_REQUIRED
|
#define STM32_DMA_REQUIRED
|
||||||
#endif
|
#endif
|
||||||
|
@ -432,6 +500,10 @@ extern UARTDriver UARTD2;
|
||||||
extern UARTDriver UARTD3;
|
extern UARTDriver UARTD3;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if STM32_UART_USE_USART6 && !defined(__DOXYGEN__)
|
||||||
|
extern UARTDriver UARTD6;
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -162,6 +162,8 @@
|
||||||
3484947)(backported to 2.4.1).
|
3484947)(backported to 2.4.1).
|
||||||
- FIX: Fixed various minor documentation errors (bug 3484942)(backported
|
- FIX: Fixed various minor documentation errors (bug 3484942)(backported
|
||||||
to 2.4.1).
|
to 2.4.1).
|
||||||
|
- NEW: Added USART6 support to the STM32 UARTv1 driver, contributed by Erik
|
||||||
|
van der Zalm.
|
||||||
- NEW: Added demo for Arduino Mega, contributed by Fabio Utzig.
|
- NEW: Added demo for Arduino Mega, contributed by Fabio Utzig.
|
||||||
- NEW: Added support for ATmega1280, contributed by Fabio Utzig.
|
- NEW: Added support for ATmega1280, contributed by Fabio Utzig.
|
||||||
- NEW: Added I2C driver for AVR, contributed by Fabio Utzig.
|
- NEW: Added I2C driver for AVR, contributed by Fabio Utzig.
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -204,18 +204,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -204,18 +204,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -204,18 +204,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 TRUE
|
#define STM32_UART_USE_USART1 TRUE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 TRUE
|
#define STM32_UART_USE_USART3 TRUE
|
||||||
|
#define STM32_UART_USE_USART6 TRUE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -196,18 +196,23 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
Loading…
Reference in New Issue