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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4343 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2012-06-24 07:41:07 +00:00
parent 30400ff287
commit ca6ab337fe
5 changed files with 39 additions and 3 deletions
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9
os/hal/platforms/STM32/OTGv1/usb_lld.c
View File

@ -532,12 +532,15 @@ static void otg_epout_handler(USBDriver *usbp, usbep_t ep) {
/*===========================================================================*/
#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
#if !defined(STM32_OTG1_HANDLER)
#error "STM32_OTG1_HANDLER not defined"
#endif
/**
* @brief OTG1 interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(OTG_FS_IRQHandler) {
CH_IRQ_HANDLER(STM32_OTG1_HANDLER) {
USBDriver *usbp = &USBD1;
uint32_t sts;
@ -631,7 +634,7 @@ void usb_lld_start(USBDriver *usbp) {
rccResetOTG_FS();
/* Enables IRQ vector.*/
nvicEnableVector(OTG_FS_IRQn,
nvicEnableVector(STM32_OTG1_NUMBER,
CORTEX_PRIORITY_MASK(STM32_USB_OTG1_IRQ_PRIORITY));
}
#endif
@ -686,7 +689,7 @@ void usb_lld_stop(USBDriver *usbp) {
if (usbp->state == USB_STOP) {
#if STM32_USB_USE_USB1
if (&USBD1 == usbp) {
nvicDisableVector(OTG_FS_IRQn);
nvicDisableVector(STM32_OTG1_NUMBER);
rccDisableOTG1(FALSE);
}
#endif

5
os/hal/platforms/STM32/OTGv1/usb_lld.h
View File

@ -87,6 +87,11 @@
#error "USB driver activated but no USB peripheral assigned"
#endif
#if STM32_USB_USE_OTG1 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to OTG1"
#endif
#if (STM32_USB_OTG1_RX_FIFO_SIZE & 3) != 0
#error "RX FIFO size must be a multiple of 4"
#endif

8
os/hal/platforms/STM32F1xx/stm32_isr.h
View File

@ -58,10 +58,18 @@
#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn
#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn
/*
* OTG units.
*/
#define STM32_OTG1_HANDLER OTG_FS_IRQHandler
#define STM32_OTG1_NUMBER OTG_FS_IRQn
/*
* SDIO unit.
*/
#define STM32_SDIO_HANDLER SDIO_IRQHandler
#define STM32_SDIO_NUMBER SDIO_IRQn
/*

10
os/hal/platforms/STM32F2xx/stm32_isr.h
View File

@ -58,10 +58,20 @@
#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn
#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn
/*
* OTG units.
*/
#define STM32_OTG1_HANDLER OTG_FS_IRQHandler
#define STM32_OTG2_HANDLER OTG_HS_IRQHandler
#define STM32_OTG1_NUMBER OTG_FS_IRQn
#define STM32_OTG2_NUMBER OTG_HS_IRQn
/*
* SDIO unit.
*/
#define STM32_SDIO_HANDLER SDIO_IRQHandler
#define STM32_SDIO_NUMBER SDIO_IRQn
/*

10
os/hal/platforms/STM32F4xx/stm32_isr.h
View File

@ -58,10 +58,20 @@
#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn
#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn
/*
* OTG units.
*/
#define STM32_OTG1_HANDLER OTG_FS_IRQHandler
#define STM32_OTG2_HANDLER OTG_HS_IRQHandler
#define STM32_OTG1_NUMBER OTG_FS_IRQn
#define STM32_OTG2_NUMBER OTG_HS_IRQn
/*
* SDIO unit.
*/
#define STM32_SDIO_HANDLER SDIO_IRQHandler
#define STM32_SDIO_NUMBER SDIO_IRQn
/*