STM32F446 support.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8665 35acf78f-673a-0410-8e92-d51de3d6d3f4master
Giovanni Di Sirio
parent
d832e5d173
commit
c89b91cbed
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@ -33,6 +33,7 @@
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* High-performance STM32 F-4 devices.
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* - STM32F401xC, STM32F401xE for High-performance STM32 F-4 devices.
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* - STM32F411xE for High-performance STM32 F-4 devices.
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* - STM32F446xx for High-performance STM32 F-4 devices.
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* .
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*
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* @addtogroup HAL
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@ -60,6 +61,9 @@
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#if defined(STM32F439xx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU"
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#elif defined(STM32F446xx)
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#define PLATFORM_NAME "STM32F446 High Performance with DSP and FPU"
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#elif defined(STM32F429xx)
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#define PLATFORM_NAME "STM32F429 High Performance with DSP and FPU"
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@ -113,7 +117,7 @@
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || \
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defined(STM32F429xx) || defined(STM32F439xx) || \
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defined(__DOXYGEN__)
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defined(STM32F446xx) || defined(__DOXYGEN__)
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/**
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* @brief Absolute maximum system clock.
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*/
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@ -747,7 +751,8 @@
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* @note The values are valid for 2.7V to 3.6V supply range.
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*/
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#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
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defined(STM32F40_41xxx) || defined(__DOXYGEN__)
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defined(STM32F40_41xxx) || defined(STM32F446xx) || \
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defined(__DOXYGEN__)
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#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
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#define STM32_0WS_THRESHOLD 30000000
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#define STM32_1WS_THRESHOLD 60000000
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@ -1157,7 +1162,7 @@
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/* Calculating VOS settings, it is different for each sub-platform.*/
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#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
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defined(__DOXYGEN__)
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defined(STM32F446xx) || defined(__DOXYGEN__)
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#if STM32_SYSCLK <= 120000000
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#define STM32_VOS STM32_VOS_SCALE3
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#define STM32_OVERDRIVE_REQUIRED FALSE
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@ -25,8 +25,10 @@
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#ifndef _STM32_REGISTRY_H_
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#define _STM32_REGISTRY_H_
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#if defined(STM32F446xx)
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#define STM32F4XX
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#if defined(STM32F439xx) || defined(STM32F429xx)
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#elif defined(STM32F439xx) || defined(STM32F429xx)
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#define STM32F429_439xx
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#define STM32F4XX
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@ -60,9 +62,341 @@
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/*===========================================================================*/
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/**
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* @name STM32F4xx capabilities
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* @name STM32F4xx/STM32F2xx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* STM32F446xx. */
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/*===========================================================================*/
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#if defined(STM32F446xx)
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/* ADC attributes.*/
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#define STM32_ADC_HANDLER Vector88
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#define STM32_ADC_NUMBER 18
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 TRUE
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#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_ADC2_DMA_CHN 0x00001100
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#define STM32_HAS_ADC3 TRUE
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#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 1))
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#define STM32_ADC3_DMA_CHN 0x00000022
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#define STM32_HAS_ADC4 FALSE
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#define STM32_HAS_SDADC1 FALSE
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#define STM32_HAS_SDADC2 FALSE
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#define STM32_HAS_SDADC3 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN2 TRUE
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#define STM32_CAN_MAX_FILTERS 28
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_DAC1_CH1_DMA_CHN 0x00700000
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_DAC1_CH2_DMA_CHN 0x07000000
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_CACHE_HANDLING FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_DMA1_CH0_HANDLER Vector6C
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#define STM32_DMA1_CH1_HANDLER Vector70
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#define STM32_DMA1_CH2_HANDLER Vector74
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#define STM32_DMA1_CH3_HANDLER Vector78
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#define STM32_DMA1_CH4_HANDLER Vector7C
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#define STM32_DMA1_CH5_HANDLER Vector80
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#define STM32_DMA1_CH6_HANDLER Vector84
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#define STM32_DMA1_CH7_HANDLER VectorFC
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#define STM32_DMA1_CH0_NUMBER 11
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#define STM32_DMA1_CH1_NUMBER 12
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#define STM32_DMA1_CH2_NUMBER 13
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#define STM32_DMA1_CH3_NUMBER 14
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#define STM32_DMA1_CH4_NUMBER 15
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#define STM32_DMA1_CH5_NUMBER 16
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#define STM32_DMA1_CH6_NUMBER 17
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#define STM32_DMA1_CH7_NUMBER 47
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#define STM32_HAS_DMA2 TRUE
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#define STM32_DMA2_CH0_HANDLER Vector120
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#define STM32_DMA2_CH1_HANDLER Vector124
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#define STM32_DMA2_CH2_HANDLER Vector128
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#define STM32_DMA2_CH3_HANDLER Vector12C
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#define STM32_DMA2_CH4_HANDLER Vector130
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#define STM32_DMA2_CH5_HANDLER Vector150
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#define STM32_DMA2_CH6_HANDLER Vector154
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#define STM32_DMA2_CH7_HANDLER Vector158
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#define STM32_DMA2_CH0_NUMBER 56
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#define STM32_DMA2_CH1_NUMBER 57
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#define STM32_DMA2_CH2_NUMBER 58
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#define STM32_DMA2_CH3_NUMBER 59
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#define STM32_DMA2_CH4_NUMBER 60
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#define STM32_DMA2_CH5_NUMBER 68
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#define STM32_DMA2_CH6_NUMBER 69
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#define STM32_DMA2_CH7_NUMBER 70
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_LINES 23
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#define STM32_EXTI_IMR_MASK 0x00000000U
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
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RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | \
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RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN | \
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RCC_AHB1ENR_GPIOFEN | \
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RCC_AHB1ENR_GPIOGEN | \
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RCC_AHB1ENR_GPIOHEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
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STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C1_RX_DMA_CHN 0x00100001
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
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STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_I2C1_TX_DMA_CHN 0x11000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C2_RX_DMA_CHN 0x00007700
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#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
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#define STM32_I2C2_TX_DMA_CHN 0x70000000
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#define STM32_HAS_I2C3 TRUE
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#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_I2C3_RX_DMA_CHN 0x00000300
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#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_I2C3_TX_DMA_CHN 0x00030000
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#define STM32_HAS_I2C4 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO TRUE
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#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_SDC_SDIO_DMA_CHN 0x04004000
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S FALSE
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#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 2))
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#define STM32_SPI1_RX_DMA_CHN 0x00000303
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#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_SPI1_TX_DMA_CHN 0x00303000
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S TRUE
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#define STM32_SPI2_I2S_FULLDUPLEX TRUE
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#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_SPI2_RX_DMA_CHN 0x00000000
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#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_SPI2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_SUPPORTS_I2S TRUE
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#define STM32_SPI3_I2S_FULLDUPLEX TRUE
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#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_SPI3_RX_DMA_CHN 0x00000000
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#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_SPI3_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 4
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 6
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#define STM32_HAS_TIM9 TRUE
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#define STM32_TIM9_IS_32BITS FALSE
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#define STM32_TIM9_CHANNELS 2
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#define STM32_HAS_TIM10 TRUE
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#define STM32_TIM10_IS_32BITS FALSE
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#define STM32_TIM10_CHANNELS 2
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#define STM32_HAS_TIM11 TRUE
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#define STM32_TIM11_IS_32BITS FALSE
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#define STM32_TIM11_CHANNELS 2
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#define STM32_HAS_TIM12 TRUE
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#define STM32_TIM12_IS_32BITS FALSE
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#define STM32_TIM12_CHANNELS 2
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#define STM32_HAS_TIM13 TRUE
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#define STM32_TIM13_IS_32BITS FALSE
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#define STM32_TIM13_CHANNELS 2
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 2
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM16 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_USART1_RX_DMA_CHN 0x00400400
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#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
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#define STM32_USART1_TX_DMA_CHN 0x40000000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_USART2_RX_DMA_CHN 0x00400000
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#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
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#define STM32_USART2_TX_DMA_CHN 0x04000000
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#define STM32_HAS_USART3 TRUE
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#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
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#define STM32_USART3_RX_DMA_CHN 0x00000040
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#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
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STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_USART3_TX_DMA_CHN 0x00074000
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#define STM32_HAS_UART4 TRUE
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#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_UART4_RX_DMA_CHN 0x00000400
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#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_UART4_TX_DMA_CHN 0x00040000
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#define STM32_HAS_UART5 TRUE
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#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
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#define STM32_UART5_RX_DMA_CHN 0x00000004
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#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
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#define STM32_UART5_TX_DMA_CHN 0x40000000
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#define STM32_HAS_USART6 TRUE
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#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 2))
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#define STM32_USART6_RX_DMA_CHN 0x00000550
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#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_USART6_TX_DMA_CHN 0x55000000
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#define STM32_HAS_UART7 FALSE
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#define STM32_HAS_UART8 FALSE
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#define STM32_HAS_LPUART1 FALSE
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/* USB attributes.*/
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 TRUE
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#define STM32_HAS_OTG2 TRUE
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/* IWDG attributes.*/
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#define STM32_HAS_IWDG TRUE
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#define STM32_IWDG_IS_WINDOWED FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC TRUE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D TRUE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC TRUE
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#define STM32_FSMC_IS_FMC TRUE
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#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 4) |\
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STM32_DMA_STREAM_ID_MSK(2, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_FSMC_DMA_CHN 0x03010201
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define STM32_HAS_CRC TRUE
|
||||
#define STM32_CRC_PROGRAMMABLE FALSE
|
||||
|
||||
#endif /* defined(STM32F446xx) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32F439xx, STM32F429xx, STM32F437xx, STM32F427xx. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -423,7 +757,8 @@
|
|||
#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F2XX. */
|
||||
/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F205xx */
|
||||
/* STM32F215xx, STM32F207xx, STM32F217xx. */
|
||||
/*===========================================================================*/
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F2XX)
|
||||
/* ADC attributes.*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue