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Improvements to the PAL drivers. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2867 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
gdisirio 2011-04-03 11:29:27 +00:00
parent 8d2e166f09
commit c4fec713d2
10 changed files with 40 additions and 60 deletions
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25
os/hal/include/pal.h
View File

@ -263,9 +263,8 @@ typedef struct {
* @api
*/
#if !defined(pal_lld_setport) || defined(__DOXYGEN__)
#define palSetPort(port, bits) { \
palWritePort(port, palReadLatch(port) | (bits)); \
}
#define palSetPort(port, bits) \
palWritePort(port, palReadLatch(port) | (bits))
#else
#define palSetPort(port, bits) pal_lld_setport(port, bits)
#endif
@ -286,9 +285,8 @@ typedef struct {
* @api
*/
#if !defined(pal_lld_clearport) || defined(__DOXYGEN__)
#define palClearPort(port, bits) { \
palWritePort(port, palReadLatch(port) & ~(bits)); \
}
#define palClearPort(port, bits) \
palWritePort(port, palReadLatch(port) & ~(bits))
#else
#define palClearPort(port, bits) pal_lld_clearport(port, bits)
#endif
@ -309,9 +307,8 @@ typedef struct {
* @api
*/
#if !defined(pal_lld_toggleport) || defined(__DOXYGEN__)
#define palTogglePort(port, bits) { \
palWritePort(port, palReadLatch(port) ^ (bits)); \
}
#define palTogglePort(port, bits) \
palWritePort(port, palReadLatch(port) ^ (bits))
#else
#define palTogglePort(port, bits) pal_lld_toggleport(port, bits)
#endif
@ -347,10 +344,9 @@ typedef struct {
* @api
*/
#if !defined(pal_lld_writegroup) || defined(__DOXYGEN__)
#define palWriteGroup(port, mask, offset, bits) { \
#define palWriteGroup(port, mask, offset, bits) \
palWritePort(port, (palReadLatch(port) & ~((mask) << (offset))) | \
(((bits) & (mask)) << (offset))); \
}
(((bits) & (mask)) << (offset)))
#else
#define palWriteGroup(port, mask, offset, bits) \
pal_lld_writegroup(port, mask, offset, bits)
@ -416,10 +412,9 @@ typedef struct {
* @api
*/
#if !defined(pal_lld_writepad) || defined(__DOXYGEN__)
#define palWritePad(port, pad, bit) { \
#define palWritePad(port, pad, bit) \
palWritePort(port, (palReadLatch(port) & ~PAL_PORT_BIT(pad)) | \
(((bit) & 1) << pad)); \
}
(((bit) & 1) << pad))
#else
#define palWritePad(port, pad, bit) pal_lld_writepad(port, pad, bit)
#endif

21
os/hal/platforms/AT91SAM7/pal_lld.h
View File

@ -155,9 +155,7 @@ typedef AT91PS_PIO ioportid_t;
*
* @notapi
*/
#define pal_lld_writeport(port, bits) { \
(port)->PIO_ODSR = (bits); \
}
#define pal_lld_writeport(port, bits) ((port)->PIO_ODSR = (bits))
/**
* @brief Sets a bits mask on a I/O port.
@ -169,9 +167,7 @@ typedef AT91PS_PIO ioportid_t;
*
* @notapi
*/
#define pal_lld_setport(port, bits) { \
(port)->PIO_SODR = (bits); \
}
#define pal_lld_setport(port, bits) ((port)->PIO_SODR = (bits))
/**
* @brief Clears a bits mask on a I/O port.
@ -183,9 +179,7 @@ typedef AT91PS_PIO ioportid_t;
*
* @notapi
*/
#define pal_lld_clearport(port, bits) { \
(port)->PIO_CODR = (bits); \
}
#define pal_lld_clearport(port, bits) ((port)->PIO_CODR = (bits))
/**
* @brief Writes a group of bits.
@ -201,11 +195,10 @@ typedef AT91PS_PIO ioportid_t;
*
* @notapi
*/
#define pal_lld_writegroup(port, mask, offset, bits) { \
(port)->PIO_OWER = (mask) << (offset); \
(port)->PIO_ODSR = (bits) << (offset); \
(port)->PIO_OWDR = (mask) << (offset); \
}
#define pal_lld_writegroup(port, mask, offset, bits) \
((port)->PIO_OWER = (mask) << (offset), \
(port)->PIO_ODSR = (bits) << (offset), \
(port)->PIO_OWDR = (mask) << (offset))
/**
* @brief Pads group mode setup.

13
os/hal/platforms/LPC214x/pal_lld.h
View File

@ -194,11 +194,10 @@ typedef FIO * ioportid_t;
*
* @notapi
*/
#define pal_lld_writegroup(port, mask, offset, bits) { \
(port)->FIO_MASK = ~((mask) << (offset)); \
(port)->FIO_PIN = (bits) << (offset); \
(port)->FIO_MASK = 0; \
}
#define pal_lld_writegroup(port, mask, offset, bits) \
((port)->FIO_MASK = ~((mask) << (offset)), \
(port)->FIO_PIN = (bits) << (offset), \
(port)->FIO_MASK = 0)
/**
* @brief Pads group mode setup.
@ -236,9 +235,7 @@ typedef FIO * ioportid_t;
*
* @notapi
*/
#define pal_lld_lpc214x_set_direction(port, dir) { \
(port)->FIO_DIR = (dir); \
}
#define pal_lld_lpc214x_set_direction(port, dir) ((port)->FIO_DIR = (dir))
extern const PALConfig pal_default_config;

4
os/hal/platforms/MSP430/pal_lld.h
View File

@ -255,9 +255,7 @@ typedef msp430_ioport_t *ioportid_t;
*
* @notapi
*/
#define pal_lld_writeport(port, bits) { \
(port)->iop_common.out.reg_p = (bits); \
}
#define pal_lld_writeport(port, bits) ((port)->iop_common.out.reg_p = (bits))
/**
* @brief Pads group mode setup.

9
os/hal/platforms/Posix/pal_lld.h
View File

@ -129,10 +129,9 @@ typedef sim_vio_port_t *ioportid_t;
*
* @param[in] config architecture-dependent ports configuration
*/
#define pal_lld_init(config) { \
vio_port_1 = (config)->VP1Data; \
vio_port_2 = (config)->VP2Data; \
}
#define pal_lld_init(config) \
(vio_port_1 = (config)->VP1Data, \
vio_port_2 = (config)->VP2Data)
/**
* @brief Reads the physical I/O port states.
@ -178,7 +177,7 @@ typedef sim_vio_port_t *ioportid_t;
* @param[in] mask group mask
* @param[in] mode group mode
*/
#define pal_lld_setgroupmode(port, mask, mode) \
#define pal_lld_setgroupmode(port, mask, mode) \
_pal_lld_setgroupmode(port, mask, mode)
#if !defined(__DOXYGEN__)

7
os/hal/platforms/STM32/pal_lld.h
View File

@ -279,10 +279,9 @@ typedef GPIO_TypeDef * ioportid_t;
*
* @notapi
*/
#define pal_lld_writegroup(port, mask, offset, bits) { \
(port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \
(((bits) & (mask)) << (offset)); \
}
#define pal_lld_writegroup(port, mask, offset, bits) \
((port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \
(((bits) & (mask)) << (offset)))
/**
* @brief Pads group mode setup.

5
os/hal/platforms/STM8L/pal_lld.h
View File

@ -175,7 +175,7 @@ typedef GPIO_TypeDef *ioportid_t;
*
* @notapi
*/
#define pal_lld_init(config) *IOPORTS = *(config)
#define pal_lld_init(config) (*IOPORTS = *(config))
/**
* @brief Reads the physical I/O port states.
@ -215,7 +215,6 @@ typedef GPIO_TypeDef *ioportid_t;
*/
#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
/**
* @brief Pads group mode setup.
* @details This function programs a pads group belonging to the same port
@ -231,7 +230,7 @@ typedef GPIO_TypeDef *ioportid_t;
* @notapi
*/
#define pal_lld_setgroupmode(port, mask, mode) \
_pal_lld_setgroupmode(port, mask, mode)
_pal_lld_setgroupmode(port, mask, mode)
extern ROMCONST PALConfig pal_default_config;

5
os/hal/platforms/STM8S/pal_lld.h
View File

@ -160,7 +160,7 @@ typedef GPIO_TypeDef *ioportid_t;
*
* @notapi
*/
#define pal_lld_init(config) *IOPORTS = *(config)
#define pal_lld_init(config) (*IOPORTS = *(config))
/**
* @brief Reads the physical I/O port states.
@ -200,7 +200,6 @@ typedef GPIO_TypeDef *ioportid_t;
*/
#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
/**
* @brief Pads group mode setup.
* @details This function programs a pads group belonging to the same port
@ -216,7 +215,7 @@ typedef GPIO_TypeDef *ioportid_t;
* @notapi
*/
#define pal_lld_setgroupmode(port, mask, mode) \
_pal_lld_setgroupmode(port, mask, mode)
_pal_lld_setgroupmode(port, mask, mode)
extern ROMCONST PALConfig pal_default_config;

9
os/hal/platforms/Win32/pal_lld.h
View File

@ -129,10 +129,9 @@ typedef sim_vio_port_t *ioportid_t;
*
* @param[in] config architecture-dependent ports configuration
*/
#define pal_lld_init(config) { \
vio_port_1 = (config)->VP1Data; \
vio_port_2 = (config)->VP2Data; \
}
#define pal_lld_init(config) \
(vio_port_1 = (config)->VP1Data, \
vio_port_2 = (config)->VP2Data)
/**
* @brief Reads the physical I/O port states.
@ -178,7 +177,7 @@ typedef sim_vio_port_t *ioportid_t;
* @param[in] mask group mask
* @param[in] mode group mode
*/
#define pal_lld_setgroupmode(port, mask, mode) \
#define pal_lld_setgroupmode(port, mask, mode) \
_pal_lld_setgroupmode(port, mask, mode)
#if !defined(__DOXYGEN__)

2
readme.txt
View File

@ -96,6 +96,8 @@
- NEW: Added board files for the Olimex STM32-P107.
- NEW: Improved setup packets handling in the USB driver through a specific
callback.
- NEW: Improvements to the PAL driver and various implementation in order
to make them more parenthesis friendly.
- OPT: Simplified Serial over USB driver configuration.
- CHANGE: Renamed the demo ARMCM3-STM32F107-GCC in ARMCM3-STM32F107 and added
IAR and Keil projects.