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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3063 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2011-06-19 14:41:33 +00:00
parent 45765c3f76
commit c4c18450ff
9 changed files with 295 additions and 194 deletions
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15
boards/ST_STM32L_DISCOVERY/board.c
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@ -27,14 +27,15 @@
* This variable is used by the HAL when initializing the PAL driver.
*/
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*const PALConfig pal_default_config =
const PALConfig pal_default_config =
{
{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
};*/
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR},
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR},
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR},
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR},
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR},
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR}
};
#endif
/*

2
boards/ST_STM32L_DISCOVERY/board.h
View File

@ -108,7 +108,7 @@
PIN_PUDR_FLOATING(4) | \
PIN_PUDR_FLOATING(GPIOB_LED4) | \
PIN_PUDR_FLOATING(GPIOB_LED3)))
#define VAL_GPIOB_ODR 0xFFFFFFFF
#define VAL_GPIOB_ODR 0xFFFFFF3F
/*
* Port C setup.

2
demos/ARMCM3-STM32L152-DISCOVERY/halconf.h
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@ -38,7 +38,7 @@
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL FALSE
#define HAL_USE_PAL TRUE
#endif
/**

6
demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp
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@ -2037,6 +2037,12 @@
<file>
<name>$PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\hal_lld.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\pal_lld.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\pal_lld.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.c</name>
</file>

7
os/hal/platforms/STM32/hal_lld.h
View File

@ -89,6 +89,7 @@
#define STM32_HAS_GPIOE TRUE
#define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOH FALSE
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 FALSE
@ -156,6 +157,7 @@
#define STM32_HAS_GPIOE TRUE
#define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOH FALSE
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 TRUE
@ -223,6 +225,7 @@
#define STM32_HAS_GPIOE FALSE
#define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOH FALSE
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 FALSE
@ -290,6 +293,7 @@
#define STM32_HAS_GPIOE TRUE
#define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOH FALSE
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 TRUE
@ -357,6 +361,7 @@
#define STM32_HAS_GPIOE TRUE
#define STM32_HAS_GPIOF TRUE
#define STM32_HAS_GPIOG TRUE
#define STM32_HAS_GPIOH FALSE
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 TRUE
@ -424,6 +429,7 @@
#define STM32_HAS_GPIOE TRUE
#define STM32_HAS_GPIOF TRUE
#define STM32_HAS_GPIOG TRUE
#define STM32_HAS_GPIOH FALSE
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 TRUE
@ -491,6 +497,7 @@
#define STM32_HAS_GPIOE TRUE
#define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOH FALSE
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 TRUE

62
os/hal/platforms/STM32L1xx/hal_lld.h
View File

@ -133,6 +133,68 @@
#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */
#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */
/* STM32L1xx capabilities.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_CAN1 FALSE
#define STM32_HAS_CAN2 FALSE
#define STM32_HAS_DAC TRUE
#define STM32_HAS_DMA1 TRUE
#define STM32_HAS_DMA2 FALSE
#define STM32_HAS_ETH FALSE
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
#define STM32_HAS_GPIOC TRUE
#define STM32_HAS_GPIOD TRUE
#define STM32_HAS_GPIOE TRUE
#define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOH TRUE
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 TRUE
#define STM32_HAS_RTC TRUE
#define STM32_HAS_SDIO FALSE
#define STM32_HAS_SPI1 TRUE
#define STM32_HAS_SPI2 TRUE
#define STM32_HAS_SPI3 FALSE
#define STM32_HAS_TIM1 FALSE
#define STM32_HAS_TIM2 TRUE
#define STM32_HAS_TIM3 TRUE
#define STM32_HAS_TIM4 TRUE
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM6 TRUE
#define STM32_HAS_TIM7 TRUE
#define STM32_HAS_TIM8 FALSE
#define STM32_HAS_TIM9 TRUE
#define STM32_HAS_TIM10 TRUE
#define STM32_HAS_TIM11 TRUE
#define STM32_HAS_TIM12 FALSE
#define STM32_HAS_TIM13 FALSE
#define STM32_HAS_TIM14 FALSE
#define STM32_HAS_TIM15 FALSE
#define STM32_HAS_TIM16 FALSE
#define STM32_HAS_TIM17 FALSE
#define STM32_HAS_USART1 TRUE
#define STM32_HAS_USART2 TRUE
#define STM32_HAS_USART3 TRUE
#define STM32_HAS_UART3 FALSE
#define STM32_HAS_UART4 FALSE
#define STM32_HAS_USB TRUE
#define STM32_HAS_OTG1 FALSE
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/

57
os/hal/platforms/STM32L1xx/pal_lld.c
View File

@ -58,6 +58,17 @@
/* Driver local functions. */
/*===========================================================================*/
static void initgpio(GPIO_TypeDef *gpiop, const stm32_gpio_setup_t *config) {
gpiop->MODER = config->moder;
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = 0;
gpiop->AFRH = 0;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
@ -79,37 +90,31 @@ void _pal_lld_init(const PALConfig *config) {
/*
* Enables the GPIO related clocks.
*/
RCC->APB2ENR |= APB2_EN_MASK;
RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN |
RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN |
RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN;
RCC->AHBLPENR |= RCC_AHBLPENR_GPIOALPEN | RCC_AHBLPENR_GPIOBLPEN |
RCC_AHBLPENR_GPIOCLPEN | RCC_AHBLPENR_GPIODLPEN |
RCC_AHBLPENR_GPIOELPEN | RCC_AHBLPENR_GPIOHLPEN;
/*
* Initial GPIO setup.
*/
GPIOA->ODR = config->PAData.odr;
GPIOA->CRH = config->PAData.crh;
GPIOA->CRL = config->PAData.crl;
GPIOB->ODR = config->PBData.odr;
GPIOB->CRH = config->PBData.crh;
GPIOB->CRL = config->PBData.crl;
GPIOC->ODR = config->PCData.odr;
GPIOC->CRH = config->PCData.crh;
GPIOC->CRL = config->PCData.crl;
GPIOD->ODR = config->PDData.odr;
GPIOD->CRH = config->PDData.crh;
GPIOD->CRL = config->PDData.crl;
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
GPIOE->ODR = config->PEData.odr;
GPIOE->CRH = config->PEData.crh;
GPIOE->CRL = config->PEData.crl;
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
GPIOF->ODR = config->PFData.odr;
GPIOF->CRH = config->PFData.crh;
GPIOF->CRL = config->PFData.crl;
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
GPIOG->ODR = config->PGData.odr;
GPIOG->CRH = config->PGData.crh;
GPIOG->CRL = config->PGData.crl;
initgpio(GPIOA, &config->PAData);
initgpio(GPIOB, &config->PBData);
initgpio(GPIOC, &config->PCData);
initgpio(GPIOD, &config->PDData);
#if STM32_HAS_GPIOE
initgpio(GPIOE, &config->PEData);
#endif
#if STM32_HAS_GPIOF
initgpio(GPIOF, &config->PFData);
#endif
#if STM32_HAS_GPIOG
initgpio(GPIOG, &config->PGData);
#endif
#if STM32_HAS_GPIOH
initgpio(GPIOH, &config->PHData);
#endif
}
@ -133,6 +138,7 @@ void _pal_lld_init(const PALConfig *config) {
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
uint_fast8_t mode) {
#if 0
static const uint8_t cfgtab[] = {
4, /* PAL_MODE_RESET, implemented as input.*/
2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/
@ -179,6 +185,7 @@ void _pal_lld_setgroupmode(ioportid_t port,
}
port->CRH = (port->CRH & mh) | crh;
port->CRL = (port->CRL & ml) | crl;
#endif
}
#endif /* HAL_USE_PAL */

31
os/hal/platforms/STM32L1xx/pal_lld.h
View File

@ -19,8 +19,8 @@
*/
/**
* @file STM32/pal_lld.h
* @brief STM32 GPIO low level driver header.
* @file STM32L1xx/pal_lld.h
* @brief STM32L1xx GPIO low level driver header.
*
* @addtogroup PAL
* @{
@ -134,6 +134,23 @@
/* I/O Ports Types and constants. */
/*===========================================================================*/
/**
* @brief STM32 GPIO registers block.
*/
typedef struct {
volatile uint32_t MODER;
volatile uint32_t OTYPER;
volatile uint32_t OSPEEDR;
volatile uint32_t PUPDR;
volatile uint32_t IDR;
volatile uint32_t ODR;
volatile uint32_t BSRR;
volatile uint32_t LCKR;
volatile uint32_t AFRL;
volatile uint32_t AFRH;
} GPIO_TypeDef;
/**
* @brief GPIO port setup info.
*/
@ -166,21 +183,21 @@ typedef struct {
stm32_gpio_setup_t PCData;
/** @brief Port D setup data.*/
stm32_gpio_setup_t PDData;
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
#if STM32_HAS_GPIOE
/** @brief Port E setup data.*/
stm32_gpio_setup_t PEData;
#endif
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
#if STM32_HAS_GPIOF
/** @brief Port F setup data.*/
stm32_gpio_setup_t PFData;
#endif
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
#if STM32_HAS_GPIOG
/** @brief Port G setup data.*/
stm32_gpio_setup_t PGData;
#endif
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
#if STM32_HAS_GPIOH
/** @brief Port H setup data.*/
stm32_gpio_setup_t PGData;
stm32_gpio_setup_t PHData;
#endif
} PALConfig;

3
os/hal/platforms/STM32L1xx/stm32l1xx.h
View File

@ -411,7 +411,7 @@ typedef struct
/**
* @brief General Purpose IO
*/
#if 0
typedef struct
{
__IO uint32_t MODER;
@ -428,6 +428,7 @@ typedef struct
__IO uint32_t LCKR;
__IO uint32_t AFR[2];
} GPIO_TypeDef;
#endif
/**
* @brief SysTem Configuration