git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3063 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
45765c3f76
commit
c4c18450ff
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@ -27,14 +27,15 @@
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* This variable is used by the HAL when initializing the PAL driver.
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*/
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/*const PALConfig pal_default_config =
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const PALConfig pal_default_config =
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{
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{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
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{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
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{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
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{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
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{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
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};*/
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{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR},
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{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR},
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{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR},
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR},
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR},
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR}
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};
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#endif
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/*
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@ -108,7 +108,7 @@
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PIN_PUDR_FLOATING(4) | \
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PIN_PUDR_FLOATING(GPIOB_LED4) | \
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PIN_PUDR_FLOATING(GPIOB_LED3)))
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#define VAL_GPIOB_ODR 0xFFFFFFFF
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#define VAL_GPIOB_ODR 0xFFFFFF3F
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/*
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* Port C setup.
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@ -38,7 +38,7 @@
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* @brief Enables the PAL subsystem.
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*/
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#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
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#define HAL_USE_PAL FALSE
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#define HAL_USE_PAL TRUE
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#endif
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/**
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@ -2037,6 +2037,12 @@
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<file>
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<name>$PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\hal_lld.h</name>
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</file>
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<file>
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<name>$PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\pal_lld.c</name>
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</file>
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<file>
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<name>$PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\pal_lld.h</name>
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</file>
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<file>
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<name>$PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.c</name>
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</file>
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@ -89,6 +89,7 @@
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 FALSE
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@ -156,6 +157,7 @@
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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@ -223,6 +225,7 @@
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 FALSE
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@ -290,6 +293,7 @@
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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@ -357,6 +361,7 @@
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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@ -424,6 +429,7 @@
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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@ -491,6 +497,7 @@
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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@ -133,6 +133,68 @@
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#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */
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#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */
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/* STM32L1xx capabilities.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_DAC TRUE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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#define STM32_HAS_ETH FALSE
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_RTC TRUE
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#define STM32_HAS_SDIO FALSE
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#define STM32_HAS_SPI1 TRUE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_TIM1 FALSE
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#define STM32_HAS_TIM2 TRUE
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 TRUE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 TRUE
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#define STM32_HAS_TIM7 TRUE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 TRUE
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#define STM32_HAS_TIM10 TRUE
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#define STM32_HAS_TIM11 TRUE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM16 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 TRUE
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#define STM32_HAS_UART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_USB TRUE
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#define STM32_HAS_OTG1 FALSE
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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@ -58,6 +58,17 @@
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/* Driver local functions. */
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/*===========================================================================*/
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static void initgpio(GPIO_TypeDef *gpiop, const stm32_gpio_setup_t *config) {
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gpiop->MODER = config->moder;
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gpiop->OTYPER = config->otyper;
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gpiop->OSPEEDR = config->ospeedr;
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gpiop->PUPDR = config->pupdr;
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gpiop->ODR = config->odr;
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gpiop->AFRL = 0;
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gpiop->AFRH = 0;
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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@ -79,37 +90,31 @@ void _pal_lld_init(const PALConfig *config) {
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/*
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* Enables the GPIO related clocks.
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*/
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RCC->APB2ENR |= APB2_EN_MASK;
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN |
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN |
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN;
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RCC->AHBLPENR |= RCC_AHBLPENR_GPIOALPEN | RCC_AHBLPENR_GPIOBLPEN |
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RCC_AHBLPENR_GPIOCLPEN | RCC_AHBLPENR_GPIODLPEN |
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RCC_AHBLPENR_GPIOELPEN | RCC_AHBLPENR_GPIOHLPEN;
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/*
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* Initial GPIO setup.
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*/
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GPIOA->ODR = config->PAData.odr;
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GPIOA->CRH = config->PAData.crh;
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GPIOA->CRL = config->PAData.crl;
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GPIOB->ODR = config->PBData.odr;
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GPIOB->CRH = config->PBData.crh;
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GPIOB->CRL = config->PBData.crl;
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GPIOC->ODR = config->PCData.odr;
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GPIOC->CRH = config->PCData.crh;
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GPIOC->CRL = config->PCData.crl;
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GPIOD->ODR = config->PDData.odr;
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GPIOD->CRH = config->PDData.crh;
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GPIOD->CRL = config->PDData.crl;
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#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
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GPIOE->ODR = config->PEData.odr;
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GPIOE->CRH = config->PEData.crh;
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GPIOE->CRL = config->PEData.crl;
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#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
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GPIOF->ODR = config->PFData.odr;
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GPIOF->CRH = config->PFData.crh;
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GPIOF->CRL = config->PFData.crl;
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#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
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GPIOG->ODR = config->PGData.odr;
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GPIOG->CRH = config->PGData.crh;
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GPIOG->CRL = config->PGData.crl;
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initgpio(GPIOA, &config->PAData);
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initgpio(GPIOB, &config->PBData);
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initgpio(GPIOC, &config->PCData);
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initgpio(GPIOD, &config->PDData);
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#if STM32_HAS_GPIOE
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initgpio(GPIOE, &config->PEData);
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#endif
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#if STM32_HAS_GPIOF
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initgpio(GPIOF, &config->PFData);
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#endif
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#if STM32_HAS_GPIOG
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initgpio(GPIOG, &config->PGData);
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#endif
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#if STM32_HAS_GPIOH
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initgpio(GPIOH, &config->PHData);
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#endif
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}
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@ -133,7 +138,8 @@ void _pal_lld_init(const PALConfig *config) {
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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uint_fast8_t mode) {
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static const uint8_t cfgtab[] = {
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#if 0
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static const uint8_t cfgtab[] = {
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4, /* PAL_MODE_RESET, implemented as input.*/
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2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/
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4, /* PAL_MODE_INPUT */
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@ -179,6 +185,7 @@ void _pal_lld_setgroupmode(ioportid_t port,
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}
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port->CRH = (port->CRH & mh) | crh;
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port->CRL = (port->CRL & ml) | crl;
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#endif
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}
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#endif /* HAL_USE_PAL */
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@ -19,8 +19,8 @@
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*/
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/**
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* @file STM32/pal_lld.h
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* @brief STM32 GPIO low level driver header.
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* @file STM32L1xx/pal_lld.h
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* @brief STM32L1xx GPIO low level driver header.
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*
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* @addtogroup PAL
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* @{
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@ -134,20 +134,37 @@
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/* I/O Ports Types and constants. */
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/*===========================================================================*/
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/**
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* @brief STM32 GPIO registers block.
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*/
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typedef struct {
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volatile uint32_t MODER;
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volatile uint32_t OTYPER;
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volatile uint32_t OSPEEDR;
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volatile uint32_t PUPDR;
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volatile uint32_t IDR;
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volatile uint32_t ODR;
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volatile uint32_t BSRR;
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volatile uint32_t LCKR;
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volatile uint32_t AFRL;
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volatile uint32_t AFRH;
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} GPIO_TypeDef;
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/**
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* @brief GPIO port setup info.
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*/
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typedef struct {
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/** Initial value for MODER register.*/
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uint32_t moder;
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uint32_t moder;
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/** Initial value for OTYPER register.*/
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uint32_t otyper;
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uint32_t otyper;
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/** Initial value for OSPEEDR register.*/
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uint32_t ospeedr;
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uint32_t ospeedr;
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/** Initial value for PUPDR register.*/
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uint32_t pupdr;
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uint32_t pupdr;
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/** Initial value for ODR register.*/
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uint32_t odr;
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uint32_t odr;
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} stm32_gpio_setup_t;
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/**
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@ -166,21 +183,21 @@ typedef struct {
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stm32_gpio_setup_t PCData;
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/** @brief Port D setup data.*/
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stm32_gpio_setup_t PDData;
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#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
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#if STM32_HAS_GPIOE
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/** @brief Port E setup data.*/
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stm32_gpio_setup_t PEData;
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#endif
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#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
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#if STM32_HAS_GPIOF
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/** @brief Port F setup data.*/
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stm32_gpio_setup_t PFData;
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#endif
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#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
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#if STM32_HAS_GPIOG
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/** @brief Port G setup data.*/
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stm32_gpio_setup_t PGData;
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#endif
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#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
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#if STM32_HAS_GPIOH
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/** @brief Port H setup data.*/
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stm32_gpio_setup_t PGData;
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stm32_gpio_setup_t PHData;
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#endif
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} PALConfig;
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@ -4,9 +4,9 @@
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* @author MCD Application Team
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* @version V1.0.0
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* @date 31-December-2010
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32L1xx devices.
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32L1xx devices.
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******************************************************************************
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* @attention
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*
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@ -28,20 +28,20 @@
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/** @addtogroup stm32l1xx
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* @{
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*/
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#ifndef __STM32L1XX_H
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#define __STM32L1XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#endif
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/* Uncomment the line below according to the target STM32L device used in your
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application
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/* Uncomment the line below according to the target STM32L device used in your
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application
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*/
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#if !defined (STM32L1XX_MD)
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@ -50,7 +50,7 @@
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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- Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx
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- Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx
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microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
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*/
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@ -62,30 +62,30 @@
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#if !defined USE_STDPERIPH_DRIVER
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_STDPERIPH_DRIVER*/
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#endif
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/**
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* @brief In the following line adjust the value of External High Speed oscillator (HSE)
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used in your application
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used in your application
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Tip: To avoid modifying this file each time you need to use different HSE, you
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can define the HSE value in your toolchain compiler preprocessor.
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*/
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*/
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#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
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/**
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* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
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||||
Timeout value
|
||||
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
|
||||
Timeout value
|
||||
*/
|
||||
#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
|
||||
|
||||
/**
|
||||
* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
|
||||
Timeout value
|
||||
* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
|
||||
Timeout value
|
||||
*/
|
||||
#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
|
||||
|
||||
|
|
@ -100,10 +100,10 @@
|
|||
/**
|
||||
* @brief STM32L1xx Standard Peripheral Library version number
|
||||
*/
|
||||
#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
|
||||
|(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
|
||||
|(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
|
||||
|
|
@ -118,8 +118,8 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32L1xx Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
* @brief STM32L1xx Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
#define __MPU_PRESENT 1 /*!< STM32L provides MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
|
||||
|
|
@ -196,7 +196,7 @@ typedef enum IRQn
|
|||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
*/
|
||||
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
||||
|
||||
|
|
@ -205,41 +205,41 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
|||
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
/* ARM Compiler
|
||||
------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source
|
||||
module. Using the 'Options for File' dialog you can simply change the
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source
|
||||
module. Using the 'Options for File' dialog you can simply change the
|
||||
'Code / Const' area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the
|
||||
'Options for Target' dialog.
|
||||
Available memory areas are declared in the 'Target' tab of the
|
||||
'Options for Target' dialog.
|
||||
*/
|
||||
#define __RAM_FUNC FLASH_Status
|
||||
#define __RAM_FUNC FLASH_Status
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc FLASH_Status
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".data")))".
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".data")))".
|
||||
*/
|
||||
#define __RAM_FUNC FLASH_Status __attribute__((section(".data")))
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
/* TASKING Compiler
|
||||
----------------
|
||||
RAM functions are defined using a specific toolchain pragma. This pragma is
|
||||
defined in the stm32l1xx_flash_ramfunc.c
|
||||
RAM functions are defined using a specific toolchain pragma. This pragma is
|
||||
defined in the stm32l1xx_flash_ramfunc.c
|
||||
*/
|
||||
#define __RAM_FUNC FLASH_Status
|
||||
|
||||
|
|
@ -251,10 +251,10 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
|
|||
|
||||
/** @addtogroup Peripheral_registers_structures
|
||||
* @{
|
||||
*/
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Analog to Digital Converter
|
||||
/**
|
||||
* @brief Analog to Digital Converter
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
|
|
@ -291,8 +291,8 @@ typedef struct
|
|||
} ADC_Common_TypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Comparator
|
||||
/**
|
||||
* @brief Comparator
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
|
|
@ -300,8 +300,8 @@ typedef struct
|
|||
__IO uint32_t CSR;
|
||||
} COMP_TypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC calculation unit
|
||||
/**
|
||||
* @brief CRC calculation unit
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
|
|
@ -313,7 +313,7 @@ typedef struct
|
|||
__IO uint32_t CR;
|
||||
} CRC_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Digital to Analog Converter
|
||||
*/
|
||||
|
||||
|
|
@ -332,10 +332,10 @@ typedef struct
|
|||
__IO uint32_t DHR8RD;
|
||||
__IO uint32_t DOR1;
|
||||
__IO uint32_t DOR2;
|
||||
__IO uint32_t SR;
|
||||
__IO uint32_t SR;
|
||||
} DAC_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Debug MCU
|
||||
*/
|
||||
|
||||
|
|
@ -347,7 +347,7 @@ typedef struct
|
|||
__IO uint32_t APB2FZ;
|
||||
}DBGMCU_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief DMA Controller
|
||||
*/
|
||||
|
||||
|
|
@ -365,7 +365,7 @@ typedef struct
|
|||
__IO uint32_t IFCR;
|
||||
} DMA_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief External Interrupt/Event Controller
|
||||
*/
|
||||
|
||||
|
|
@ -379,7 +379,7 @@ typedef struct
|
|||
__IO uint32_t PR;
|
||||
} EXTI_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief FLASH Registers
|
||||
*/
|
||||
|
||||
|
|
@ -393,13 +393,13 @@ typedef struct
|
|||
__IO uint32_t OPTKEYR;
|
||||
__IO uint32_t SR;
|
||||
__IO uint32_t OBR;
|
||||
__IO uint32_t WRPR;
|
||||
__IO uint32_t WRPR;
|
||||
} FLASH_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Option Bytes Registers
|
||||
*/
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t RDP;
|
||||
|
|
@ -408,10 +408,10 @@ typedef struct
|
|||
__IO uint32_t WRP23;
|
||||
} OB_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief General Purpose IO
|
||||
*/
|
||||
|
||||
#if 0
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t MODER;
|
||||
|
|
@ -428,8 +428,9 @@ typedef struct
|
|||
__IO uint32_t LCKR;
|
||||
__IO uint32_t AFR[2];
|
||||
} GPIO_TypeDef;
|
||||
#endif
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief SysTem Configuration
|
||||
*/
|
||||
|
||||
|
|
@ -440,7 +441,7 @@ typedef struct
|
|||
__IO uint32_t EXTICR[4];
|
||||
} SYSCFG_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Inter-integrated Circuit Interface
|
||||
*/
|
||||
|
||||
|
|
@ -466,7 +467,7 @@ typedef struct
|
|||
uint16_t RESERVED8;
|
||||
} I2C_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Independent WATCHDOG
|
||||
*/
|
||||
|
||||
|
|
@ -479,7 +480,7 @@ typedef struct
|
|||
} IWDG_TypeDef;
|
||||
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief LCD
|
||||
*/
|
||||
|
||||
|
|
@ -493,7 +494,7 @@ typedef struct
|
|||
__IO uint32_t RAM[16];
|
||||
} LCD_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Power Control
|
||||
*/
|
||||
|
||||
|
|
@ -503,7 +504,7 @@ typedef struct
|
|||
__IO uint32_t CSR;
|
||||
} PWR_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Reset and Clock Control
|
||||
*/
|
||||
|
||||
|
|
@ -521,12 +522,12 @@ typedef struct
|
|||
__IO uint32_t APB1ENR;
|
||||
__IO uint32_t AHBLPENR;
|
||||
__IO uint32_t APB2LPENR;
|
||||
__IO uint32_t APB1LPENR;
|
||||
__IO uint32_t CSR;
|
||||
__IO uint32_t APB1LPENR;
|
||||
__IO uint32_t CSR;
|
||||
} RCC_TypeDef;
|
||||
|
||||
/**
|
||||
* @brief Routing Interface
|
||||
/**
|
||||
* @brief Routing Interface
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
|
|
@ -539,7 +540,7 @@ typedef struct
|
|||
__IO uint32_t HYSCR3;
|
||||
} RI_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Real-Time Clock
|
||||
*/
|
||||
|
||||
|
|
@ -587,7 +588,7 @@ typedef struct
|
|||
__IO uint32_t BKP19R;
|
||||
} RTC_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Serial Peripheral Interface
|
||||
*/
|
||||
|
||||
|
|
@ -606,10 +607,10 @@ typedef struct
|
|||
__IO uint16_t RXCRCR;
|
||||
uint16_t RESERVED5;
|
||||
__IO uint16_t TXCRCR;
|
||||
uint16_t RESERVED6;
|
||||
uint16_t RESERVED6;
|
||||
} SPI_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief TIM
|
||||
*/
|
||||
|
||||
|
|
@ -657,10 +658,10 @@ typedef struct
|
|||
uint16_t RESERVED20;
|
||||
} TIM_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Universal Synchronous Asynchronous Receiver Transmitter
|
||||
*/
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint16_t SR;
|
||||
|
|
@ -679,7 +680,7 @@ typedef struct
|
|||
uint16_t RESERVED6;
|
||||
} USART_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief Window WATCHDOG
|
||||
*/
|
||||
|
||||
|
|
@ -693,7 +694,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -767,10 +768,10 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Peripheral_declaration
|
||||
* @{
|
||||
*/
|
||||
*/
|
||||
|
||||
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
|
||||
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
|
||||
|
|
@ -819,7 +820,7 @@ typedef struct
|
|||
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
|
||||
|
||||
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
|
||||
#define OB ((OB_TypeDef *) OB_BASE)
|
||||
#define OB ((OB_TypeDef *) OB_BASE)
|
||||
|
||||
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
||||
|
||||
|
|
@ -830,11 +831,11 @@ typedef struct
|
|||
/** @addtogroup Exported_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral Registers Bits Definition */
|
||||
/******************************************************************************/
|
||||
|
|
@ -888,7 +889,7 @@ typedef struct
|
|||
#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
||||
|
||||
#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
|
||||
|
||||
|
||||
/******************* Bit definition for ADC_CR2 register ********************/
|
||||
#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
|
||||
#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
|
||||
|
|
@ -1014,7 +1015,7 @@ typedef struct
|
|||
#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
|
||||
|
||||
#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
|
||||
#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
|
||||
#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
|
||||
|
|
@ -1281,7 +1282,7 @@ typedef struct
|
|||
|
||||
|
||||
/******************* Bit definition for ADC_JSQR register *******************/
|
||||
#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
|
||||
#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
|
||||
#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
|
|
@ -1341,7 +1342,7 @@ typedef struct
|
|||
/******************* Bit definition for ADC_CCR register ********************/
|
||||
#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/
|
||||
#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
|
||||
|
||||
/******************************************************************************/
|
||||
|
|
@ -2016,9 +2017,9 @@ typedef struct
|
|||
#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
|
||||
#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
|
||||
#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
|
||||
#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
|
||||
#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
|
||||
#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
|
||||
#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
|
||||
#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
|
||||
#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
|
||||
|
||||
/****************** Bit definition for FLASH_PDKEYR register ******************/
|
||||
#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
|
||||
|
|
@ -2059,7 +2060,7 @@ typedef struct
|
|||
/* General Purpose IOs (GPIO) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/******************* Bit definition for GPIO_MODER register *****************/
|
||||
/******************* Bit definition for GPIO_MODER register *****************/
|
||||
#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
|
||||
#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
|
||||
#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
|
||||
|
|
@ -2109,7 +2110,7 @@ typedef struct
|
|||
#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
|
||||
#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
|
||||
|
||||
/******************* Bit definition for GPIO_OTYPER register ****************/
|
||||
/******************* Bit definition for GPIO_OTYPER register ****************/
|
||||
#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
|
||||
#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
|
||||
#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
|
||||
|
|
@ -2127,7 +2128,7 @@ typedef struct
|
|||
#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
|
||||
#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
|
||||
|
||||
/******************* Bit definition for GPIO_OSPEEDR register ***************/
|
||||
/******************* Bit definition for GPIO_OSPEEDR register ***************/
|
||||
#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
|
||||
#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
|
||||
#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
|
||||
|
|
@ -2177,7 +2178,7 @@ typedef struct
|
|||
#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
|
||||
#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
|
||||
|
||||
/******************* Bit definition for GPIO_PUPDR register *****************/
|
||||
/******************* Bit definition for GPIO_PUPDR register *****************/
|
||||
#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
|
||||
#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
|
||||
#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
|
||||
|
|
@ -2227,7 +2228,7 @@ typedef struct
|
|||
#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
|
||||
#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
|
||||
|
||||
/******************* Bit definition for GPIO_IDR register *******************/
|
||||
/******************* Bit definition for GPIO_IDR register *******************/
|
||||
#define GPIO_OTYPER_IDR_0 ((uint32_t)0x00000001)
|
||||
#define GPIO_OTYPER_IDR_1 ((uint32_t)0x00000002)
|
||||
#define GPIO_OTYPER_IDR_2 ((uint32_t)0x00000004)
|
||||
|
|
@ -2245,7 +2246,7 @@ typedef struct
|
|||
#define GPIO_OTYPER_IDR_14 ((uint32_t)0x00004000)
|
||||
#define GPIO_OTYPER_IDR_15 ((uint32_t)0x00008000)
|
||||
|
||||
/******************* Bit definition for GPIO_ODR register *******************/
|
||||
/******************* Bit definition for GPIO_ODR register *******************/
|
||||
#define GPIO_OTYPER_ODR_0 ((uint32_t)0x00000001)
|
||||
#define GPIO_OTYPER_ODR_1 ((uint32_t)0x00000002)
|
||||
#define GPIO_OTYPER_ODR_2 ((uint32_t)0x00000004)
|
||||
|
|
@ -2263,7 +2264,7 @@ typedef struct
|
|||
#define GPIO_OTYPER_ODR_14 ((uint32_t)0x00004000)
|
||||
#define GPIO_OTYPER_ODR_15 ((uint32_t)0x00008000)
|
||||
|
||||
/******************* Bit definition for GPIO_BSRR register ******************/
|
||||
/******************* Bit definition for GPIO_BSRR register ******************/
|
||||
#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
|
||||
#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
|
||||
#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
|
||||
|
|
@ -2770,7 +2771,7 @@ typedef struct
|
|||
#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
|
||||
#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */
|
||||
#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */
|
||||
|
||||
|
||||
/***************** Bit definition for RCC_APB2RSTR register *****************/
|
||||
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */
|
||||
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */
|
||||
|
|
@ -2900,7 +2901,7 @@ typedef struct
|
|||
|
||||
#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */
|
||||
#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */
|
||||
|
||||
|
||||
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
|
||||
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */
|
||||
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
|
||||
|
|
@ -3303,9 +3304,9 @@ typedef struct
|
|||
#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
|
||||
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
|
||||
|
|
@ -3313,9 +3314,9 @@ typedef struct
|
|||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) /*!< PH[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
|
||||
|
|
@ -3323,9 +3324,9 @@ typedef struct
|
|||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) /*!< PH[1] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
|
||||
|
|
@ -3333,9 +3334,9 @@ typedef struct
|
|||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) /*!< PH[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
|
||||
|
|
@ -3348,36 +3349,36 @@ typedef struct
|
|||
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
|
||||
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
|
||||
|
|
@ -3389,37 +3390,37 @@ typedef struct
|
|||
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
|
||||
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
|
||||
|
|
@ -3432,42 +3433,42 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
|
||||
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Routing Interface (RI) */
|
||||
|
|
@ -4253,7 +4254,7 @@ typedef struct
|
|||
|
||||
#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */
|
||||
|
||||
/****************** Bit definition for USB_BTABLE register ******************/
|
||||
/****************** Bit definition for USB_BTABLE register ******************/
|
||||
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */
|
||||
|
||||
/*!< Buffer descriptor table */
|
||||
|
|
@ -5093,7 +5094,7 @@ typedef struct
|
|||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
#ifdef USE_STDPERIPH_DRIVER
|
||||
#include "stm32l1xx_conf.h"
|
||||
|
|
|
|||
Loading…
Reference in New Issue