New STM32F3xx CMSIS headers.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8587 35acf78f-673a-0410-8e92-d51de3d6d3f4master
Giovanni Di Sirio
parent
d7b170b525
commit
c246d898d2
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@ -2,9 +2,9 @@
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******************************************************************************
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* @file stm32f301x8.h
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* @author MCD Application Team
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* @version V2.0.1
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* @date 18-June-2014
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* @brief CMSIS STM32F301x6/STM32F301x8 Devices Peripheral Access Layer Header File.
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* @version V2.2.0
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* @date 13-November-2015
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* @brief CMSIS STM32F301x8 Devices Peripheral Access Layer Header File.
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*
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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@ -14,7 +14,7 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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@ -63,11 +63,11 @@
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/**
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* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
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*/
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#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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#define __MPU_PRESENT 0 /*!< STM32F301x6/STM32F301x8 devices do not provide an MPU */
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#define __NVIC_PRIO_BITS 4 /*!< STM32F301x6/STM32F301x8 devices use 4 Bits for the Priority Levels */
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#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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#define __MPU_PRESENT 0 /*!< STM32F301x8 devices do not provide an MPU */
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#define __NVIC_PRIO_BITS 4 /*!< STM32F301x8 devices use 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1 /*!< STM32F301x6/STM32F301x8 devices provide an FPU */
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#define __FPU_PRESENT 1 /*!< STM32F301x8 devices provide an FPU */
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/**
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* @}
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@ -78,7 +78,7 @@
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*/
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/**
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* @brief STM32F301x6/STM32F301x8 device Interrupt Number Definition, according to the selected device
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* @brief STM32F301x8 devices Interrupt Number Definition, according to the selected device
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* in @ref Library_configuration_section
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*/
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typedef enum
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@ -129,12 +129,12 @@ typedef enum
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
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SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel1 underrun error Interrupt */
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TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
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COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
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COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
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I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */
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I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
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FPU_IRQn = 81 /*!< Floating point Interrupt */
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FPU_IRQn = 81, /*!< Floating point Interrupt */
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} IRQn_Type;
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/**
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@ -235,20 +235,20 @@ typedef struct
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typedef struct
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{
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__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
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__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
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__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
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__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
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__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
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__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
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__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
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__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
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__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
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__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
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__IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
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__IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
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__IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
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__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
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__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
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__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
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__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
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__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
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__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
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__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
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__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
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__IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
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__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
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__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
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} DAC_TypeDef;
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/**
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@ -277,8 +277,8 @@ typedef struct
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typedef struct
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{
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__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
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__IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
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__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
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__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
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} DMA_TypeDef;
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/**
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@ -287,20 +287,20 @@ typedef struct
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typedef struct
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{
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__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
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__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
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__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
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__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
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__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
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__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
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uint32_t RESERVED1; /*!< Reserved, 0x18 */
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uint32_t RESERVED2; /*!< Reserved, 0x1C */
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__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
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__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
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__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
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__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
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__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
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__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
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__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
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__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
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__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
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__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
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__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
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__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
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uint32_t RESERVED1; /*!< Reserved, 0x18 */
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uint32_t RESERVED2; /*!< Reserved, 0x1C */
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__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
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__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
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__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
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__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
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__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
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__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
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}EXTI_TypeDef;
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/**
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@ -348,11 +348,10 @@ typedef struct
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__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
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__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
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__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
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__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
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__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
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__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
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__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
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__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
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__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
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__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
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}GPIO_TypeDef;
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/**
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@ -370,10 +369,10 @@ typedef struct
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typedef struct
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{
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__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
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__IO uint32_t RESERVED0; /*!< Reserved, 0x04 */
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__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
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__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
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__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
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uint32_t RESERVED; /*!< Reserved, 0x04 */
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__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
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__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
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} SYSCFG_TypeDef;
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/**
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@ -480,6 +479,10 @@ typedef struct
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__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
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__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
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__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
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__IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
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__IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
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__IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
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__IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
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} RTC_TypeDef;
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@ -489,13 +492,13 @@ typedef struct
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typedef struct
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{
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__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
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__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
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__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
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__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
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__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
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__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
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__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
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__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
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__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
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__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
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__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
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__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
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__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
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} SPI_TypeDef;
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@ -531,7 +534,6 @@ typedef struct
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__IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
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} TIM_TypeDef;
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/**
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* @brief Touch Sensing Controller (TSC)
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*/
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@ -591,7 +593,6 @@ typedef struct
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#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
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#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
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#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
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#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
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#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
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@ -663,7 +664,7 @@ typedef struct
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#define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
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#define ADC1_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
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#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
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#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
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/**
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* @}
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*/
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#define PWR ((PWR_TypeDef *) PWR_BASE)
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#define DAC ((DAC_TypeDef *) DAC_BASE)
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#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
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#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
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#define COMP ((COMP_TypeDef *) COMP_BASE)
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#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
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#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
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#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
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#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
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#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
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#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
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#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
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#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
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#define USART1 ((USART_TypeDef *) USART1_BASE)
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#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
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#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
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#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
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/**
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* @}
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*/
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/* Analog to Digital Converter SAR (ADC) */
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/* */
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/******************************************************************************/
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/******************** Bit definition for ADC_ISR register ********************/
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#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
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#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
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@ -1521,6 +1524,7 @@ typedef struct
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/* Analog Comparators (COMP) */
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/* */
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/******************************************************************************/
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/********************** Bit definition for COMP2_CSR register ***************/
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#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
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#define COMP2_CSR_COMP2INPDAC ((uint32_t)0x00000002) /*!< COMP2 non inverting input to DAC output */
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#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
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/******************* Bit definition for CRC_IDR register ********************/
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#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
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#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
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/******************** Bit definition for CRC_CR register ********************/
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#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
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#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
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#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
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/***************** Bit definition for DAC_SWTRIGR register ******************/
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#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
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/* External Interrupt/Event Controller (EXTI) */
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/* */
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/******************************************************************************/
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/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
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/******************* Bit definition for EXTI_IMR register *******************/
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#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
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#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
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#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
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#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
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#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
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#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
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#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
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#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
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#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
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/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
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/******************* Bit definition for EXTI_EMR register *******************/
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#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
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#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
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#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
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#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
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#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
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#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
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#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
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#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
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#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
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/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
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/****************** Bit definition for EXTI_RTSR register *******************/
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#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
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#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
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#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
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|
|||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
|
||||
#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
|
||||
#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
|
||||
#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
|
||||
#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
|
||||
#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
|
||||
#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
|
||||
#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
|
||||
#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
||||
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
||||
|
|
@ -2001,14 +2007,11 @@ typedef struct
|
|||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
|
||||
#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
|
||||
#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
|
||||
#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
|
||||
#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
|
||||
#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
|
||||
#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
|
||||
#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
|
||||
#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
||||
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
||||
|
|
@ -2032,14 +2035,11 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
|
||||
#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
|
||||
#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
|
||||
#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
|
||||
#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
|
||||
#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
|
||||
#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
|
||||
#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
|
||||
#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
||||
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
||||
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
||||
|
|
@ -2063,12 +2063,37 @@ typedef struct
|
|||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
|
||||
#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
|
||||
#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
|
||||
#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
|
||||
#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
|
||||
#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
|
||||
#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
|
||||
#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
|
||||
#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
|
||||
#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_IMR2 register ******************/
|
||||
#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
|
||||
#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
|
||||
#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
|
||||
#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
|
||||
#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
|
||||
#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
|
||||
#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -2133,6 +2158,11 @@ typedef struct
|
|||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
|
||||
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
|
||||
#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
|
||||
#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
|
||||
|
||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
||||
|
|
@ -2162,6 +2192,7 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* General Purpose I/O (GPIO) */
|
||||
|
|
@ -2476,7 +2507,7 @@ typedef struct
|
|||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||||
|
|
@ -2490,6 +2521,9 @@ typedef struct
|
|||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||||
|
||||
/* Legacy defines */
|
||||
#define I2C_CR1_DFN I2C_CR1_DNF
|
||||
|
||||
/****************** Bit definition for I2C_CR2 register ********************/
|
||||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||||
|
|
@ -2509,9 +2543,17 @@ typedef struct
|
|||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||||
|
||||
/******************* Bit definition for I2C_OAR2 register *******************/
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
|
||||
#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
||||
#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
||||
#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
||||
#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
||||
#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
||||
#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
||||
#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
|
||||
/******************* Bit definition for I2C_TIMINGR register *****************/
|
||||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||||
|
|
@ -2833,8 +2875,8 @@ typedef struct
|
|||
#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
|
||||
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
|
||||
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
|
||||
|
||||
/***************** Bit definition for RCC_APB2ENR register ******************/
|
||||
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
|
||||
|
|
@ -2954,10 +2996,12 @@ typedef struct
|
|||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||||
/* Legacy defines */
|
||||
#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
|
||||
|
||||
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
|
||||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||||
|
|
@ -2976,16 +3020,12 @@ typedef struct
|
|||
#define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
|
||||
#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
|
||||
#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
|
||||
|
||||
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
|
||||
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
|
||||
#define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
|
||||
#define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
|
||||
#define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
|
||||
|
||||
|
|
@ -2993,7 +3033,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
|
||||
|
|
@ -3002,7 +3042,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
|
||||
|
|
@ -3371,8 +3411,20 @@ typedef struct
|
|||
/******************** Bits definition for RTC_BKP15R register ***************/
|
||||
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP16R register ***************/
|
||||
#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP17R register ***************/
|
||||
#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP18R register ***************/
|
||||
#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP19R register ***************/
|
||||
#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Number of backup registers ******************************/
|
||||
#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_NUMBER 20
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3471,7 +3523,7 @@ typedef struct
|
|||
/* System Configuration(SYSCFG) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register *****************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
|
||||
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
|
@ -3480,7 +3532,7 @@ typedef struct
|
|||
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00003800) /*!< DMA remap mask */
|
||||
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
|
||||
|
|
@ -3675,9 +3727,9 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register *****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3942,7 +3994,7 @@ typedef struct
|
|||
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
|
||||
|
||||
/******************* Bit definition for TIM_RCR register ********************/
|
||||
#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
|
||||
#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
|
||||
|
|
@ -4498,11 +4550,23 @@ typedef struct
|
|||
((INSTANCE) == DMA1_Channel7))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
/****************************** I2C Instances *********************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
||||
|
|
@ -4513,12 +4577,12 @@ typedef struct
|
|||
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
|
||||
((INSTANCE) == SPI3))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** OPAMP Instances *******************************/
|
||||
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** RTC Instances *********************************/
|
||||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||||
|
||||
|
|
@ -4566,12 +4630,12 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : at least 5 capture/compare channels *******/
|
||||
#define IS_TIM_CC5_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : at least 6 capture/compare channels *******/
|
||||
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/************************** TIM Instances : Advanced-control timers ***********/
|
||||
|
||||
/****************** TIM Instances : supporting clock selection ****************/
|
||||
|
|
@ -4614,7 +4678,7 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : supporting Hall interface *****************/
|
||||
#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : supporting input XOR function *************/
|
||||
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
|
||||
|
|
@ -4650,8 +4714,8 @@ typedef struct
|
|||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting the break function *************/
|
||||
|
|
@ -4725,11 +4789,11 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : supporting 2 break inputs *****************/
|
||||
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : supporting DMA generation on Update events*/
|
||||
#define IS_TIM_DMA_INSTANCE(INSTANCE)\
|
||||
|
|
@ -4787,7 +4851,7 @@ typedef struct
|
|||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
||||
/******************** UART Instances : Wake-up from Stop mode **********************/
|
||||
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
|
@ -4796,7 +4860,7 @@ typedef struct
|
|||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/****************** UART Instances : Auto Baud Rate detection *****************/
|
||||
/****************** UART Instances : Driver Enable ****************************/
|
||||
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
|
@ -4807,6 +4871,8 @@ typedef struct
|
|||
/*********************** UART Instances : IRDA mode ***************************/
|
||||
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
/******************** UART Instances : Support of continuous communication using DMA ****/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
|
||||
/****************************** WWDG Instances ********************************/
|
||||
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
||||
|
||||
|
|
@ -4824,27 +4890,34 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define HRTIM1_FLT_IRQn I2C3_ER_IRQn
|
||||
#define HRTIM1_TIME_IRQn I2C3_EV_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM18_DAC2_IRQn TIM1_CC_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
|
||||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
|
||||
#define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@
|
|||
******************************************************************************
|
||||
* @file stm32f302x8.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CMSIS STM32F302x6/STM32F302x8 Devices Peripheral Access Layer Header File.
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS STM32F302x8 Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -63,11 +63,11 @@
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< STM32F302x6/STM32F302x8 devices do not provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F302x6/STM32F302x8 devices use 4 Bits for the Priority Levels */
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< STM32F302x8 devices do not provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F302x8 devices use 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F302x6/STM32F302x8 devices provide an FPU */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F302x8 devices provide an FPU */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32F302x6/STM32F302x8 device Interrupt Number Definition, according to the selected device
|
||||
* @brief STM32F302x8 devices Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum
|
||||
|
|
@ -134,15 +134,15 @@ typedef enum
|
|||
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
|
||||
USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
|
||||
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
|
||||
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel1 underrun error Interrupt */
|
||||
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
|
||||
COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
|
||||
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
|
||||
I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */
|
||||
I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
|
||||
USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
|
||||
USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
|
||||
USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
|
||||
USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
|
||||
USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
|
||||
FPU_IRQn = 81 /*!< Floating point Interrupt */
|
||||
FPU_IRQn = 81, /*!< Floating point Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
|
|
@ -303,20 +303,20 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
|
||||
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
|
||||
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
|
||||
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
|
||||
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
|
||||
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
|
||||
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
|
||||
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
|
||||
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
|
||||
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
|
||||
__IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
|
||||
__IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
__IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
|
||||
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
|
||||
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
|
||||
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
|
||||
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
|
||||
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
|
||||
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
|
||||
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
|
||||
__IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
|
||||
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
|
||||
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
|
||||
} DAC_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -345,8 +345,8 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
|
||||
} DMA_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -355,20 +355,20 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
}EXTI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -416,11 +416,10 @@ typedef struct
|
|||
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
||||
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
||||
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
||||
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
|
||||
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
|
||||
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
|
||||
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
||||
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
}GPIO_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -438,10 +437,10 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t RESERVED0; /*!< Reserved, 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
uint32_t RESERVED; /*!< Reserved, 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
} SYSCFG_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -548,6 +547,10 @@ typedef struct
|
|||
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
|
||||
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
|
||||
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
|
||||
__IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
|
||||
__IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
|
||||
__IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
|
||||
__IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
|
||||
} RTC_TypeDef;
|
||||
|
||||
|
||||
|
|
@ -557,13 +560,13 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
||||
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
||||
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
|
||||
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
||||
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
||||
} SPI_TypeDef;
|
||||
|
|
@ -599,7 +602,6 @@ typedef struct
|
|||
__IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
|
||||
} TIM_TypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Touch Sensing Controller (TSC)
|
||||
*/
|
||||
|
|
@ -673,9 +675,9 @@ typedef struct
|
|||
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
|
||||
__IO uint16_t RESERVEDB; /*!< Reserved */
|
||||
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
|
||||
__IO uint16_t RESERVEDC; /*!< Reserved */
|
||||
__IO uint16_t RESERVEDC; /*!< Reserved */
|
||||
__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
|
||||
__IO uint16_t RESERVEDD; /*!< Reserved */
|
||||
__IO uint16_t RESERVEDD; /*!< Reserved */
|
||||
} USB_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -695,7 +697,6 @@ typedef struct
|
|||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
|
|
@ -770,7 +771,7 @@ typedef struct
|
|||
#define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
|
||||
#define ADC1_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
|
||||
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -796,13 +797,13 @@ typedef struct
|
|||
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
|
||||
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
|
||||
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
|
||||
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE)
|
||||
|
|
@ -831,6 +832,7 @@ typedef struct
|
|||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||||
#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
|
||||
#define USB ((USB_TypeDef *) USB_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -852,6 +854,7 @@ typedef struct
|
|||
/* Analog to Digital Converter SAR (ADC) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************** Bit definition for ADC_ISR register ********************/
|
||||
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
|
||||
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
|
||||
|
|
@ -1630,6 +1633,7 @@ typedef struct
|
|||
/* Analog Comparators (COMP) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/********************** Bit definition for COMP2_CSR register ***************/
|
||||
#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
|
||||
#define COMP2_CSR_COMP2INPDAC ((uint32_t)0x00000002) /*!< COMP2 non inverting input to DAC output */
|
||||
|
|
@ -3038,7 +3042,7 @@ typedef struct
|
|||
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
||||
|
||||
/******************* Bit definition for CRC_IDR register ********************/
|
||||
#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
|
||||
/******************** Bit definition for CRC_CR register ********************/
|
||||
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
|
||||
|
|
@ -3083,7 +3087,6 @@ typedef struct
|
|||
|
||||
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
|
||||
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
|
||||
|
||||
/***************** Bit definition for DAC_SWTRIGR register ******************/
|
||||
#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
|
||||
|
||||
|
|
@ -3139,6 +3142,7 @@ typedef struct
|
|||
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
|
||||
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
|
||||
#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x40000000)
|
||||
#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
|
||||
|
||||
/******************** Bit definition for DBGMCU_APB2_FZ register ************/
|
||||
#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
|
||||
|
|
@ -3249,7 +3253,7 @@ typedef struct
|
|||
/* External Interrupt/Event Controller (EXTI) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
|
||||
/******************* Bit definition for EXTI_IMR register *******************/
|
||||
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
||||
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
||||
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
||||
|
|
@ -3279,8 +3283,11 @@ typedef struct
|
|||
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
|
||||
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
|
||||
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
|
||||
#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
|
||||
#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
|
||||
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
|
||||
/******************* Bit definition for EXTI_EMR register *******************/
|
||||
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
||||
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
||||
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
||||
|
|
@ -3310,8 +3317,11 @@ typedef struct
|
|||
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
|
||||
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
|
||||
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
|
||||
#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
|
||||
#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
|
||||
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_RTSR register *******************/
|
||||
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
||||
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
||||
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
||||
|
|
@ -3335,14 +3345,11 @@ typedef struct
|
|||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
|
||||
#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
|
||||
#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
|
||||
#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
|
||||
#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
|
||||
#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
|
||||
#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
|
||||
#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
|
||||
#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
||||
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
||||
|
|
@ -3366,14 +3373,11 @@ typedef struct
|
|||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
|
||||
#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
|
||||
#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
|
||||
#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
|
||||
#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
|
||||
#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
|
||||
#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
|
||||
#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
|
||||
#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
||||
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
||||
|
|
@ -3397,14 +3401,11 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
|
||||
#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
|
||||
#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
|
||||
#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
|
||||
#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
|
||||
#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
|
||||
#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
|
||||
#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
|
||||
#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
||||
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
||||
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
||||
|
|
@ -3428,12 +3429,37 @@ typedef struct
|
|||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
|
||||
#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
|
||||
#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
|
||||
#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
|
||||
#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
|
||||
#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
|
||||
#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
|
||||
#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
|
||||
#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
|
||||
#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_IMR2 register ******************/
|
||||
#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
|
||||
#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
|
||||
#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
|
||||
#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
|
||||
#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
|
||||
#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
|
||||
#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3498,6 +3524,11 @@ typedef struct
|
|||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
|
||||
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
|
||||
#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
|
||||
#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
|
||||
|
||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
||||
|
|
@ -3527,6 +3558,7 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* General Purpose I/O (GPIO) */
|
||||
|
|
@ -3841,7 +3873,7 @@ typedef struct
|
|||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||||
|
|
@ -3855,6 +3887,9 @@ typedef struct
|
|||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||||
|
||||
/* Legacy defines */
|
||||
#define I2C_CR1_DFN I2C_CR1_DNF
|
||||
|
||||
/****************** Bit definition for I2C_CR2 register ********************/
|
||||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||||
|
|
@ -3874,9 +3909,17 @@ typedef struct
|
|||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||||
|
||||
/******************* Bit definition for I2C_OAR2 register *******************/
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
|
||||
#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
||||
#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
||||
#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
||||
#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
||||
#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
||||
#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
||||
#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
|
||||
/******************* Bit definition for I2C_TIMINGR register *****************/
|
||||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||||
|
|
@ -4206,8 +4249,8 @@ typedef struct
|
|||
#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
|
||||
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
|
||||
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
|
||||
|
||||
/***************** Bit definition for RCC_APB2ENR register ******************/
|
||||
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
|
||||
|
|
@ -4329,10 +4372,12 @@ typedef struct
|
|||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||||
/* Legacy defines */
|
||||
#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
|
||||
|
||||
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
|
||||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||||
|
|
@ -4351,16 +4396,12 @@ typedef struct
|
|||
#define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
|
||||
#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
|
||||
#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
|
||||
|
||||
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
|
||||
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
|
||||
#define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
|
||||
#define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
|
||||
#define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
|
||||
|
||||
|
|
@ -4368,7 +4409,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
|
||||
|
|
@ -4377,7 +4418,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
|
||||
|
|
@ -4746,8 +4787,20 @@ typedef struct
|
|||
/******************** Bits definition for RTC_BKP15R register ***************/
|
||||
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP16R register ***************/
|
||||
#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP17R register ***************/
|
||||
#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP18R register ***************/
|
||||
#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP19R register ***************/
|
||||
#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Number of backup registers ******************************/
|
||||
#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_NUMBER 20
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -4846,7 +4899,7 @@ typedef struct
|
|||
/* System Configuration(SYSCFG) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register *****************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
|
||||
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
|
@ -4856,7 +4909,7 @@ typedef struct
|
|||
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00003800) /*!< DMA remap mask */
|
||||
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
|
||||
|
|
@ -5051,9 +5104,9 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register *****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -5318,7 +5371,7 @@ typedef struct
|
|||
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
|
||||
|
||||
/******************* Bit definition for TIM_RCR register ********************/
|
||||
#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
|
||||
#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
|
||||
|
|
@ -5804,7 +5857,7 @@ typedef struct
|
|||
|
||||
/**************************** ISTR interrupt events *************************/
|
||||
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
|
||||
#define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
|
||||
#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
|
||||
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
|
||||
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
|
||||
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
|
||||
|
|
@ -5815,8 +5868,11 @@ typedef struct
|
|||
#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
|
||||
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
|
||||
|
||||
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
|
||||
#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
|
||||
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
|
||||
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
|
||||
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
|
||||
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
|
||||
|
|
@ -5825,9 +5881,12 @@ typedef struct
|
|||
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
|
||||
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
|
||||
|
||||
/************************* CNTR control register bits definitions ***********/
|
||||
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
|
||||
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
|
||||
#define USB_CNTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
|
||||
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
|
||||
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
|
||||
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
|
||||
|
|
@ -5838,10 +5897,14 @@ typedef struct
|
|||
#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
|
||||
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
|
||||
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
|
||||
#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
|
||||
#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
|
||||
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
|
||||
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
|
||||
#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
|
||||
|
||||
/*************************** LPM register bits definitions ******************/
|
||||
#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
|
||||
#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
|
||||
|
|
@ -5995,11 +6058,23 @@ typedef struct
|
|||
((INSTANCE) == DMA1_Channel7))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
/****************************** I2C Instances *********************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
||||
|
|
@ -6010,12 +6085,12 @@ typedef struct
|
|||
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
|
||||
((INSTANCE) == SPI3))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** OPAMP Instances *******************************/
|
||||
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** RTC Instances *********************************/
|
||||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||||
|
||||
|
|
@ -6063,12 +6138,12 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : at least 5 capture/compare channels *******/
|
||||
#define IS_TIM_CC5_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : at least 6 capture/compare channels *******/
|
||||
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/************************** TIM Instances : Advanced-control timers ***********/
|
||||
|
||||
/****************** TIM Instances : supporting clock selection ****************/
|
||||
|
|
@ -6111,7 +6186,7 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : supporting Hall interface *****************/
|
||||
#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : supporting input XOR function *************/
|
||||
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
|
||||
|
|
@ -6147,8 +6222,8 @@ typedef struct
|
|||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting the break function *************/
|
||||
|
|
@ -6222,11 +6297,11 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : supporting 2 break inputs *****************/
|
||||
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : supporting DMA generation on Update events*/
|
||||
#define IS_TIM_DMA_INSTANCE(INSTANCE)\
|
||||
|
|
@ -6284,7 +6359,7 @@ typedef struct
|
|||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
||||
/******************** UART Instances : Wake-up from Stop mode **********************/
|
||||
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
|
@ -6293,7 +6368,7 @@ typedef struct
|
|||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/****************** UART Instances : Auto Baud Rate detection *****************/
|
||||
/****************** UART Instances : Driver Enable ****************************/
|
||||
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
|
@ -6304,6 +6379,8 @@ typedef struct
|
|||
/*********************** UART Instances : IRDA mode ***************************/
|
||||
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
/******************** UART Instances : Support of continuous communication using DMA ****/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
|
||||
/****************************** USB Instances *********************************/
|
||||
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
|
||||
|
||||
|
|
@ -6324,31 +6401,42 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define HRTIM1_FLT_IRQn I2C3_ER_IRQn
|
||||
#define HRTIM1_TIME_IRQn I2C3_EV_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM18_DAC2_IRQn TIM1_CC_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
#define CEC_IRQn USBWakeUp_IRQn
|
||||
#define USBWakeUp_IRQn USBWakeUp_RMP_IRQn
|
||||
#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
|
||||
#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
|
||||
|
||||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
|
||||
#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
|
||||
#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
|
||||
#define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
#define CEC_IRQHandler USBWakeUp_IRQHandler
|
||||
#define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler
|
||||
#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
|
||||
#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@
|
|||
******************************************************************************
|
||||
* @file stm32f302xc.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CMSIS STM32F302xB/STM32F302xC Devices Peripheral Access Layer Header File.
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS STM32F302xC Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -63,11 +63,11 @@
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< STM32F302xB/STM32F302xC devices provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F302xB/STM32F302xC devices use 4 Bits for the Priority Levels */
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< STM32F302xC devices provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F302xC devices use 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F302xB/STM32F302xC devices provide an FPU */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F302xC devices provide an FPU */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32F302xB/STM32F302xC device Interrupt Number Definition, according to the selected device
|
||||
* @brief STM32F302xC devices Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum
|
||||
|
|
@ -139,7 +139,7 @@ typedef enum
|
|||
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
|
||||
UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
|
||||
UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
|
||||
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error Interrupts */
|
||||
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
|
||||
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
|
||||
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
|
||||
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
|
||||
|
|
@ -147,10 +147,10 @@ typedef enum
|
|||
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
|
||||
COMP1_2_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt via EXTI Line21 and 22 */
|
||||
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
|
||||
USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
|
||||
USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
|
||||
USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
|
||||
USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
|
||||
USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
|
||||
FPU_IRQn = 81 /*!< Floating point Interrupt */
|
||||
FPU_IRQn = 81, /*!< Floating point Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
|
|
@ -316,14 +316,14 @@ typedef struct
|
|||
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
|
||||
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
|
||||
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
|
||||
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
|
||||
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
|
||||
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
|
||||
__IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
|
||||
__IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
__IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
|
||||
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
|
||||
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
|
||||
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
|
||||
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
|
||||
__IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
|
||||
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
|
||||
} DAC_TypeDef;
|
||||
|
||||
|
|
@ -353,8 +353,8 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
|
||||
} DMA_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -363,20 +363,20 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
}EXTI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -424,11 +424,10 @@ typedef struct
|
|||
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
||||
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
||||
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
||||
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
|
||||
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
|
||||
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
|
||||
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
||||
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
}GPIO_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -446,10 +445,10 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t RESERVED0; /*!< Reserved, 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
uint32_t RESERVED; /*!< Reserved, 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
} SYSCFG_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -565,13 +564,13 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
||||
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
||||
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
|
||||
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
||||
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
||||
} SPI_TypeDef;
|
||||
|
|
@ -680,7 +679,7 @@ typedef struct
|
|||
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
|
||||
__IO uint16_t RESERVEDB; /*!< Reserved */
|
||||
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
|
||||
__IO uint16_t RESERVEDC; /*!< Reserved */
|
||||
__IO uint16_t RESERVEDC; /*!< Reserved */
|
||||
} USB_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -700,7 +699,6 @@ typedef struct
|
|||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
|
|
@ -789,7 +787,7 @@ typedef struct
|
|||
#define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
|
||||
#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
|
||||
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -816,17 +814,17 @@ typedef struct
|
|||
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
|
||||
#define CAN ((CAN_TypeDef *) CAN_BASE)
|
||||
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
|
||||
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
|
||||
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
|
||||
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
||||
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
||||
|
|
@ -864,6 +862,7 @@ typedef struct
|
|||
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
|
||||
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
|
||||
#define USB ((USB_TypeDef *) USB_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -885,6 +884,7 @@ typedef struct
|
|||
/* Analog to Digital Converter SAR (ADC) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************** Bit definition for ADC_ISR register ********************/
|
||||
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
|
||||
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
|
||||
|
|
@ -1663,6 +1663,7 @@ typedef struct
|
|||
/* Analog Comparators (COMP) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/********************** Bit definition for COMP1_CSR register ***************/
|
||||
#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
|
||||
#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
|
||||
|
|
@ -1796,7 +1797,6 @@ typedef struct
|
|||
#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
|
||||
#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
|
||||
#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
|
||||
#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
|
||||
#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
|
||||
#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
|
||||
|
||||
|
|
@ -3160,7 +3160,7 @@ typedef struct
|
|||
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
||||
|
||||
/******************* Bit definition for CRC_IDR register ********************/
|
||||
#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
|
||||
/******************** Bit definition for CRC_CR register ********************/
|
||||
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
|
||||
|
|
@ -3205,31 +3205,8 @@ typedef struct
|
|||
|
||||
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
|
||||
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
|
||||
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
|
||||
#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
|
||||
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
|
||||
|
||||
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
|
||||
#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
|
||||
#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
|
||||
#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
|
||||
|
||||
#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
|
||||
#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
|
||||
#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
|
||||
|
||||
#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
|
||||
#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
||||
#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
||||
#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
|
||||
#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
|
||||
|
||||
#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
|
||||
#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
|
||||
|
||||
/***************** Bit definition for DAC_SWTRIGR register ******************/
|
||||
#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
|
||||
#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
|
||||
|
||||
/***************** Bit definition for DAC_DHR12R1 register ******************/
|
||||
#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
|
||||
|
|
@ -3240,36 +3217,20 @@ typedef struct
|
|||
/****************** Bit definition for DAC_DHR8R1 register ******************/
|
||||
#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
|
||||
|
||||
/***************** Bit definition for DAC_DHR12R2 register ******************/
|
||||
#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
|
||||
|
||||
/***************** Bit definition for DAC_DHR12L2 register ******************/
|
||||
#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
|
||||
|
||||
/****************** Bit definition for DAC_DHR8R2 register ******************/
|
||||
#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
|
||||
|
||||
/***************** Bit definition for DAC_DHR12RD register ******************/
|
||||
#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
|
||||
#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
|
||||
|
||||
/***************** Bit definition for DAC_DHR12LD register ******************/
|
||||
#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
|
||||
#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
|
||||
|
||||
/****************** Bit definition for DAC_DHR8RD register ******************/
|
||||
#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
|
||||
#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
|
||||
|
||||
/******************* Bit definition for DAC_DOR1 register *******************/
|
||||
#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
|
||||
|
||||
/******************* Bit definition for DAC_DOR2 register *******************/
|
||||
#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
|
||||
|
||||
/******************** Bit definition for DAC_SR register ********************/
|
||||
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
|
||||
#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3411,7 +3372,7 @@ typedef struct
|
|||
/* External Interrupt/Event Controller (EXTI) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
|
||||
/******************* Bit definition for EXTI_IMR register *******************/
|
||||
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
||||
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
||||
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
||||
|
|
@ -3441,8 +3402,11 @@ typedef struct
|
|||
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
|
||||
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
|
||||
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
|
||||
#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
|
||||
#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
|
||||
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
|
||||
/******************* Bit definition for EXTI_EMR register *******************/
|
||||
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
||||
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
||||
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
||||
|
|
@ -3472,8 +3436,11 @@ typedef struct
|
|||
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
|
||||
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
|
||||
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
|
||||
#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
|
||||
#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
|
||||
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_RTSR register *******************/
|
||||
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
||||
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
||||
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
||||
|
|
@ -3497,14 +3464,11 @@ typedef struct
|
|||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
|
||||
#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
|
||||
#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
|
||||
#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
|
||||
#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
|
||||
#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
|
||||
#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
|
||||
#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
|
||||
#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
||||
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
||||
|
|
@ -3528,14 +3492,11 @@ typedef struct
|
|||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
|
||||
#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
|
||||
#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
|
||||
#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
|
||||
#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
|
||||
#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
|
||||
#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
|
||||
#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
|
||||
#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
||||
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
||||
|
|
@ -3559,14 +3520,11 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
|
||||
#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
|
||||
#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
|
||||
#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
|
||||
#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
|
||||
#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
|
||||
#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
|
||||
#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
|
||||
#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
||||
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
||||
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
||||
|
|
@ -3590,12 +3548,37 @@ typedef struct
|
|||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
|
||||
#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
|
||||
#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
|
||||
#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
|
||||
#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
|
||||
#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
|
||||
#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
|
||||
#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
|
||||
#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
|
||||
#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_IMR2 register ******************/
|
||||
#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
|
||||
#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
|
||||
#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
|
||||
#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
|
||||
#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
|
||||
#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
|
||||
#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3660,6 +3643,11 @@ typedef struct
|
|||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
|
||||
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
|
||||
#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
|
||||
#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
|
||||
|
||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
||||
|
|
@ -3689,6 +3677,7 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* General Purpose I/O (GPIO) */
|
||||
|
|
@ -4003,7 +3992,7 @@ typedef struct
|
|||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||||
|
|
@ -4017,6 +4006,9 @@ typedef struct
|
|||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||||
|
||||
/* Legacy defines */
|
||||
#define I2C_CR1_DFN I2C_CR1_DNF
|
||||
|
||||
/****************** Bit definition for I2C_CR2 register ********************/
|
||||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||||
|
|
@ -4036,9 +4028,17 @@ typedef struct
|
|||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||||
|
||||
/******************* Bit definition for I2C_OAR2 register *******************/
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
|
||||
#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
||||
#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
||||
#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
||||
#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
||||
#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
||||
#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
||||
#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
|
||||
/******************* Bit definition for I2C_TIMINGR register *****************/
|
||||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||||
|
|
@ -4309,7 +4309,7 @@ typedef struct
|
|||
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
|
||||
|
||||
#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
|
||||
|
||||
/********************* Bit definition for RCC_CIR register ********************/
|
||||
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
|
||||
|
|
@ -4370,7 +4370,7 @@ typedef struct
|
|||
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
|
||||
#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
|
||||
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
|
||||
|
||||
/***************** Bit definition for RCC_APB2ENR register ******************/
|
||||
|
|
@ -4427,6 +4427,7 @@ typedef struct
|
|||
/******************** Bit definition for RCC_CSR register *******************/
|
||||
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
|
||||
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
|
||||
#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
|
||||
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
|
||||
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
|
||||
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
|
||||
|
|
@ -4498,10 +4499,12 @@ typedef struct
|
|||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||||
/* Legacy defines */
|
||||
#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
|
||||
|
||||
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
|
||||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||||
|
|
@ -4511,10 +4514,8 @@ typedef struct
|
|||
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
|
||||
#define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
|
||||
#define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000300) /*!< TIMSW bits */
|
||||
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
|
||||
|
||||
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
|
||||
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
|
||||
|
||||
|
|
@ -4522,7 +4523,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
|
||||
|
|
@ -4531,7 +4532,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
|
||||
|
|
@ -4540,7 +4541,7 @@ typedef struct
|
|||
#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
|
||||
|
|
@ -4549,7 +4550,7 @@ typedef struct
|
|||
#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
|
||||
|
|
@ -4919,7 +4920,7 @@ typedef struct
|
|||
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Number of backup registers ******************************/
|
||||
#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_NUMBER 16
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -5018,7 +5019,7 @@ typedef struct
|
|||
/* System Configuration(SYSCFG) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register *****************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
|
||||
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
|
@ -5029,7 +5030,7 @@ typedef struct
|
|||
#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
|
||||
|
|
@ -5223,10 +5224,10 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register *****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
|
||||
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
|
||||
|
||||
|
|
@ -5493,7 +5494,7 @@ typedef struct
|
|||
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
|
||||
|
||||
/******************* Bit definition for TIM_RCR register ********************/
|
||||
#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
|
||||
#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
|
||||
|
|
@ -5574,13 +5575,6 @@ typedef struct
|
|||
#define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
||||
#define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
||||
|
||||
/******************* Bit definition for TIM8_OR register *********************/
|
||||
#define TIM8_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
|
||||
#define TIM8_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
||||
#define TIM8_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
||||
#define TIM8_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
||||
#define TIM8_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
||||
|
||||
/****************** Bit definition for TIM_CCMR3 register *******************/
|
||||
#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
|
||||
#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
|
||||
|
|
@ -5984,7 +5978,7 @@ typedef struct
|
|||
|
||||
/**************************** ISTR interrupt events *************************/
|
||||
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
|
||||
#define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
|
||||
#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
|
||||
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
|
||||
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
|
||||
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
|
||||
|
|
@ -5994,8 +5988,11 @@ typedef struct
|
|||
#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
|
||||
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
|
||||
|
||||
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
|
||||
#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
|
||||
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
|
||||
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
|
||||
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
|
||||
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
|
||||
|
|
@ -6003,9 +6000,12 @@ typedef struct
|
|||
#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
|
||||
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
|
||||
|
||||
/************************* CNTR control register bits definitions ***********/
|
||||
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
|
||||
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
|
||||
#define USB_CNTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
|
||||
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
|
||||
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
|
||||
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
|
||||
|
|
@ -6014,10 +6014,14 @@ typedef struct
|
|||
#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
|
||||
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
|
||||
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
|
||||
#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
|
||||
#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
|
||||
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
|
||||
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
|
||||
#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
|
||||
|
||||
/******************** FNR Frame Number Register bit definitions ************/
|
||||
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
|
||||
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
|
||||
|
|
@ -6129,11 +6133,10 @@ typedef struct
|
|||
/****************************** ADC Instances *********************************/
|
||||
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
|
||||
((INSTANCE) == ADC2))
|
||||
|
||||
|
||||
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
|
||||
|
||||
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_2_COMMON)
|
||||
|
||||
/****************************** CAN Instances *********************************/
|
||||
#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
|
||||
|
||||
|
|
@ -6158,9 +6161,8 @@ typedef struct
|
|||
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
|
||||
|
||||
#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
|
||||
(((INSTANCE) == DAC1) && \
|
||||
(((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2)))
|
||||
(((INSTANCE) == DAC1) && \
|
||||
((CHANNEL) == DAC_CHANNEL_1))
|
||||
|
||||
/****************************** DMA Instances *********************************/
|
||||
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
|
||||
|
|
@ -6177,12 +6179,23 @@ typedef struct
|
|||
((INSTANCE) == DMA2_Channel5))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOD))
|
||||
|
||||
/****************************** I2C Instances *********************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
||||
|
|
@ -6192,13 +6205,13 @@ typedef struct
|
|||
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
|
||||
((INSTANCE) == SPI3))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** OPAMP Instances *******************************/
|
||||
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
|
||||
((INSTANCE) == OPAMP2))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** RTC Instances *********************************/
|
||||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||||
|
||||
|
|
@ -6256,12 +6269,12 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : at least 5 capture/compare channels *******/
|
||||
#define IS_TIM_CC5_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : at least 6 capture/compare channels *******/
|
||||
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/************************** TIM Instances : Advanced-control timers ***********/
|
||||
|
||||
/****************** TIM Instances : supporting clock selection ****************/
|
||||
|
|
@ -6318,7 +6331,7 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : supporting Hall interface *****************/
|
||||
#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : supporting input XOR function *************/
|
||||
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
|
||||
|
|
@ -6349,8 +6362,8 @@ typedef struct
|
|||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM6) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
|
|
@ -6362,10 +6375,10 @@ typedef struct
|
|||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting the break function *************/
|
||||
|
|
@ -6455,7 +6468,7 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : supporting 2 break inputs *****************/
|
||||
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
|
||||
|
|
@ -6524,7 +6537,7 @@ typedef struct
|
|||
((INSTANCE) == USART3) || \
|
||||
((INSTANCE) == UART4) || \
|
||||
((INSTANCE) == UART5))
|
||||
|
||||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
|
|
@ -6566,6 +6579,12 @@ typedef struct
|
|||
((INSTANCE) == UART4) || \
|
||||
((INSTANCE) == UART5))
|
||||
|
||||
/******************** UART Instances : Support of continuous communication using DMA ****/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3) || \
|
||||
((INSTANCE) == UART4))
|
||||
|
||||
/****************************** USB Instances *********************************/
|
||||
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
|
||||
|
||||
|
|
@ -6586,31 +6605,38 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP1_2_IRQn
|
||||
#define COMP2_IRQn COMP1_2_IRQn
|
||||
#define COMP_IRQn COMP1_2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM18_DAC2_IRQn TIM1_CC_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
#define CEC_IRQn USBWakeUp_IRQn
|
||||
#define USBWakeUp_IRQn USBWakeUp_RMP_IRQn
|
||||
#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
|
||||
#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
|
||||
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
|
||||
#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define COMP_IRQn COMP1_2_IRQn
|
||||
#define COMP2_IRQn COMP1_2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP1_2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
|
||||
#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define COMP_IRQHandler COMP1_2_IRQHandler
|
||||
#define COMP2_IRQHandler COMP1_2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP1_2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP1_2_IRQHandler
|
||||
#define COMP2_IRQHandler COMP1_2_IRQHandler
|
||||
#define COMP_IRQHandler COMP1_2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
#define CEC_IRQHandler USBWakeUp_IRQHandler
|
||||
#define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler
|
||||
#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
|
||||
#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -2,9 +2,9 @@
|
|||
******************************************************************************
|
||||
* @file stm32f303x8.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CMSIS STM32F303x6/STM32F303x8 Devices Peripheral Access Layer Header File.
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS STM32F303x8 Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -63,11 +63,11 @@
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< STM32F303x6/STM32F303x8 devices do not provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F303x6/STM32F303x8 devices use 4 Bits for the Priority Levels */
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< STM32F303x8 devices do not provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F303x8 devices use 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F303x6/STM32F303x8 devices provide an FPU */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F303x8 devices provide an FPU */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32F303x6/STM32F303x8 device Interrupt Number Definition, according to the selected device
|
||||
* @brief STM32F303x8 devices Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum
|
||||
|
|
@ -112,8 +112,8 @@ typedef enum
|
|||
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
|
||||
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
|
||||
ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
|
||||
CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
|
||||
CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
|
||||
CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
|
||||
CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
|
||||
CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
|
||||
CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
|
||||
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
|
||||
|
|
@ -130,12 +130,12 @@ typedef enum
|
|||
USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
|
||||
USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
|
||||
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
|
||||
TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
|
||||
TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
|
||||
TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
|
||||
COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */
|
||||
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */
|
||||
FPU_IRQn = 81 /*!< Floating point Interrupt */
|
||||
COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
|
||||
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
|
||||
FPU_IRQn = 81, /*!< Floating point Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
|
|
@ -338,8 +338,8 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
|
||||
} DMA_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -348,20 +348,20 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
}EXTI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -409,8 +409,7 @@ typedef struct
|
|||
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
||||
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
||||
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
||||
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
|
||||
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
|
||||
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
|
||||
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
||||
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
|
|
@ -431,10 +430,10 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
__IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
|
||||
__IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
|
||||
|
|
@ -544,17 +543,6 @@ typedef struct
|
|||
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
|
||||
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
|
||||
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
|
||||
__IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
|
||||
__IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
|
||||
__IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
|
||||
__IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
|
||||
__IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
|
||||
__IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
|
||||
__IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
|
||||
__IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
|
||||
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
|
||||
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
|
||||
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
|
||||
} RTC_TypeDef;
|
||||
|
||||
|
||||
|
|
@ -660,14 +648,12 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 64KB) base address in the alias region */
|
||||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 12KB) base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
|
||||
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the bit-band region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 12KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
||||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
|
||||
/*!< Peripheral memory map */
|
||||
|
|
@ -700,11 +686,8 @@ typedef struct
|
|||
#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
|
||||
#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
|
||||
#define COMP_BASE COMP2_BASE
|
||||
#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
|
||||
#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
|
||||
#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
|
||||
#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
|
||||
#define OPAMP_BASE OPAMP1_BASE
|
||||
#define OPAMP_BASE OPAMP2_BASE
|
||||
#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
|
||||
#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
|
||||
#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
|
||||
|
|
@ -740,7 +723,7 @@ typedef struct
|
|||
#define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
|
||||
#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
|
||||
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -760,16 +743,16 @@ typedef struct
|
|||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
||||
#define CAN ((CAN_TypeDef *) CAN_BASE)
|
||||
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
||||
#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
|
||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
|
||||
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
|
||||
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
||||
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
||||
|
|
@ -799,6 +782,7 @@ typedef struct
|
|||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||||
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
|
||||
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -820,6 +804,7 @@ typedef struct
|
|||
/* Analog to Digital Converter SAR (ADC) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************** Bit definition for ADC_ISR register ********************/
|
||||
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
|
||||
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
|
||||
|
|
@ -1598,6 +1583,7 @@ typedef struct
|
|||
/* Analog Comparators (COMP) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/********************** Bit definition for COMP2_CSR register ***************/
|
||||
#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
|
||||
#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
|
||||
|
|
@ -3008,7 +2994,7 @@ typedef struct
|
|||
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
||||
|
||||
/******************* Bit definition for CRC_IDR register ********************/
|
||||
#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
|
||||
/******************** Bit definition for CRC_CR register ********************/
|
||||
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
|
||||
|
|
@ -3034,6 +3020,7 @@ typedef struct
|
|||
/******************** Bit definition for DAC_CR register ********************/
|
||||
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
|
||||
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
|
||||
#define DAC_CR_OUTEN1 ((uint32_t)0x00000002) /*!< DAC channel1 output switch enable */
|
||||
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
|
||||
|
||||
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
|
||||
|
|
@ -3054,7 +3041,7 @@ typedef struct
|
|||
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
|
||||
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
|
||||
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
|
||||
#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
|
||||
#define DAC_CR_OUTEN2 ((uint32_t)0x00020000) /*!< DAC channel2 output switch enable */
|
||||
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
|
||||
|
||||
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
|
||||
|
|
@ -3258,7 +3245,7 @@ typedef struct
|
|||
/* External Interrupt/Event Controller (EXTI) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
|
||||
/******************* Bit definition for EXTI_IMR register *******************/
|
||||
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
||||
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
||||
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
||||
|
|
@ -3288,8 +3275,11 @@ typedef struct
|
|||
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
|
||||
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
|
||||
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
|
||||
#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
|
||||
#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
|
||||
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
|
||||
/******************* Bit definition for EXTI_EMR register *******************/
|
||||
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
||||
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
||||
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
||||
|
|
@ -3319,8 +3309,11 @@ typedef struct
|
|||
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
|
||||
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
|
||||
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
|
||||
#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
|
||||
#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
|
||||
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_RTSR register *******************/
|
||||
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
||||
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
||||
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
||||
|
|
@ -3344,14 +3337,11 @@ typedef struct
|
|||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
|
||||
#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
|
||||
#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
|
||||
#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
|
||||
#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
|
||||
#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
|
||||
#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
|
||||
#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
|
||||
#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
||||
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
||||
|
|
@ -3375,14 +3365,11 @@ typedef struct
|
|||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
|
||||
#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
|
||||
#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
|
||||
#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
|
||||
#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
|
||||
#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
|
||||
#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
|
||||
#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
|
||||
#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
||||
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
||||
|
|
@ -3406,14 +3393,11 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
|
||||
#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
|
||||
#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
|
||||
#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
|
||||
#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
|
||||
#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
|
||||
#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
|
||||
#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
|
||||
#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
||||
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
||||
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
||||
|
|
@ -3437,12 +3421,37 @@ typedef struct
|
|||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
|
||||
#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
|
||||
#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
|
||||
#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
|
||||
#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
|
||||
#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
|
||||
#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
|
||||
#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
|
||||
#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
|
||||
#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_IMR2 register ******************/
|
||||
#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
|
||||
#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
|
||||
#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
|
||||
#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
|
||||
#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
|
||||
#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
|
||||
#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3507,6 +3516,11 @@ typedef struct
|
|||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
|
||||
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
|
||||
#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
|
||||
#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
|
||||
|
||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
||||
|
|
@ -3536,6 +3550,7 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* General Purpose I/O (GPIO) */
|
||||
|
|
@ -3850,7 +3865,7 @@ typedef struct
|
|||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||||
|
|
@ -3864,6 +3879,9 @@ typedef struct
|
|||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||||
|
||||
/* Legacy defines */
|
||||
#define I2C_CR1_DFN I2C_CR1_DNF
|
||||
|
||||
/****************** Bit definition for I2C_CR2 register ********************/
|
||||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||||
|
|
@ -3883,9 +3901,17 @@ typedef struct
|
|||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||||
|
||||
/******************* Bit definition for I2C_OAR2 register *******************/
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
|
||||
#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
||||
#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
||||
#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
||||
#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
||||
#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
||||
#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
||||
#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
|
||||
/******************* Bit definition for I2C_TIMINGR register *****************/
|
||||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||||
|
|
@ -4152,7 +4178,7 @@ typedef struct
|
|||
#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
|
||||
#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
|
||||
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
|
||||
|
||||
/********************* Bit definition for RCC_CIR register ********************/
|
||||
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
|
||||
|
|
@ -4206,7 +4232,7 @@ typedef struct
|
|||
#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
|
||||
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
|
||||
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
|
||||
|
||||
/***************** Bit definition for RCC_APB2ENR register ******************/
|
||||
|
|
@ -4328,20 +4354,20 @@ typedef struct
|
|||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||||
/* Legacy defines */
|
||||
#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
|
||||
|
||||
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000010) /*!< I2CSW bits */
|
||||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||||
|
||||
#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
|
||||
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000100) /*!< TIMSW bits */
|
||||
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
|
||||
|
||||
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
|
||||
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
|
||||
|
||||
|
|
@ -4349,7 +4375,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
|
||||
|
|
@ -4358,7 +4384,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
|
||||
|
|
@ -4694,41 +4720,8 @@ typedef struct
|
|||
/******************** Bits definition for RTC_BKP4R register ****************/
|
||||
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP5R register ****************/
|
||||
#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP6R register ****************/
|
||||
#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP7R register ****************/
|
||||
#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP8R register ****************/
|
||||
#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP9R register ****************/
|
||||
#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP10R register ***************/
|
||||
#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP11R register ***************/
|
||||
#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP12R register ***************/
|
||||
#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP13R register ***************/
|
||||
#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP14R register ***************/
|
||||
#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP15R register ***************/
|
||||
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Number of backup registers ******************************/
|
||||
#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_NUMBER 5
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -4806,7 +4799,7 @@ typedef struct
|
|||
/* System Configuration(SYSCFG) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register *****************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
|
||||
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
|
@ -4815,8 +4808,8 @@ typedef struct
|
|||
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x0000F800) /*!< DMA remap mask */
|
||||
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
|
||||
#define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
||||
|
|
@ -5016,10 +5009,10 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register *****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
|
||||
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
|
||||
|
||||
|
|
@ -5304,7 +5297,7 @@ typedef struct
|
|||
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
|
||||
|
||||
/******************* Bit definition for TIM_RCR register ********************/
|
||||
#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
|
||||
#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
|
||||
|
|
@ -5827,11 +5820,10 @@ typedef struct
|
|||
/****************************** ADC Instances *********************************/
|
||||
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
|
||||
((INSTANCE) == ADC2))
|
||||
|
||||
|
||||
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
|
||||
|
||||
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON))
|
||||
|
||||
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_2_COMMON)
|
||||
/****************************** CAN Instances *********************************/
|
||||
#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
|
||||
|
||||
|
|
@ -5871,29 +5863,42 @@ typedef struct
|
|||
((INSTANCE) == DMA1_Channel7))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
/****************************** I2C Instances *********************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** OPAMP Instances *******************************/
|
||||
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** RTC Instances *********************************/
|
||||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||||
|
||||
/****************************** SMBUS Instances *******************************/
|
||||
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
|
||||
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
|
||||
|
||||
/****************************** SPI Instances *********************************/
|
||||
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1))
|
||||
#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
|
||||
|
||||
/******************* TIM Instances : All supported instances ******************/
|
||||
#define IS_TIM_INSTANCE(INSTANCE)\
|
||||
|
|
@ -5941,7 +5946,7 @@ typedef struct
|
|||
/****************** TIM Instances : at least 6 capture/compare channels *******/
|
||||
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
|
||||
|
||||
/************************** TIM Instances : Advanced-control timers ***********/
|
||||
|
||||
/****************** TIM Instances : supporting clock selection ****************/
|
||||
|
|
@ -6033,9 +6038,9 @@ typedef struct
|
|||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting the break function *************/
|
||||
|
|
@ -6182,7 +6187,7 @@ typedef struct
|
|||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
||||
/******************** UART Instances : Wake-up from Stop mode **********************/
|
||||
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
|
@ -6205,6 +6210,8 @@ typedef struct
|
|||
/*********************** UART Instances : IRDA mode ***************************/
|
||||
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
/******************** UART Instances : Support of continuous communication using DMA ****/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
|
||||
/****************************** WWDG Instances ********************************/
|
||||
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
||||
|
||||
|
|
@ -6222,31 +6229,36 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
|
||||
#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM18_DAC2_IRQn TIM1_CC_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
|
||||
#define TIM7_IRQn TIM7_DAC2_IRQn
|
||||
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
|
||||
#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
|
||||
#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
|
||||
#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
|
||||
#define TIM7_IRQHandler TIM7_DAC2_IRQHandler
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@
|
|||
******************************************************************************
|
||||
* @file stm32f303xc.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CMSIS STM32F303xB/STM32F303xC Devices Peripheral Access Layer Header File.
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS STM32F303xC Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -63,11 +63,11 @@
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< STM32F303xB/STM32F303xC devices provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F303xB/STM32F303xC devices use 4 Bits for the Priority Levels */
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< STM32F303xC devices provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F303xC devices use 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F303xB/STM32F303xC devices provide an FPU */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F303xC devices provide an FPU */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32F303xB/STM32F303xC devices Interrupt Number Definition, according to the selected device
|
||||
* @brief STM32F303xC devices Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum
|
||||
|
|
@ -144,7 +144,7 @@ typedef enum
|
|||
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
|
||||
UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
|
||||
UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
|
||||
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */
|
||||
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
|
||||
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
|
||||
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
|
||||
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
|
||||
|
|
@ -155,10 +155,10 @@ typedef enum
|
|||
COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
|
||||
COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
|
||||
COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
|
||||
USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
|
||||
USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
|
||||
USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
|
||||
USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
|
||||
USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
|
||||
FPU_IRQn = 81 /*!< Floating point Interrupt */
|
||||
FPU_IRQn = 81, /*!< Floating point Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
|
|
@ -361,8 +361,8 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
|
||||
} DMA_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -371,20 +371,20 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
}EXTI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -432,8 +432,7 @@ typedef struct
|
|||
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
||||
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
||||
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
||||
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
|
||||
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
|
||||
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
|
||||
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
||||
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
|
|
@ -454,10 +453,10 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
} SYSCFG_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -573,13 +572,13 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
||||
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
||||
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
|
||||
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
||||
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
||||
} SPI_TypeDef;
|
||||
|
|
@ -688,7 +687,7 @@ typedef struct
|
|||
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
|
||||
__IO uint16_t RESERVEDB; /*!< Reserved */
|
||||
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
|
||||
__IO uint16_t RESERVEDC; /*!< Reserved */
|
||||
__IO uint16_t RESERVEDC; /*!< Reserved */
|
||||
} USB_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -705,14 +704,12 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 256KB) base address in the alias region */
|
||||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 40KB) base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
|
||||
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the bit-band region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 40KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
||||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
|
||||
/*!< Peripheral memory map */
|
||||
|
|
@ -809,7 +806,7 @@ typedef struct
|
|||
#define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
|
||||
#define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
|
||||
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -837,9 +834,9 @@ typedef struct
|
|||
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
|
||||
#define CAN ((CAN_TypeDef *) CAN_BASE)
|
||||
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
|
||||
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
|
||||
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
|
||||
|
|
@ -847,12 +844,12 @@ typedef struct
|
|||
#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
|
||||
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
|
||||
#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
|
||||
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
|
||||
#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
|
||||
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
||||
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
||||
|
|
@ -894,6 +891,7 @@ typedef struct
|
|||
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
|
||||
#define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
|
||||
#define USB ((USB_TypeDef *) USB_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -915,6 +913,7 @@ typedef struct
|
|||
/* Analog to Digital Converter SAR (ADC) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************** Bit definition for ADC_ISR register ********************/
|
||||
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
|
||||
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
|
||||
|
|
@ -1781,6 +1780,7 @@ typedef struct
|
|||
/* Analog Comparators (COMP) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/********************** Bit definition for COMP1_CSR register ***************/
|
||||
#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
|
||||
#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
|
||||
|
|
@ -1996,7 +1996,6 @@ typedef struct
|
|||
#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
|
||||
#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
|
||||
#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
|
||||
#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
|
||||
#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
|
||||
#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
|
||||
|
||||
|
|
@ -3420,7 +3419,7 @@ typedef struct
|
|||
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
||||
|
||||
/******************* Bit definition for CRC_IDR register ********************/
|
||||
#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
|
||||
/******************** Bit definition for CRC_CR register ********************/
|
||||
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
|
||||
|
|
@ -3673,7 +3672,7 @@ typedef struct
|
|||
/* External Interrupt/Event Controller (EXTI) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
|
||||
/******************* Bit definition for EXTI_IMR register *******************/
|
||||
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
||||
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
||||
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
||||
|
|
@ -3703,8 +3702,11 @@ typedef struct
|
|||
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
|
||||
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
|
||||
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
|
||||
#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
|
||||
#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
|
||||
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
|
||||
/******************* Bit definition for EXTI_EMR register *******************/
|
||||
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
||||
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
||||
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
||||
|
|
@ -3734,8 +3736,11 @@ typedef struct
|
|||
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
|
||||
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
|
||||
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
|
||||
#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
|
||||
#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
|
||||
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_RTSR register *******************/
|
||||
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
||||
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
||||
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
||||
|
|
@ -3759,14 +3764,11 @@ typedef struct
|
|||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
|
||||
#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
|
||||
#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
|
||||
#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
|
||||
#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
|
||||
#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
|
||||
#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
|
||||
#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
|
||||
#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
||||
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
||||
|
|
@ -3790,14 +3792,11 @@ typedef struct
|
|||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
|
||||
#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
|
||||
#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
|
||||
#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
|
||||
#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
|
||||
#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
|
||||
#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
|
||||
#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
|
||||
#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
||||
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
||||
|
|
@ -3821,14 +3820,11 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
|
||||
#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
|
||||
#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
|
||||
#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
|
||||
#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
|
||||
#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
|
||||
#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
|
||||
#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
|
||||
#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
||||
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
||||
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
||||
|
|
@ -3852,12 +3848,37 @@ typedef struct
|
|||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
|
||||
#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
|
||||
#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
|
||||
#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
|
||||
#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
|
||||
#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
|
||||
#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
|
||||
#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
|
||||
#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
|
||||
#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_IMR2 register ******************/
|
||||
#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
|
||||
#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
|
||||
#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
|
||||
#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
|
||||
#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
|
||||
#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
|
||||
#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3922,6 +3943,11 @@ typedef struct
|
|||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
|
||||
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
|
||||
#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
|
||||
#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
|
||||
|
||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
||||
|
|
@ -3951,6 +3977,7 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* General Purpose I/O (GPIO) */
|
||||
|
|
@ -4265,7 +4292,7 @@ typedef struct
|
|||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||||
|
|
@ -4279,6 +4306,9 @@ typedef struct
|
|||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||||
|
||||
/* Legacy defines */
|
||||
#define I2C_CR1_DFN I2C_CR1_DNF
|
||||
|
||||
/****************** Bit definition for I2C_CR2 register ********************/
|
||||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||||
|
|
@ -4298,9 +4328,17 @@ typedef struct
|
|||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||||
|
||||
/******************* Bit definition for I2C_OAR2 register *******************/
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
|
||||
#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
||||
#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
||||
#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
||||
#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
||||
#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
||||
#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
||||
#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
|
||||
/******************* Bit definition for I2C_TIMINGR register *****************/
|
||||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||||
|
|
@ -4571,7 +4609,7 @@ typedef struct
|
|||
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
|
||||
|
||||
#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
|
||||
|
||||
/********************* Bit definition for RCC_CIR register ********************/
|
||||
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
|
||||
|
|
@ -4634,7 +4672,7 @@ typedef struct
|
|||
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
|
||||
#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
|
||||
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
|
||||
#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
|
||||
|
||||
|
|
@ -4694,6 +4732,7 @@ typedef struct
|
|||
/******************** Bit definition for RCC_CSR register *******************/
|
||||
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
|
||||
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
|
||||
#define RCC_CSR_VREGRSTF ((uint32_t)0x00800000) /*!< Voltage regulator reset flag */
|
||||
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
|
||||
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
|
||||
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
|
||||
|
|
@ -4788,10 +4827,12 @@ typedef struct
|
|||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||||
/* Legacy defines */
|
||||
#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
|
||||
|
||||
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
|
||||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||||
|
|
@ -4801,14 +4842,11 @@ typedef struct
|
|||
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
|
||||
#define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
|
||||
#define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000300) /*!< TIMSW bits */
|
||||
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
|
||||
#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
|
||||
|
||||
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
|
||||
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
|
||||
#define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
|
||||
|
||||
|
|
@ -4816,7 +4854,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
|
||||
|
|
@ -4825,7 +4863,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
|
||||
|
|
@ -4834,7 +4872,7 @@ typedef struct
|
|||
#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
|
||||
|
|
@ -4843,7 +4881,7 @@ typedef struct
|
|||
#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
|
||||
|
|
@ -5213,7 +5251,7 @@ typedef struct
|
|||
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Number of backup registers ******************************/
|
||||
#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_NUMBER 16
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -5312,7 +5350,7 @@ typedef struct
|
|||
/* System Configuration(SYSCFG) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register *****************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
|
||||
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
|
@ -5323,8 +5361,8 @@ typedef struct
|
|||
#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
|
||||
|
|
@ -5528,10 +5566,10 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register *****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/8/15/16/17 */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
|
||||
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
|
||||
|
||||
|
|
@ -5798,7 +5836,7 @@ typedef struct
|
|||
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
|
||||
|
||||
/******************* Bit definition for TIM_RCR register ********************/
|
||||
#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
|
||||
#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
|
||||
|
|
@ -6289,7 +6327,7 @@ typedef struct
|
|||
|
||||
/**************************** ISTR interrupt events *************************/
|
||||
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
|
||||
#define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
|
||||
#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
|
||||
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
|
||||
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
|
||||
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
|
||||
|
|
@ -6299,8 +6337,11 @@ typedef struct
|
|||
#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
|
||||
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
|
||||
|
||||
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
|
||||
#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
|
||||
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
|
||||
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
|
||||
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
|
||||
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
|
||||
|
|
@ -6308,9 +6349,12 @@ typedef struct
|
|||
#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
|
||||
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
|
||||
|
||||
/************************* CNTR control register bits definitions ***********/
|
||||
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
|
||||
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
|
||||
#define USB_CNTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
|
||||
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
|
||||
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
|
||||
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
|
||||
|
|
@ -6319,10 +6363,14 @@ typedef struct
|
|||
#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
|
||||
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
|
||||
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
|
||||
#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
|
||||
#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
|
||||
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
|
||||
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
|
||||
#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
|
||||
|
||||
/******************** FNR Frame Number Register bit definitions ************/
|
||||
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
|
||||
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
|
||||
|
|
@ -6470,9 +6518,9 @@ typedef struct
|
|||
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
|
||||
|
||||
#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
|
||||
(((INSTANCE) == DAC1) && \
|
||||
((((INSTANCE) == DAC1) && \
|
||||
(((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2)))
|
||||
((CHANNEL) == DAC_CHANNEL_2))))
|
||||
|
||||
/****************************** DMA Instances *********************************/
|
||||
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
|
||||
|
|
@ -6489,12 +6537,23 @@ typedef struct
|
|||
((INSTANCE) == DMA2_Channel5))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOD))
|
||||
|
||||
/****************************** I2C Instances *********************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
||||
|
|
@ -6504,15 +6563,15 @@ typedef struct
|
|||
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
|
||||
((INSTANCE) == SPI3))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** OPAMP Instances *******************************/
|
||||
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
|
||||
((INSTANCE) == OPAMP2) || \
|
||||
((INSTANCE) == OPAMP3) || \
|
||||
((INSTANCE) == OPAMP4))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** RTC Instances *********************************/
|
||||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||||
|
||||
|
|
@ -6583,7 +6642,7 @@ typedef struct
|
|||
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
|
||||
/************************** TIM Instances : Advanced-control timers ***********/
|
||||
|
||||
/****************** TIM Instances : supporting clock selection ****************/
|
||||
|
|
@ -6698,11 +6757,11 @@ typedef struct
|
|||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting the break function *************/
|
||||
|
|
@ -6765,10 +6824,10 @@ typedef struct
|
|||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3))) \
|
||||
|| \
|
||||
|| \
|
||||
(((INSTANCE) == TIM8) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM15) && \
|
||||
|
|
@ -6886,7 +6945,7 @@ typedef struct
|
|||
((INSTANCE) == USART3) || \
|
||||
((INSTANCE) == UART4) || \
|
||||
((INSTANCE) == UART5))
|
||||
|
||||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
|
|
@ -6928,6 +6987,9 @@ typedef struct
|
|||
((INSTANCE) == UART4) || \
|
||||
((INSTANCE) == UART5))
|
||||
|
||||
/******************** UART Instances : Support of continuous communication using DMA ****/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
|
||||
|
||||
/****************************** USB Instances *********************************/
|
||||
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
|
||||
|
||||
|
|
@ -6948,31 +7010,48 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define SDADC1_IRQn ADC4_IRQn
|
||||
#define COMP1_2_IRQn COMP1_2_3_IRQn
|
||||
#define COMP2_IRQn COMP1_2_3_IRQn
|
||||
#define COMP_IRQn COMP1_2_3_IRQn
|
||||
#define COMP4_6_IRQn COMP4_5_6_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM18_DAC2_IRQn TIM1_CC_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
#define TIM7_DAC2_IRQn TIM7_IRQn
|
||||
#define TIM12_IRQn TIM8_BRK_IRQn
|
||||
#define TIM14_IRQn TIM8_TRG_COM_IRQn
|
||||
#define TIM13_IRQn TIM8_UP_IRQn
|
||||
#define CEC_IRQn USBWakeUp_IRQn
|
||||
#define USBWakeUp_IRQn USBWakeUp_RMP_IRQn
|
||||
#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
|
||||
#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
|
||||
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
|
||||
#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define COMP_IRQn COMP1_2_3_IRQn
|
||||
#define COMP2_IRQn COMP1_2_3_IRQn
|
||||
#define COMP1_2_IRQn COMP1_2_3_IRQn
|
||||
#define COMP4_6_IRQn COMP4_5_6_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
|
||||
#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define COMP_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP2_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define SDADC1_IRQHandler ADC4_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP2_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
|
||||
#define TIM12_IRQHandler TIM8_BRK_IRQHandler
|
||||
#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
|
||||
#define TIM13_IRQHandler TIM8_UP_IRQHandler
|
||||
#define CEC_IRQHandler USBWakeUp_IRQHandler
|
||||
#define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler
|
||||
#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
|
||||
#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f318xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS STM32F318xx Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -63,7 +63,7 @@
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< STM32F318xx devices do not provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F318xx devices use 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32F318xx device Interrupt Number Definition, according to the selected device
|
||||
* @brief STM32F318xx devices Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum
|
||||
|
|
@ -128,12 +128,12 @@ typedef enum
|
|||
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
|
||||
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
|
||||
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel1 underrun error Interrupt */
|
||||
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
|
||||
COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
|
||||
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
|
||||
I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */
|
||||
I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
|
||||
FPU_IRQn = 81 /*!< Floating point Interrupt */
|
||||
FPU_IRQn = 81, /*!< Floating point Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
|
|
@ -234,20 +234,20 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
|
||||
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
|
||||
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
|
||||
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
|
||||
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
|
||||
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
|
||||
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
|
||||
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
|
||||
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
|
||||
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
|
||||
__IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
|
||||
__IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
__IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
|
||||
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
|
||||
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
|
||||
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
|
||||
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
|
||||
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
|
||||
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
|
||||
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
|
||||
__IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
|
||||
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
|
||||
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
|
||||
} DAC_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -276,8 +276,8 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
|
||||
} DMA_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -286,20 +286,20 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
}EXTI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -347,11 +347,10 @@ typedef struct
|
|||
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
||||
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
||||
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
||||
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
|
||||
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
|
||||
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
|
||||
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
||||
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
}GPIO_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -369,10 +368,10 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t RESERVED0; /*!< Reserved, 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
uint32_t RESERVED; /*!< Reserved, 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
} SYSCFG_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -479,6 +478,10 @@ typedef struct
|
|||
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
|
||||
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
|
||||
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
|
||||
__IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
|
||||
__IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
|
||||
__IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
|
||||
__IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
|
||||
} RTC_TypeDef;
|
||||
|
||||
|
||||
|
|
@ -488,13 +491,13 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
||||
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
||||
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
|
||||
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
||||
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
||||
} SPI_TypeDef;
|
||||
|
|
@ -530,7 +533,6 @@ typedef struct
|
|||
__IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
|
||||
} TIM_TypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Touch Sensing Controller (TSC)
|
||||
*/
|
||||
|
|
@ -590,7 +592,6 @@ typedef struct
|
|||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
|
|
@ -662,7 +663,7 @@ typedef struct
|
|||
#define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
|
||||
#define ADC1_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
|
||||
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -687,13 +688,13 @@ typedef struct
|
|||
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
|
||||
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
|
||||
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
|
||||
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE)
|
||||
|
|
@ -721,6 +722,7 @@ typedef struct
|
|||
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
|
||||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||||
#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -742,6 +744,7 @@ typedef struct
|
|||
/* Analog to Digital Converter SAR (ADC) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************** Bit definition for ADC_ISR register ********************/
|
||||
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
|
||||
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
|
||||
|
|
@ -1520,6 +1523,7 @@ typedef struct
|
|||
/* Analog Comparators (COMP) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/********************** Bit definition for COMP2_CSR register ***************/
|
||||
#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
|
||||
#define COMP2_CSR_COMP2INPDAC ((uint32_t)0x00000002) /*!< COMP2 non inverting input to DAC output */
|
||||
|
|
@ -1672,7 +1676,7 @@ typedef struct
|
|||
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
||||
|
||||
/******************* Bit definition for CRC_IDR register ********************/
|
||||
#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
|
||||
/******************** Bit definition for CRC_CR register ********************/
|
||||
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
|
||||
|
|
@ -1717,7 +1721,6 @@ typedef struct
|
|||
|
||||
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
|
||||
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
|
||||
|
||||
/***************** Bit definition for DAC_SWTRIGR register ******************/
|
||||
#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
|
||||
|
||||
|
|
@ -1883,7 +1886,7 @@ typedef struct
|
|||
/* External Interrupt/Event Controller (EXTI) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
|
||||
/******************* Bit definition for EXTI_IMR register *******************/
|
||||
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
||||
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
||||
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
||||
|
|
@ -1913,8 +1916,11 @@ typedef struct
|
|||
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
|
||||
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
|
||||
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
|
||||
#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
|
||||
#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
|
||||
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
|
||||
/******************* Bit definition for EXTI_EMR register *******************/
|
||||
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
||||
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
||||
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
||||
|
|
@ -1944,8 +1950,11 @@ typedef struct
|
|||
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
|
||||
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
|
||||
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
|
||||
#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
|
||||
#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
|
||||
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_RTSR register *******************/
|
||||
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
||||
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
||||
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
||||
|
|
@ -1969,14 +1978,11 @@ typedef struct
|
|||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
|
||||
#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
|
||||
#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
|
||||
#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
|
||||
#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
|
||||
#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
|
||||
#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
|
||||
#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
|
||||
#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
||||
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
||||
|
|
@ -2000,14 +2006,11 @@ typedef struct
|
|||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
|
||||
#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
|
||||
#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
|
||||
#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
|
||||
#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
|
||||
#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
|
||||
#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
|
||||
#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
|
||||
#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
||||
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
||||
|
|
@ -2031,14 +2034,11 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
|
||||
#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
|
||||
#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
|
||||
#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
|
||||
#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
|
||||
#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
|
||||
#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
|
||||
#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
|
||||
#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
||||
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
||||
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
||||
|
|
@ -2062,12 +2062,37 @@ typedef struct
|
|||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
|
||||
#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
|
||||
#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
|
||||
#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
|
||||
#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
|
||||
#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
|
||||
#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
|
||||
#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
|
||||
#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
|
||||
#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_IMR2 register ******************/
|
||||
#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
|
||||
#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
|
||||
#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
|
||||
#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
|
||||
#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
|
||||
#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
|
||||
#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -2132,6 +2157,11 @@ typedef struct
|
|||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
|
||||
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
|
||||
#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
|
||||
#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
|
||||
|
||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
||||
|
|
@ -2161,6 +2191,7 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* General Purpose I/O (GPIO) */
|
||||
|
|
@ -2475,7 +2506,7 @@ typedef struct
|
|||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||||
|
|
@ -2489,6 +2520,9 @@ typedef struct
|
|||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||||
|
||||
/* Legacy defines */
|
||||
#define I2C_CR1_DFN I2C_CR1_DNF
|
||||
|
||||
/****************** Bit definition for I2C_CR2 register ********************/
|
||||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||||
|
|
@ -2508,9 +2542,17 @@ typedef struct
|
|||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||||
|
||||
/******************* Bit definition for I2C_OAR2 register *******************/
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
|
||||
#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
||||
#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
||||
#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
||||
#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
||||
#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
||||
#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
||||
#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
|
||||
/******************* Bit definition for I2C_TIMINGR register *****************/
|
||||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||||
|
|
@ -2815,8 +2857,8 @@ typedef struct
|
|||
#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
|
||||
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
|
||||
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
|
||||
|
||||
/***************** Bit definition for RCC_APB2ENR register ******************/
|
||||
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
|
||||
|
|
@ -2936,10 +2978,12 @@ typedef struct
|
|||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||||
/* Legacy defines */
|
||||
#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
|
||||
|
||||
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
|
||||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||||
|
|
@ -2958,16 +3002,12 @@ typedef struct
|
|||
#define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
|
||||
#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
|
||||
#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
|
||||
|
||||
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
|
||||
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
|
||||
#define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
|
||||
#define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
|
||||
#define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
|
||||
|
||||
|
|
@ -2975,7 +3015,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
|
||||
|
|
@ -2984,7 +3024,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
|
||||
|
|
@ -3353,8 +3393,20 @@ typedef struct
|
|||
/******************** Bits definition for RTC_BKP15R register ***************/
|
||||
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP16R register ***************/
|
||||
#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP17R register ***************/
|
||||
#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP18R register ***************/
|
||||
#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP19R register ***************/
|
||||
#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Number of backup registers ******************************/
|
||||
#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_NUMBER 20
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3453,7 +3505,7 @@ typedef struct
|
|||
/* System Configuration(SYSCFG) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register *****************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
|
||||
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
|
@ -3462,7 +3514,7 @@ typedef struct
|
|||
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00003800) /*!< DMA remap mask */
|
||||
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
|
||||
|
|
@ -3657,9 +3709,8 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register *****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3924,7 +3975,7 @@ typedef struct
|
|||
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
|
||||
|
||||
/******************* Bit definition for TIM_RCR register ********************/
|
||||
#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
|
||||
#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
|
||||
|
|
@ -4480,11 +4531,23 @@ typedef struct
|
|||
((INSTANCE) == DMA1_Channel7))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
/****************************** I2C Instances *********************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
||||
|
|
@ -4495,12 +4558,12 @@ typedef struct
|
|||
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
|
||||
((INSTANCE) == SPI3))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** OPAMP Instances *******************************/
|
||||
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** RTC Instances *********************************/
|
||||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||||
|
||||
|
|
@ -4548,12 +4611,12 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : at least 5 capture/compare channels *******/
|
||||
#define IS_TIM_CC5_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : at least 6 capture/compare channels *******/
|
||||
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/************************** TIM Instances : Advanced-control timers ***********/
|
||||
|
||||
/****************** TIM Instances : supporting clock selection ****************/
|
||||
|
|
@ -4596,7 +4659,7 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : supporting Hall interface *****************/
|
||||
#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : supporting input XOR function *************/
|
||||
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
|
||||
|
|
@ -4632,8 +4695,8 @@ typedef struct
|
|||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting the break function *************/
|
||||
|
|
@ -4707,11 +4770,11 @@ typedef struct
|
|||
|
||||
/****************** TIM Instances : supporting 2 break inputs *****************/
|
||||
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
((INSTANCE) == TIM1)
|
||||
|
||||
/****************** TIM Instances : supporting DMA generation on Update events*/
|
||||
#define IS_TIM_DMA_INSTANCE(INSTANCE)\
|
||||
|
|
@ -4769,7 +4832,7 @@ typedef struct
|
|||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
||||
/******************** UART Instances : Wake-up from Stop mode **********************/
|
||||
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
|
@ -4778,7 +4841,7 @@ typedef struct
|
|||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/****************** UART Instances : Auto Baud Rate detection *****************/
|
||||
/****************** UART Instances : Driver Enable ****************************/
|
||||
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
|
@ -4789,6 +4852,8 @@ typedef struct
|
|||
/*********************** UART Instances : IRDA mode ***************************/
|
||||
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
/******************** UART Instances : Support of continuous communication using DMA ****/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
|
||||
/****************************** WWDG Instances ********************************/
|
||||
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
||||
|
||||
|
|
@ -4806,27 +4871,34 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define HRTIM1_FLT_IRQn I2C3_ER_IRQn
|
||||
#define HRTIM1_TIME_IRQn I2C3_EV_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM18_DAC2_IRQn TIM1_CC_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
|
||||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
|
||||
#define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f328xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS STM32F328xx Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -63,7 +63,7 @@
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< STM32F328xx devices do not provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F328xx devices use 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32F328xx device Interrupt Number Definition, according to the selected device
|
||||
* @brief STM32F328xx devices Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum
|
||||
|
|
@ -111,8 +111,8 @@ typedef enum
|
|||
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
|
||||
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
|
||||
ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
|
||||
CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
|
||||
CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
|
||||
CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
|
||||
CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
|
||||
CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
|
||||
CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
|
||||
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
|
||||
|
|
@ -129,12 +129,12 @@ typedef enum
|
|||
USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
|
||||
USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
|
||||
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
|
||||
TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
|
||||
TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
|
||||
TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
|
||||
COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */
|
||||
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */
|
||||
FPU_IRQn = 81 /*!< Floating point Interrupt */
|
||||
COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
|
||||
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
|
||||
FPU_IRQn = 81, /*!< Floating point Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
|
|
@ -337,8 +337,8 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
|
||||
} DMA_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -347,20 +347,20 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
}EXTI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -408,8 +408,7 @@ typedef struct
|
|||
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
||||
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
||||
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
||||
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
|
||||
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
|
||||
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
|
||||
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
||||
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
|
|
@ -430,10 +429,10 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
__IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
|
||||
__IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
|
||||
|
|
@ -543,17 +542,6 @@ typedef struct
|
|||
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
|
||||
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
|
||||
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
|
||||
__IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
|
||||
__IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
|
||||
__IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
|
||||
__IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
|
||||
__IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
|
||||
__IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
|
||||
__IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
|
||||
__IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
|
||||
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
|
||||
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
|
||||
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
|
||||
} RTC_TypeDef;
|
||||
|
||||
|
||||
|
|
@ -603,7 +591,6 @@ typedef struct
|
|||
__IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
|
||||
} TIM_TypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Touch Sensing Controller (TSC)
|
||||
*/
|
||||
|
|
@ -660,14 +647,12 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 64KB) base address in the alias region */
|
||||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 12KB) base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
|
||||
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the bit-band region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 12KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
||||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
|
||||
/*!< Peripheral memory map */
|
||||
|
|
@ -757,16 +742,16 @@ typedef struct
|
|||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
||||
#define CAN ((CAN_TypeDef *) CAN_BASE)
|
||||
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
||||
#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
|
||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
|
||||
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
|
||||
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
||||
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
||||
|
|
@ -796,6 +781,7 @@ typedef struct
|
|||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||||
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
|
||||
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -817,6 +803,7 @@ typedef struct
|
|||
/* Analog to Digital Converter SAR (ADC) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************** Bit definition for ADC_ISR register ********************/
|
||||
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
|
||||
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
|
||||
|
|
@ -1595,6 +1582,7 @@ typedef struct
|
|||
/* Analog Comparators (COMP) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/********************** Bit definition for COMP2_CSR register ***************/
|
||||
#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
|
||||
#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
|
||||
|
|
@ -3005,7 +2993,7 @@ typedef struct
|
|||
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
||||
|
||||
/******************* Bit definition for CRC_IDR register ********************/
|
||||
#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
|
||||
/******************** Bit definition for CRC_CR register ********************/
|
||||
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
|
||||
|
|
@ -3030,7 +3018,7 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
/******************** Bit definition for DAC_CR register ********************/
|
||||
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
|
||||
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
|
||||
#define DAC_CR_OUTEN1 ((uint32_t)0x00000002) /*!< DAC channel1 output switch enable */
|
||||
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
|
||||
|
||||
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
|
||||
|
|
@ -3051,7 +3039,7 @@ typedef struct
|
|||
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
|
||||
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
|
||||
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
|
||||
#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
|
||||
#define DAC_CR_OUTEN2 ((uint32_t)0x00020000) /*!< DAC channel2 output switch enable */
|
||||
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
|
||||
|
||||
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
|
||||
|
|
@ -3255,7 +3243,7 @@ typedef struct
|
|||
/* External Interrupt/Event Controller (EXTI) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
|
||||
/******************* Bit definition for EXTI_IMR register *******************/
|
||||
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
||||
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
||||
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
||||
|
|
@ -3285,8 +3273,11 @@ typedef struct
|
|||
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
|
||||
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
|
||||
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
|
||||
#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
|
||||
#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
|
||||
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
|
||||
/******************* Bit definition for EXTI_EMR register *******************/
|
||||
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
||||
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
||||
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
||||
|
|
@ -3316,8 +3307,11 @@ typedef struct
|
|||
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
|
||||
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
|
||||
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
|
||||
#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
|
||||
#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
|
||||
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_RTSR register *******************/
|
||||
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
||||
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
||||
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
||||
|
|
@ -3341,14 +3335,11 @@ typedef struct
|
|||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
|
||||
#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
|
||||
#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
|
||||
#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
|
||||
#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
|
||||
#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
|
||||
#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
|
||||
#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
|
||||
#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
||||
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
||||
|
|
@ -3372,14 +3363,11 @@ typedef struct
|
|||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
|
||||
#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
|
||||
#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
|
||||
#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
|
||||
#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
|
||||
#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
|
||||
#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
|
||||
#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
|
||||
#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
||||
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
||||
|
|
@ -3403,14 +3391,11 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
|
||||
#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
|
||||
#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
|
||||
#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
|
||||
#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
|
||||
#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
|
||||
#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
|
||||
#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
|
||||
#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
||||
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
||||
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
||||
|
|
@ -3434,12 +3419,37 @@ typedef struct
|
|||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
|
||||
#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
|
||||
#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
|
||||
#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
|
||||
#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
|
||||
#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
|
||||
#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
|
||||
#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
|
||||
#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
|
||||
#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_IMR2 register ******************/
|
||||
#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
|
||||
#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
|
||||
#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
|
||||
#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
|
||||
#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
|
||||
#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
|
||||
#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3504,6 +3514,11 @@ typedef struct
|
|||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
|
||||
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
|
||||
#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
|
||||
#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
|
||||
|
||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
||||
|
|
@ -3533,6 +3548,7 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* General Purpose I/O (GPIO) */
|
||||
|
|
@ -3847,7 +3863,7 @@ typedef struct
|
|||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||||
|
|
@ -3861,6 +3877,9 @@ typedef struct
|
|||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||||
|
||||
/* Legacy defines */
|
||||
#define I2C_CR1_DFN I2C_CR1_DNF
|
||||
|
||||
/****************** Bit definition for I2C_CR2 register ********************/
|
||||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||||
|
|
@ -3880,9 +3899,17 @@ typedef struct
|
|||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||||
|
||||
/******************* Bit definition for I2C_OAR2 register *******************/
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
|
||||
#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
||||
#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
||||
#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
||||
#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
||||
#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
||||
#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
||||
#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
|
||||
/******************* Bit definition for I2C_TIMINGR register *****************/
|
||||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||||
|
|
@ -4132,7 +4159,7 @@ typedef struct
|
|||
#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
|
||||
#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
|
||||
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
|
||||
|
||||
/********************* Bit definition for RCC_CIR register ********************/
|
||||
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
|
||||
|
|
@ -4186,7 +4213,7 @@ typedef struct
|
|||
#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
|
||||
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
|
||||
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
|
||||
|
||||
/***************** Bit definition for RCC_APB2ENR register ******************/
|
||||
|
|
@ -4207,7 +4234,6 @@ typedef struct
|
|||
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
|
||||
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
|
||||
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
|
||||
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
|
||||
#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
|
||||
#define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /*!< DAC 2 clock enable */
|
||||
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
|
||||
|
|
@ -4309,20 +4335,20 @@ typedef struct
|
|||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||||
/* Legacy defines */
|
||||
#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
|
||||
|
||||
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000010) /*!< I2CSW bits */
|
||||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||||
|
||||
#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
|
||||
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000100) /*!< TIMSW bits */
|
||||
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
|
||||
|
||||
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
|
||||
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
|
||||
|
||||
|
|
@ -4330,7 +4356,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
|
||||
|
|
@ -4339,7 +4365,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
|
||||
|
|
@ -4675,41 +4701,8 @@ typedef struct
|
|||
/******************** Bits definition for RTC_BKP4R register ****************/
|
||||
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP5R register ****************/
|
||||
#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP6R register ****************/
|
||||
#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP7R register ****************/
|
||||
#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP8R register ****************/
|
||||
#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP9R register ****************/
|
||||
#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP10R register ***************/
|
||||
#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP11R register ***************/
|
||||
#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP12R register ***************/
|
||||
#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP13R register ***************/
|
||||
#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP14R register ***************/
|
||||
#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP15R register ***************/
|
||||
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Number of backup registers ******************************/
|
||||
#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_NUMBER 5
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -4787,7 +4780,7 @@ typedef struct
|
|||
/* System Configuration(SYSCFG) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register *****************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
|
||||
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
|
@ -4796,8 +4789,8 @@ typedef struct
|
|||
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x0000F800) /*!< DMA remap mask */
|
||||
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
|
||||
#define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
||||
|
|
@ -4997,9 +4990,9 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register *****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
|
||||
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
|
||||
|
||||
|
|
@ -5287,7 +5280,7 @@ typedef struct
|
|||
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
|
||||
|
||||
/******************* Bit definition for TIM_RCR register ********************/
|
||||
#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
|
||||
#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
|
||||
|
|
@ -5810,11 +5803,10 @@ typedef struct
|
|||
/****************************** ADC Instances *********************************/
|
||||
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
|
||||
((INSTANCE) == ADC2))
|
||||
|
||||
|
||||
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
|
||||
|
||||
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON))
|
||||
|
||||
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_2_COMMON)
|
||||
/****************************** CAN Instances *********************************/
|
||||
#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
|
||||
|
||||
|
|
@ -5854,29 +5846,42 @@ typedef struct
|
|||
((INSTANCE) == DMA1_Channel7))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
/****************************** I2C Instances *********************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** OPAMP Instances *******************************/
|
||||
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** RTC Instances *********************************/
|
||||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||||
|
||||
/****************************** SMBUS Instances *******************************/
|
||||
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
|
||||
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
|
||||
|
||||
/****************************** SPI Instances *********************************/
|
||||
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1))
|
||||
#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
|
||||
|
||||
/******************* TIM Instances : All supported instances ******************/
|
||||
#define IS_TIM_INSTANCE(INSTANCE)\
|
||||
|
|
@ -5924,7 +5929,7 @@ typedef struct
|
|||
/****************** TIM Instances : at least 6 capture/compare channels *******/
|
||||
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
|
||||
|
||||
/************************** TIM Instances : Advanced-control timers ***********/
|
||||
|
||||
/****************** TIM Instances : supporting clock selection ****************/
|
||||
|
|
@ -6016,9 +6021,9 @@ typedef struct
|
|||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting the break function *************/
|
||||
|
|
@ -6165,7 +6170,7 @@ typedef struct
|
|||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
||||
/******************** UART Instances : Wake-up from Stop mode **********************/
|
||||
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
|
@ -6188,6 +6193,8 @@ typedef struct
|
|||
/*********************** UART Instances : IRDA mode ***************************/
|
||||
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
/******************** UART Instances : Support of continuous communication using DMA ****/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
|
||||
/****************************** WWDG Instances ********************************/
|
||||
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
||||
|
||||
|
|
@ -6205,31 +6212,36 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
|
||||
#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM18_DAC2_IRQn TIM1_CC_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
|
||||
#define TIM7_IRQn TIM7_DAC2_IRQn
|
||||
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
|
||||
#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
|
||||
#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
|
||||
#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
|
||||
#define TIM7_IRQHandler TIM7_DAC2_IRQHandler
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@
|
|||
******************************************************************************
|
||||
* @file stm32f334x8.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CMSIS STM32F334x4/STM32F334x6/STM32F334x8 Devices Peripheral Access Layer Header File.
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -63,11 +63,11 @@
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices do not provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices use 4 Bits for the Priority Levels */
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< STM32F334x8 devices do not provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F334x8 devices use 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices provide an FPU */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F334x8 devices provide an FPU */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32F334x4/STM32F334x6/STM32F334x8 device Interrupt Number Definition, according to the selected device
|
||||
* @brief STM32F334x8 devices Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum
|
||||
|
|
@ -112,8 +112,8 @@ typedef enum
|
|||
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
|
||||
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
|
||||
ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
|
||||
CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
|
||||
CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
|
||||
CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
|
||||
CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
|
||||
CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
|
||||
CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
|
||||
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
|
||||
|
|
@ -130,11 +130,11 @@ typedef enum
|
|||
USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
|
||||
USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
|
||||
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
|
||||
TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
|
||||
TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
|
||||
TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
|
||||
COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */
|
||||
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */
|
||||
COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
|
||||
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
|
||||
HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */
|
||||
HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */
|
||||
HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */
|
||||
|
|
@ -142,7 +142,7 @@ typedef enum
|
|||
HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */
|
||||
HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */
|
||||
HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */
|
||||
FPU_IRQn = 81 /*!< Floating point Interrupt */
|
||||
FPU_IRQn = 81, /*!< Floating point Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
|
|
@ -345,8 +345,8 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
|
||||
} DMA_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -355,20 +355,20 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
}EXTI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -416,8 +416,7 @@ typedef struct
|
|||
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
||||
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
||||
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
||||
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
|
||||
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
|
||||
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
|
||||
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
||||
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
|
|
@ -432,7 +431,7 @@ typedef struct
|
|||
__IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
|
||||
} OPAMP_TypeDef;
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief High resolution Timer (HRTIM)
|
||||
*/
|
||||
/* HRTIM master registers definition */
|
||||
|
|
@ -534,10 +533,10 @@ typedef struct {
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
__IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
|
||||
__IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
|
||||
|
|
@ -647,17 +646,6 @@ typedef struct
|
|||
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
|
||||
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
|
||||
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
|
||||
__IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
|
||||
__IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
|
||||
__IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
|
||||
__IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
|
||||
__IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
|
||||
__IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
|
||||
__IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
|
||||
__IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
|
||||
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
|
||||
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
|
||||
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
|
||||
} RTC_TypeDef;
|
||||
|
||||
|
||||
|
|
@ -763,14 +751,12 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 64KB) base address in the alias region */
|
||||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 12KB) base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
|
||||
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the bit-band region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 12KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
||||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
|
||||
/*!< Peripheral memory map */
|
||||
|
|
@ -847,7 +833,7 @@ typedef struct
|
|||
#define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
|
||||
#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
|
||||
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -874,16 +860,16 @@ typedef struct
|
|||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
||||
#define CAN ((CAN_TypeDef *) CAN_BASE)
|
||||
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
||||
#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
|
||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
|
||||
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
|
||||
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
||||
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
||||
|
|
@ -913,6 +899,7 @@ typedef struct
|
|||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||||
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
|
||||
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -934,6 +921,7 @@ typedef struct
|
|||
/* Analog to Digital Converter SAR (ADC) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************** Bit definition for ADC_ISR register ********************/
|
||||
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
|
||||
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
|
||||
|
|
@ -1736,6 +1724,7 @@ typedef struct
|
|||
/* Analog Comparators (COMP) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/********************** Bit definition for COMP2_CSR register ***************/
|
||||
#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
|
||||
#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
|
||||
|
|
@ -3146,7 +3135,7 @@ typedef struct
|
|||
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
||||
|
||||
/******************* Bit definition for CRC_IDR register ********************/
|
||||
#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
|
||||
/******************** Bit definition for CRC_CR register ********************/
|
||||
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
|
||||
|
|
@ -3172,6 +3161,7 @@ typedef struct
|
|||
/******************** Bit definition for DAC_CR register ********************/
|
||||
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
|
||||
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
|
||||
#define DAC_CR_OUTEN1 ((uint32_t)0x00000002) /*!< DAC channel1 output switch enable */
|
||||
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
|
||||
|
||||
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
|
||||
|
|
@ -3192,7 +3182,7 @@ typedef struct
|
|||
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
|
||||
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
|
||||
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
|
||||
#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
|
||||
#define DAC_CR_OUTEN2 ((uint32_t)0x00020000) /*!< DAC channel2 output switch enable */
|
||||
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
|
||||
|
||||
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
|
||||
|
|
@ -3397,7 +3387,7 @@ typedef struct
|
|||
/* External Interrupt/Event Controller (EXTI) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
|
||||
/******************* Bit definition for EXTI_IMR register *******************/
|
||||
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
||||
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
||||
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
||||
|
|
@ -3427,8 +3417,11 @@ typedef struct
|
|||
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
|
||||
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
|
||||
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
|
||||
#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
|
||||
#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
|
||||
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
|
||||
/******************* Bit definition for EXTI_EMR register *******************/
|
||||
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
||||
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
||||
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
||||
|
|
@ -3458,8 +3451,11 @@ typedef struct
|
|||
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
|
||||
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
|
||||
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
|
||||
#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
|
||||
#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
|
||||
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_RTSR register *******************/
|
||||
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
||||
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
||||
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
||||
|
|
@ -3483,14 +3479,11 @@ typedef struct
|
|||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
|
||||
#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
|
||||
#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
|
||||
#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
|
||||
#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
|
||||
#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
|
||||
#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
|
||||
#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
|
||||
#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
||||
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
||||
|
|
@ -3514,14 +3507,11 @@ typedef struct
|
|||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
|
||||
#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
|
||||
#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
|
||||
#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
|
||||
#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
|
||||
#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
|
||||
#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
|
||||
#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
|
||||
#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
||||
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
||||
|
|
@ -3545,14 +3535,11 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
|
||||
#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
|
||||
#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
|
||||
#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
|
||||
#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
|
||||
#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
|
||||
#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
|
||||
#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
|
||||
#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
||||
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
||||
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
||||
|
|
@ -3576,12 +3563,37 @@ typedef struct
|
|||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
|
||||
#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
|
||||
#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
|
||||
#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
|
||||
#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
|
||||
#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
|
||||
#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
|
||||
#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
|
||||
#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
|
||||
#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_IMR2 register ******************/
|
||||
#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
|
||||
#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
|
||||
#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
|
||||
#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
|
||||
#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
|
||||
#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
|
||||
#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3646,6 +3658,11 @@ typedef struct
|
|||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
|
||||
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
|
||||
#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
|
||||
#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
|
||||
|
||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
||||
|
|
@ -3675,6 +3692,7 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* General Purpose I/O (GPIO) */
|
||||
|
|
@ -4068,13 +4086,18 @@ typedef struct
|
|||
#define HRTIM_MCMP1R_MCMP1R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
|
||||
|
||||
/******************* Bit definition for HRTIM_MCMP2R register *****************/
|
||||
#define HRTIM_MCMP1R_MCMP2R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
|
||||
#define HRTIM_MCMP2R_MCMP2R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
|
||||
|
||||
/******************* Bit definition for HRTIM_MCMP3R register *****************/
|
||||
#define HRTIM_MCMP1R_MCMP3R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
|
||||
#define HRTIM_MCMP3R_MCMP3R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
|
||||
|
||||
/******************* Bit definition for HRTIM_MCMP4R register *****************/
|
||||
#define HRTIM_MCMP1R_MCMP4R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
|
||||
#define HRTIM_MCMP4R_MCMP4R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
|
||||
|
||||
/* Legacy defines */
|
||||
#define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP2R_MCMP2R
|
||||
#define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP3R_MCMP3R
|
||||
#define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP4R_MCMP4R
|
||||
|
||||
/******************** Slave control register **********************************/
|
||||
#define HRTIM_TIMCR_CK_PSC ((uint32_t)0x00000007) /*!< Slave prescaler mask*/
|
||||
|
|
@ -5175,7 +5198,7 @@ typedef struct
|
|||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||||
|
|
@ -5189,6 +5212,9 @@ typedef struct
|
|||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||||
|
||||
/* Legacy defines */
|
||||
#define I2C_CR1_DFN I2C_CR1_DNF
|
||||
|
||||
/****************** Bit definition for I2C_CR2 register ********************/
|
||||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||||
|
|
@ -5208,9 +5234,17 @@ typedef struct
|
|||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||||
|
||||
/******************* Bit definition for I2C_OAR2 register *******************/
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
|
||||
#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
||||
#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
||||
#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
||||
#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
||||
#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
||||
#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
||||
#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
|
||||
/******************* Bit definition for I2C_TIMINGR register *****************/
|
||||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||||
|
|
@ -5477,7 +5511,7 @@ typedef struct
|
|||
#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
|
||||
#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
|
||||
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
|
||||
|
||||
/********************* Bit definition for RCC_CIR register ********************/
|
||||
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
|
||||
|
|
@ -5506,7 +5540,7 @@ typedef struct
|
|||
#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
|
||||
#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
|
||||
#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
|
||||
#define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /*!< TIM17 reset */
|
||||
#define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /*!< HRTIM1 reset */
|
||||
|
||||
/****************** Bit definition for RCC_APB1RSTR register ******************/
|
||||
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
|
||||
|
|
@ -5532,7 +5566,7 @@ typedef struct
|
|||
#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
|
||||
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
|
||||
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
|
||||
|
||||
/***************** Bit definition for RCC_APB2ENR register ******************/
|
||||
|
|
@ -5543,7 +5577,7 @@ typedef struct
|
|||
#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
|
||||
#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
|
||||
#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
|
||||
#define RCC_APB2ENR_HRTIM1EN ((uint32_t)0x20000000) /*!< TIM17 reset */
|
||||
#define RCC_APB2ENR_HRTIM1EN ((uint32_t)0x20000000) /*!< HRTIM1 reset */
|
||||
|
||||
/****************** Bit definition for RCC_APB1ENR register ******************/
|
||||
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
|
||||
|
|
@ -5655,34 +5689,34 @@ typedef struct
|
|||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||||
/* Legacy defines */
|
||||
#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
|
||||
|
||||
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000010) /*!< I2CSW bits */
|
||||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||||
|
||||
#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
|
||||
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000100) /*!< TIMSW bits */
|
||||
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
|
||||
|
||||
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
|
||||
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
|
||||
|
||||
#define RCC_CFGR3_HRTIMSW ((uint32_t)0x00001000) /*!< TIMSW bits */
|
||||
#define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /*!< TIM1SW bits */
|
||||
#define RCC_CFGR3_HRTIMSW ((uint32_t)0x00001000) /*!< HRTIM1SW bits */
|
||||
#define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /*!< HRTIM1SW bits */
|
||||
|
||||
#define RCC_CFGR3_HRTIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
|
||||
#define RCC_CFGR3_HRTIM1SW_PLL ((uint32_t)0x00001000) /*!< PLL clock used as TIM1 clock source */
|
||||
#define RCC_CFGR3_HRTIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as HRTIM1 clock source */
|
||||
#define RCC_CFGR3_HRTIM1SW_PLL ((uint32_t)0x00001000) /*!< PLL clock used as HRTIM1 clock source */
|
||||
|
||||
#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
|
||||
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
|
||||
|
|
@ -5691,7 +5725,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
|
||||
|
|
@ -6027,41 +6061,8 @@ typedef struct
|
|||
/******************** Bits definition for RTC_BKP4R register ****************/
|
||||
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP5R register ****************/
|
||||
#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP6R register ****************/
|
||||
#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP7R register ****************/
|
||||
#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP8R register ****************/
|
||||
#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP9R register ****************/
|
||||
#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP10R register ***************/
|
||||
#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP11R register ***************/
|
||||
#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP12R register ***************/
|
||||
#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP13R register ***************/
|
||||
#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP14R register ***************/
|
||||
#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Bits definition for RTC_BKP15R register ***************/
|
||||
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Number of backup registers ******************************/
|
||||
#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_NUMBER 5
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -6139,7 +6140,7 @@ typedef struct
|
|||
/* System Configuration(SYSCFG) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register *****************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
|
||||
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
|
@ -6148,8 +6149,8 @@ typedef struct
|
|||
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x0000F800) /*!< DMA remap mask */
|
||||
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
|
||||
#define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
||||
|
|
@ -6349,10 +6350,10 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register *****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
|
||||
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
|
||||
|
||||
|
|
@ -6640,7 +6641,7 @@ typedef struct
|
|||
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
|
||||
|
||||
/******************* Bit definition for TIM_RCR register ********************/
|
||||
#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
|
||||
#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
|
||||
|
|
@ -7163,11 +7164,10 @@ typedef struct
|
|||
/****************************** ADC Instances *********************************/
|
||||
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
|
||||
((INSTANCE) == ADC2))
|
||||
|
||||
|
||||
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
|
||||
|
||||
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON))
|
||||
|
||||
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_2_COMMON)
|
||||
/****************************** CAN Instances *********************************/
|
||||
#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
|
||||
|
||||
|
|
@ -7207,32 +7207,45 @@ typedef struct
|
|||
((INSTANCE) == DMA1_Channel7))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
/****************************** HRTIM Instances *********************************/
|
||||
#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
|
||||
|
||||
/****************************** I2C Instances *********************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** OPAMP Instances *******************************/
|
||||
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** RTC Instances *********************************/
|
||||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||||
|
||||
/****************************** SMBUS Instances *******************************/
|
||||
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
|
||||
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
|
||||
|
||||
/****************************** SPI Instances *********************************/
|
||||
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1))
|
||||
#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
|
||||
|
||||
/******************* TIM Instances : All supported instances ******************/
|
||||
#define IS_TIM_INSTANCE(INSTANCE)\
|
||||
|
|
@ -7280,7 +7293,7 @@ typedef struct
|
|||
/****************** TIM Instances : at least 6 capture/compare channels *******/
|
||||
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1))
|
||||
|
||||
|
||||
/************************** TIM Instances : Advanced-control timers ***********/
|
||||
|
||||
/****************** TIM Instances : supporting clock selection ****************/
|
||||
|
|
@ -7372,9 +7385,9 @@ typedef struct
|
|||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting the break function *************/
|
||||
|
|
@ -7521,7 +7534,7 @@ typedef struct
|
|||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
||||
/******************** UART Instances : Wake-up from Stop mode **********************/
|
||||
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
|
@ -7544,6 +7557,8 @@ typedef struct
|
|||
/*********************** UART Instances : IRDA mode ***************************/
|
||||
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
/******************** UART Instances : Support of continuous communication using DMA ****/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
|
||||
/****************************** WWDG Instances ********************************/
|
||||
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
||||
|
||||
|
|
@ -7561,31 +7576,40 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
|
||||
#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define I2C3_ER_IRQn HRTIM1_FLT_IRQn
|
||||
#define I2C3_EV_IRQn HRTIM1_TIME_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM18_DAC2_IRQn TIM1_CC_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
|
||||
#define TIM7_IRQn TIM7_DAC2_IRQn
|
||||
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
|
||||
#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define COMP_IRQn COMP2_IRQn
|
||||
#define COMP1_2_3_IRQn COMP2_IRQn
|
||||
#define COMP1_2_IRQn COMP2_IRQn
|
||||
#define COMP4_5_6_IRQn COMP4_6_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
|
||||
#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
|
||||
#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP2_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP2_IRQHandler
|
||||
#define COMP_IRQHandler COMP2_IRQHandler
|
||||
#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
|
||||
#define I2C3_ER_IRQHandler HRTIM1_FLT_IRQHandler
|
||||
#define I2C3_EV_IRQHandler HRTIM1_TIME_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
|
||||
#define TIM7_IRQHandler TIM7_DAC2_IRQHandler
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@
|
|||
******************************************************************************
|
||||
* @file stm32f358xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CMSIS STM32F358xx Device Peripheral Access Layer Header File.
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS STM32F358xx Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -63,11 +63,11 @@
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< STM32F358xx devices provide an MPU */
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< STM32F358xx devices provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F358xx devices use 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F358xx devices provide an FPU */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F358xx devices provide an FPU */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -111,8 +111,8 @@ typedef enum
|
|||
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
|
||||
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
|
||||
ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
|
||||
CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
|
||||
CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
|
||||
CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
|
||||
CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
|
||||
CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
|
||||
CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
|
||||
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
|
||||
|
|
@ -142,7 +142,7 @@ typedef enum
|
|||
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
|
||||
UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
|
||||
UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
|
||||
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */
|
||||
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
|
||||
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
|
||||
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
|
||||
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
|
||||
|
|
@ -153,7 +153,7 @@ typedef enum
|
|||
COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
|
||||
COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
|
||||
COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
|
||||
FPU_IRQn = 81 /*!< Floating point Interrupt */
|
||||
FPU_IRQn = 81, /*!< Floating point Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
|
|
@ -356,8 +356,8 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
|
||||
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
|
||||
} DMA_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -366,20 +366,20 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
|
||||
__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
|
||||
__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
|
||||
__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
|
||||
__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
|
||||
__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
uint32_t RESERVED2; /*!< Reserved, 0x1C */
|
||||
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
|
||||
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
|
||||
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
|
||||
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
|
||||
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
|
||||
__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
|
||||
}EXTI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -427,8 +427,7 @@ typedef struct
|
|||
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
||||
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
||||
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
||||
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
|
||||
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
|
||||
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
|
||||
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
||||
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
|
|
@ -449,10 +448,10 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
__IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
} SYSCFG_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -568,13 +567,13 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
||||
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
||||
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
|
||||
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
||||
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
||||
} SPI_TypeDef;
|
||||
|
|
@ -666,14 +665,12 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 256KB) base address in the alias region */
|
||||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 40KB) base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
|
||||
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the bit-band region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 40KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
||||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
|
||||
/*!< Peripheral memory map */
|
||||
|
|
@ -768,7 +765,7 @@ typedef struct
|
|||
#define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
|
||||
#define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
|
||||
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -796,9 +793,9 @@ typedef struct
|
|||
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
|
||||
#define CAN ((CAN_TypeDef *) CAN_BASE)
|
||||
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
|
||||
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
|
||||
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
|
||||
|
|
@ -806,12 +803,12 @@ typedef struct
|
|||
#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
|
||||
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
|
||||
#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
|
||||
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
||||
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
|
||||
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
||||
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
||||
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
|
||||
#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
|
||||
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
||||
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
||||
|
|
@ -852,6 +849,7 @@ typedef struct
|
|||
#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
|
||||
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
|
||||
#define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -873,6 +871,7 @@ typedef struct
|
|||
/* Analog to Digital Converter SAR (ADC) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************** Bit definition for ADC_ISR register ********************/
|
||||
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
|
||||
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
|
||||
|
|
@ -1739,6 +1738,7 @@ typedef struct
|
|||
/* Analog Comparators (COMP) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/********************** Bit definition for COMP1_CSR register ***************/
|
||||
#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
|
||||
#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
|
||||
|
|
@ -1954,7 +1954,6 @@ typedef struct
|
|||
#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
|
||||
#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
|
||||
#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
|
||||
#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
|
||||
#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
|
||||
#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
|
||||
|
||||
|
|
@ -3378,7 +3377,7 @@ typedef struct
|
|||
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
||||
|
||||
/******************* Bit definition for CRC_IDR register ********************/
|
||||
#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
|
||||
/******************** Bit definition for CRC_CR register ********************/
|
||||
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
|
||||
|
|
@ -3631,7 +3630,7 @@ typedef struct
|
|||
/* External Interrupt/Event Controller (EXTI) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
|
||||
/******************* Bit definition for EXTI_IMR register *******************/
|
||||
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
||||
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
||||
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
||||
|
|
@ -3661,8 +3660,11 @@ typedef struct
|
|||
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
|
||||
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
|
||||
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
|
||||
#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
|
||||
#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
|
||||
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
|
||||
/******************* Bit definition for EXTI_EMR register *******************/
|
||||
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
||||
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
||||
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
||||
|
|
@ -3692,8 +3694,11 @@ typedef struct
|
|||
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
|
||||
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
|
||||
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
|
||||
#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
|
||||
#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
|
||||
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_RTSR register *******************/
|
||||
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
||||
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
||||
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
||||
|
|
@ -3717,14 +3722,11 @@ typedef struct
|
|||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
|
||||
#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
|
||||
#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
|
||||
#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
|
||||
#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
|
||||
#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
|
||||
#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
|
||||
#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
|
||||
#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
||||
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
||||
|
|
@ -3748,14 +3750,11 @@ typedef struct
|
|||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
|
||||
#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
|
||||
#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
|
||||
#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
|
||||
#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
|
||||
#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
|
||||
#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
|
||||
#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
|
||||
#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
||||
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
||||
|
|
@ -3779,14 +3778,11 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
|
||||
#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
|
||||
#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
|
||||
#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
|
||||
#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
|
||||
#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
|
||||
#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
|
||||
#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
|
||||
#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
||||
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
||||
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
||||
|
|
@ -3810,12 +3806,37 @@ typedef struct
|
|||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
|
||||
#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
|
||||
#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
|
||||
#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
|
||||
#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
|
||||
#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
|
||||
#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
|
||||
#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
|
||||
#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
|
||||
#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
|
||||
|
||||
/******************* Bit definition for EXTI_IMR2 register ******************/
|
||||
#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
|
||||
#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
|
||||
#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
|
||||
#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
|
||||
|
||||
/******************* Bit definition for EXTI_EMR2 ****************************/
|
||||
#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
|
||||
#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
|
||||
#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
|
||||
#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register ********************/
|
||||
#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
|
||||
#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register ******************/
|
||||
#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
|
||||
#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register *****************/
|
||||
#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
|
||||
#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR2 register *******************/
|
||||
#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
|
||||
#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -3880,6 +3901,11 @@ typedef struct
|
|||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
|
||||
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
|
||||
#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
|
||||
#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
|
||||
|
||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
||||
|
|
@ -3909,6 +3935,7 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* General Purpose I/O (GPIO) */
|
||||
|
|
@ -4223,7 +4250,7 @@ typedef struct
|
|||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||||
|
|
@ -4237,6 +4264,9 @@ typedef struct
|
|||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||||
|
||||
/* Legacy defines */
|
||||
#define I2C_CR1_DFN I2C_CR1_DNF
|
||||
|
||||
/****************** Bit definition for I2C_CR2 register ********************/
|
||||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||||
|
|
@ -4256,9 +4286,17 @@ typedef struct
|
|||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||||
|
||||
/******************* Bit definition for I2C_OAR2 register *******************/
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
|
||||
#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
||||
#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
||||
#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
||||
#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
||||
#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
||||
#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
||||
#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
|
||||
/******************* Bit definition for I2C_TIMINGR register *****************/
|
||||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||||
|
|
@ -4506,7 +4544,7 @@ typedef struct
|
|||
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
|
||||
|
||||
#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
|
||||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
|
||||
|
||||
/********************* Bit definition for RCC_CIR register ********************/
|
||||
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
|
||||
|
|
@ -4568,7 +4606,7 @@ typedef struct
|
|||
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
|
||||
#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
|
||||
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
|
||||
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
|
||||
#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
|
||||
|
||||
|
|
@ -4721,10 +4759,12 @@ typedef struct
|
|||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||||
/* Legacy defines */
|
||||
#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
|
||||
|
||||
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
|
||||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||||
|
|
@ -4734,14 +4774,11 @@ typedef struct
|
|||
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
|
||||
#define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
|
||||
#define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000300) /*!< TIMSW bits */
|
||||
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
|
||||
#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
|
||||
|
||||
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
|
||||
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
|
||||
|
||||
#define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
|
||||
#define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
|
||||
|
||||
|
|
@ -4749,7 +4786,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
|
||||
|
|
@ -4758,7 +4795,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
|
||||
|
|
@ -4767,7 +4804,7 @@ typedef struct
|
|||
#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
|
||||
#define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
|
||||
|
|
@ -4776,7 +4813,7 @@ typedef struct
|
|||
#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
|
||||
#define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
|
||||
|
|
@ -5146,7 +5183,7 @@ typedef struct
|
|||
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Number of backup registers ******************************/
|
||||
#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_NUMBER 16
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -5245,7 +5282,7 @@ typedef struct
|
|||
/* System Configuration(SYSCFG) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register *****************/
|
||||
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
|
||||
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
|
@ -5255,8 +5292,8 @@ typedef struct
|
|||
#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
|
||||
#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
||||
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
|
||||
|
|
@ -5460,9 +5497,9 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register *****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/8/15/16/17 */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
|
||||
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
|
||||
|
||||
|
|
@ -5729,7 +5766,7 @@ typedef struct
|
|||
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
|
||||
|
||||
/******************* Bit definition for TIM_RCR register ********************/
|
||||
#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
|
||||
#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
|
||||
|
|
@ -6294,9 +6331,9 @@ typedef struct
|
|||
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
|
||||
|
||||
#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
|
||||
(((INSTANCE) == DAC1) && \
|
||||
((((INSTANCE) == DAC1) && \
|
||||
(((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2)))
|
||||
((CHANNEL) == DAC_CHANNEL_2))))
|
||||
|
||||
/****************************** DMA Instances *********************************/
|
||||
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
|
||||
|
|
@ -6313,12 +6350,23 @@ typedef struct
|
|||
((INSTANCE) == DMA2_Channel5))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOD))
|
||||
|
||||
/****************************** I2C Instances *********************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
||||
|
|
@ -6328,15 +6376,15 @@ typedef struct
|
|||
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
|
||||
((INSTANCE) == SPI3))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** OPAMP Instances *******************************/
|
||||
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
|
||||
((INSTANCE) == OPAMP2) || \
|
||||
((INSTANCE) == OPAMP3) || \
|
||||
((INSTANCE) == OPAMP4))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/****************************** RTC Instances *********************************/
|
||||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||||
|
||||
|
|
@ -6407,7 +6455,7 @@ typedef struct
|
|||
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
|
||||
/************************** TIM Instances : Advanced-control timers ***********/
|
||||
|
||||
/****************** TIM Instances : supporting clock selection ****************/
|
||||
|
|
@ -6522,11 +6570,11 @@ typedef struct
|
|||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM15) || \
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting the break function *************/
|
||||
|
|
@ -6589,10 +6637,10 @@ typedef struct
|
|||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3))) \
|
||||
|| \
|
||||
|| \
|
||||
(((INSTANCE) == TIM8) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM15) && \
|
||||
|
|
@ -6710,7 +6758,7 @@ typedef struct
|
|||
((INSTANCE) == USART3) || \
|
||||
((INSTANCE) == UART4) || \
|
||||
((INSTANCE) == UART5))
|
||||
|
||||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
|
|
@ -6752,6 +6800,9 @@ typedef struct
|
|||
((INSTANCE) == UART4) || \
|
||||
((INSTANCE) == UART5))
|
||||
|
||||
/******************** UART Instances : Support of continuous communication using DMA ****/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
|
||||
|
||||
/****************************** WWDG Instances ********************************/
|
||||
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
||||
|
||||
|
|
@ -6769,31 +6820,44 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define SDADC1_IRQn ADC4_IRQn
|
||||
#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
|
||||
#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
|
||||
#define COMP1_2_IRQn COMP1_2_3_IRQn
|
||||
#define COMP2_IRQn COMP1_2_3_IRQn
|
||||
#define COMP_IRQn COMP1_2_3_IRQn
|
||||
#define COMP4_6_IRQn COMP4_5_6_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM18_DAC2_IRQn TIM1_CC_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
#define TIM7_DAC2_IRQn TIM7_IRQn
|
||||
#define TIM12_IRQn TIM8_BRK_IRQn
|
||||
#define TIM14_IRQn TIM8_TRG_COM_IRQn
|
||||
#define TIM13_IRQn TIM8_UP_IRQn
|
||||
|
||||
#define ADC1_IRQn ADC1_2_IRQn
|
||||
#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
|
||||
#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
|
||||
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#define COMP_IRQn COMP1_2_3_IRQn
|
||||
#define COMP2_IRQn COMP1_2_3_IRQn
|
||||
#define COMP1_2_IRQn COMP1_2_3_IRQn
|
||||
#define COMP4_6_IRQn COMP4_5_6_IRQn
|
||||
#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
|
||||
#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define COMP_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP2_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
#define ADC1_IRQHandler ADC1_2_IRQHandler
|
||||
#define SDADC1_IRQHandler ADC4_IRQHandler
|
||||
#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
|
||||
#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP2_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP_IRQHandler COMP1_2_3_IRQHandler
|
||||
#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
|
||||
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
|
||||
#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
|
||||
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
|
||||
#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
|
||||
#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
|
||||
#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
|
||||
#define TIM12_IRQHandler TIM8_BRK_IRQHandler
|
||||
#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
|
||||
#define TIM13_IRQHandler TIM8_UP_IRQHandler
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@
|
|||
******************************************************************************
|
||||
* @file stm32f373xc.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @brief CMSIS STM32F373xB/STM32F373xC Devices Peripheral Access Layer Header File.
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS STM32F373xC Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -64,10 +64,10 @@
|
|||
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< STM32F373xB/STM32F373xC devices provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F373xB/STM32F373xC devices use 4 Bits for the Priority Levels */
|
||||
#define __MPU_PRESENT 1 /*!< STM32F373xC devices provide an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< STM32F373xC devices use 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F373xB/STM32F373xC devices provide an FPU */
|
||||
#define __FPU_PRESENT 1 /*!< STM32F373xC devices provide an FPU */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32F373xB/STM32F373xC devices Interrupt Number Definition, according to the selected device
|
||||
* @brief STM32F373xC devices Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum
|
||||
|
|
@ -141,7 +141,7 @@ typedef enum
|
|||
TIM14_IRQn = 45, /*!< TIM14 global interrupt */
|
||||
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
|
||||
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
|
||||
TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/
|
||||
TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
|
||||
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
|
||||
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
|
||||
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
|
||||
|
|
@ -156,7 +156,7 @@ typedef enum
|
|||
USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
|
||||
USBWakeUp_IRQn = 76, /*!< USB Wakeup Interrupt */
|
||||
TIM19_IRQn = 78, /*!< TIM19 global Interrupt */
|
||||
FPU_IRQn = 81 /*!< Floating point Interrupt */
|
||||
FPU_IRQn = 81, /*!< Floating point Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
|
|
@ -198,8 +198,6 @@ typedef struct
|
|||
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
|
||||
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
|
||||
} ADC_TypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Controller Area Network TxMailBox
|
||||
*/
|
||||
|
|
@ -415,8 +413,7 @@ typedef struct
|
|||
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
||||
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
||||
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
||||
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
|
||||
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
|
||||
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
|
||||
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
||||
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
|
|
@ -430,7 +427,7 @@ typedef struct
|
|||
{
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
uint32_t RESERVED; /*!< Reserved, 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG control register, Adress offset: 0x14-0x08 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
} SYSCFG_TypeDef;
|
||||
|
||||
|
|
@ -593,13 +590,13 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
||||
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
||||
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
|
||||
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
||||
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
||||
} SPI_TypeDef;
|
||||
|
|
@ -705,7 +702,7 @@ typedef struct
|
|||
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
|
||||
__IO uint16_t RESERVEDB; /*!< Reserved */
|
||||
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
|
||||
__IO uint16_t RESERVEDC; /*!< Reserved */
|
||||
__IO uint16_t RESERVEDC; /*!< Reserved */
|
||||
} USB_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -725,7 +722,6 @@ typedef struct
|
|||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
|
|
@ -760,9 +756,9 @@ typedef struct
|
|||
#define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
|
||||
#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
|
||||
#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
|
||||
#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
|
||||
#define DAC_BASE DAC1_BASE
|
||||
#define CEC_BASE (APB1PERIPH_BASE + 0x00007800)
|
||||
#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
|
||||
#define TIM18_BASE (APB1PERIPH_BASE + 0x00009C00)
|
||||
|
||||
/*!< APB2 peripherals */
|
||||
|
|
@ -847,14 +843,13 @@ typedef struct
|
|||
#define TIM18 ((TIM_TypeDef *) TIM18_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||||
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE)
|
||||
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
|
||||
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
|
||||
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
|
||||
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
||||
#define TIM19 ((TIM_TypeDef *) TIM19_BASE)
|
||||
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
||||
#define SDADC1 ((SDADC_TypeDef *) SDADC1_BASE)
|
||||
#define SDADC2 ((SDADC_TypeDef *) SDADC2_BASE)
|
||||
#define SDADC3 ((SDADC_TypeDef *) SDADC3_BASE)
|
||||
|
|
@ -883,7 +878,9 @@ typedef struct
|
|||
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
|
||||
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
|
||||
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
|
||||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||||
#define USB ((USB_TypeDef *) USB_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1037,22 +1034,22 @@ typedef struct
|
|||
#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
|
||||
|
||||
/****************** Bit definition for ADC_JOFR1 register *******************/
|
||||
#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
|
||||
#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
|
||||
|
||||
/****************** Bit definition for ADC_JOFR2 register *******************/
|
||||
#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
|
||||
#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
|
||||
|
||||
/****************** Bit definition for ADC_JOFR3 register *******************/
|
||||
#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
|
||||
#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
|
||||
|
||||
/****************** Bit definition for ADC_JOFR4 register *******************/
|
||||
#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
|
||||
#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
|
||||
|
||||
/******************* Bit definition for ADC_HTR register ********************/
|
||||
#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
|
||||
#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
|
||||
|
||||
/******************* Bit definition for ADC_LTR register ********************/
|
||||
#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
|
||||
#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
|
||||
|
||||
/******************* Bit definition for ADC_SQR1 register *******************/
|
||||
#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
|
||||
|
|
@ -1253,25 +1250,25 @@ typedef struct
|
|||
#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
|
||||
#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
|
||||
/* COMPx bits definition */
|
||||
#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
|
||||
#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
|
||||
#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
|
||||
#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
|
||||
#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
|
||||
#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
|
||||
#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
|
||||
#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
|
||||
#define COMP_CSR_COMPxWNDWEN ((uint16_t)0x0080) /*!< COMPx window mode enable */
|
||||
#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
|
||||
#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
|
||||
#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
|
||||
#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
|
||||
#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
|
||||
#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
|
||||
#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
|
||||
#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x2000) /*!< COMPx hysteresis bit 1 */
|
||||
#define COMP_CSR_COMPxOUT ((uint32_t)0x4000) /*!< COMPx output level */
|
||||
#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
|
||||
#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
|
||||
#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
|
||||
#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
|
||||
#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
|
||||
#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
|
||||
#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
|
||||
#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
|
||||
#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
|
||||
#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000080) /*!< COMPx window mode enable */
|
||||
#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
|
||||
#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
|
||||
#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
|
||||
#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
|
||||
#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
|
||||
#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
|
||||
#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
|
||||
#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
|
||||
#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
|
||||
#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -2538,7 +2535,7 @@ typedef struct
|
|||
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
||||
|
||||
/******************* Bit definition for CRC_IDR register ********************/
|
||||
#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
|
||||
/******************** Bit definition for CRC_CR register ********************/
|
||||
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
|
||||
|
|
@ -2876,17 +2873,7 @@ typedef struct
|
|||
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
|
||||
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
|
||||
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
|
||||
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
|
||||
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
|
||||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
|
||||
#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
|
||||
#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
|
||||
#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
|
||||
#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
|
||||
#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
|
|
@ -2907,17 +2894,7 @@ typedef struct
|
|||
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
|
||||
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
|
||||
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
|
||||
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
|
||||
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
|
||||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
|
||||
#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
|
||||
#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
|
||||
#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
|
||||
#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
|
||||
#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
|
|
@ -2938,17 +2915,7 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
|
||||
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
|
||||
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
|
||||
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
|
||||
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
|
||||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
|
||||
#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
|
||||
#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
|
||||
#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
|
||||
#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
|
||||
#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
||||
|
|
@ -2969,18 +2936,7 @@ typedef struct
|
|||
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
|
||||
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
|
||||
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
|
||||
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
|
||||
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
|
||||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
|
||||
#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
|
||||
#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
|
||||
#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
|
||||
#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
|
||||
#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
|
||||
#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* FLASH */
|
||||
|
|
@ -3035,13 +2991,18 @@ typedef struct
|
|||
#define FLASH_OBR_LEVEL2_PROT ((uint32_t)0x00000004) /*!< Level 2 Read protection status */
|
||||
|
||||
#define FLASH_OBR_USER ((uint32_t)0x0000F700) /*!< User Option Bytes */
|
||||
#define FLASH_OBR_WDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
|
||||
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
|
||||
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
|
||||
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
|
||||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
|
||||
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
|
||||
#define FLASH_OBR_SDADC12_VDD_MONITOR ((uint32_t)0x00008000) /*!< SDADC12_VDD_MONITOR */
|
||||
#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
|
||||
#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
|
||||
|
||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
||||
|
|
@ -3071,6 +3032,7 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* General Purpose I/O (GPIO) */
|
||||
|
|
@ -3385,7 +3347,7 @@ typedef struct
|
|||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||||
|
|
@ -3399,6 +3361,9 @@ typedef struct
|
|||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||||
|
||||
/* Legacy defines */
|
||||
#define I2C_CR1_DFN I2C_CR1_DNF
|
||||
|
||||
/****************** Bit definition for I2C_CR2 register ********************/
|
||||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||||
|
|
@ -3418,9 +3383,17 @@ typedef struct
|
|||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||||
|
||||
/******************* Bit definition for I2C_OAR2 register *******************/
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
|
||||
#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
||||
#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
||||
#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
||||
#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
||||
#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
||||
#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
||||
#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
|
||||
/******************* Bit definition for I2C_TIMINGR register *****************/
|
||||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||||
|
|
@ -3916,7 +3889,6 @@ typedef struct
|
|||
/******************** Bit definition for RCC_CSR register *******************/
|
||||
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
|
||||
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
|
||||
#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
|
||||
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
|
||||
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
|
||||
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
|
||||
|
|
@ -3965,10 +3937,12 @@ typedef struct
|
|||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||||
/* Legacy defines */
|
||||
#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
|
||||
|
||||
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
|
||||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||||
|
|
@ -3988,7 +3962,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
|
||||
|
|
@ -3997,7 +3971,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
|
||||
|
|
@ -4415,7 +4389,7 @@ typedef struct
|
|||
#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Number of backup registers ******************************/
|
||||
#define RTC_BKP_NUMBER ((uint32_t)0x00000020)
|
||||
#define RTC_BKP_NUMBER 32
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -4785,7 +4759,7 @@ typedef struct
|
|||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00008000) /*!< PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
|
||||
|
|
@ -4872,9 +4846,9 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM15/16/17 */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM15/16/17 */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
|
||||
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
|
||||
|
||||
/******************************************************************************/
|
||||
|
|
@ -4899,7 +4873,6 @@ typedef struct
|
|||
#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
|
||||
|
||||
/******************* Bit definition for TIM_CR2 register ********************/
|
||||
#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
|
||||
#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
|
||||
|
|
@ -5561,7 +5534,7 @@ typedef struct
|
|||
|
||||
/**************************** ISTR interrupt events *************************/
|
||||
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
|
||||
#define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
|
||||
#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
|
||||
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
|
||||
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
|
||||
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
|
||||
|
|
@ -5571,8 +5544,11 @@ typedef struct
|
|||
#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
|
||||
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
|
||||
|
||||
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
|
||||
#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
|
||||
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
|
||||
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
|
||||
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
|
||||
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
|
||||
|
|
@ -5580,9 +5556,12 @@ typedef struct
|
|||
#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
|
||||
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
|
||||
|
||||
/************************* CNTR control register bits definitions ***********/
|
||||
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
|
||||
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
|
||||
#define USB_CNTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
|
||||
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
|
||||
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
|
||||
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
|
||||
|
|
@ -5591,10 +5570,14 @@ typedef struct
|
|||
#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
|
||||
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
|
||||
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
|
||||
#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
|
||||
#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
|
||||
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
|
||||
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
|
||||
|
||||
/* Legacy defines */
|
||||
#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
|
||||
#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
|
||||
|
||||
/******************** FNR Frame Number Register bit definitions ************/
|
||||
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
|
||||
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
|
||||
|
|
@ -5728,7 +5711,7 @@ typedef struct
|
|||
/****************************** DAC Instances *********************************/
|
||||
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
|
||||
((INSTANCE) == DAC2))
|
||||
|
||||
|
||||
#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
|
||||
((((INSTANCE) == DAC1) && \
|
||||
(((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
|
|
@ -5752,12 +5735,23 @@ typedef struct
|
|||
((INSTANCE) == DMA2_Channel5))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOD))
|
||||
|
||||
/****************************** I2C Instances *********************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
||||
|
|
@ -6155,6 +6149,9 @@ typedef struct
|
|||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/******************** UART Instances : Support of continuous communication using DMA ****/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
|
||||
|
||||
/****************************** USB Instances *********************************/
|
||||
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
|
||||
|
||||
|
|
@ -6175,25 +6172,48 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
|
||||
#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
|
||||
#define USBWakeUp_IRQn CEC_IRQn
|
||||
#define COMP1_2_IRQn COMP_IRQn
|
||||
#define COMP1_2_3_IRQn COMP_IRQn
|
||||
#define COMP2_IRQn COMP_IRQn
|
||||
#define ADC4_IRQn SDADC1_IRQn
|
||||
#define TIM8_BRK_IRQn TIM12_IRQn
|
||||
#define TIM8_UP_IRQn TIM13_IRQn
|
||||
#define TIM8_TRG_COM_IRQn TIM14_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM15_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM16_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM17_IRQn
|
||||
#define TIM1_CC_IRQn TIM18_DAC2_IRQn
|
||||
#define TIM20_UP_IRQn TIM19_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
|
||||
#define TIM7_DAC2_IRQn TIM7_IRQn
|
||||
#define USBWakeUp_RMP_IRQn USBWakeUp_IRQn
|
||||
|
||||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM15_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM16_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM17_IRQn
|
||||
#define COMP2_IRQn COMP_IRQn
|
||||
#define COMP1_2_IRQn COMP_IRQn
|
||||
#define COMP1_2_3_IRQn COMP_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM15_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM16_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM17_IRQHandler
|
||||
#define COMP2_IRQHandler COMP_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
|
||||
#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
|
||||
#define USBWakeUp_IRQHandler CEC_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP_IRQHandler
|
||||
#define COMP2_IRQHandler COMP_IRQHandler
|
||||
#define ADC4_IRQHandler SDADC1_IRQHandler
|
||||
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
|
||||
#define TIM8_UP_IRQHandler TIM13_IRQHandler
|
||||
#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM15_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM16_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM17_IRQHandler
|
||||
#define TIM1_CC_IRQHandler TIM18_DAC2_IRQHandler
|
||||
#define TIM20_UP_IRQHandler TIM19_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
|
||||
#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
|
||||
#define USBWakeUp_RMP_IRQHandler USBWakeUp_IRQHandler
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f378xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS STM32F378xx Devices Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -140,7 +140,7 @@ typedef enum
|
|||
TIM14_IRQn = 45, /*!< TIM14 global interrupt */
|
||||
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
|
||||
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
|
||||
TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/
|
||||
TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
|
||||
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
|
||||
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
|
||||
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
|
||||
|
|
@ -152,7 +152,7 @@ typedef enum
|
|||
SDADC3_IRQn = 63, /*!< ADC Sigma Delta 1 global Interrupt */
|
||||
COMP_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt */
|
||||
TIM19_IRQn = 78, /*!< TIM19 global Interrupt */
|
||||
FPU_IRQn = 81 /*!< Floating point Interrupt */
|
||||
FPU_IRQn = 81, /*!< Floating point Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
|
|
@ -194,8 +194,6 @@ typedef struct
|
|||
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
|
||||
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
|
||||
} ADC_TypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Controller Area Network TxMailBox
|
||||
*/
|
||||
|
|
@ -411,8 +409,7 @@ typedef struct
|
|||
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
||||
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
||||
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
||||
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
|
||||
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
|
||||
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
|
||||
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
||||
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
||||
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
|
||||
|
|
@ -426,7 +423,7 @@ typedef struct
|
|||
{
|
||||
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
||||
uint32_t RESERVED; /*!< Reserved, 0x04 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG control register, Adress offset: 0x14-0x08 */
|
||||
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
|
||||
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
||||
} SYSCFG_TypeDef;
|
||||
|
||||
|
|
@ -589,13 +586,13 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
|
||||
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
|
||||
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
||||
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
||||
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
|
||||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
|
||||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
|
||||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
|
||||
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
||||
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
||||
} SPI_TypeDef;
|
||||
|
|
@ -687,7 +684,6 @@ typedef struct
|
|||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
|
||||
|
|
@ -720,9 +716,9 @@ typedef struct
|
|||
#define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
|
||||
#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
|
||||
#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
|
||||
#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
|
||||
#define DAC_BASE DAC1_BASE
|
||||
#define CEC_BASE (APB1PERIPH_BASE + 0x00007800)
|
||||
#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
|
||||
#define TIM18_BASE (APB1PERIPH_BASE + 0x00009C00)
|
||||
|
||||
/*!< APB2 peripherals */
|
||||
|
|
@ -807,14 +803,13 @@ typedef struct
|
|||
#define TIM18 ((TIM_TypeDef *) TIM18_BASE)
|
||||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||||
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE)
|
||||
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
|
||||
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
|
||||
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
|
||||
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
||||
#define TIM19 ((TIM_TypeDef *) TIM19_BASE)
|
||||
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
||||
#define SDADC1 ((SDADC_TypeDef *) SDADC1_BASE)
|
||||
#define SDADC2 ((SDADC_TypeDef *) SDADC2_BASE)
|
||||
#define SDADC3 ((SDADC_TypeDef *) SDADC3_BASE)
|
||||
|
|
@ -843,6 +838,8 @@ typedef struct
|
|||
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
|
||||
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
|
||||
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
|
||||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -996,22 +993,22 @@ typedef struct
|
|||
#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
|
||||
|
||||
/****************** Bit definition for ADC_JOFR1 register *******************/
|
||||
#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
|
||||
#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
|
||||
|
||||
/****************** Bit definition for ADC_JOFR2 register *******************/
|
||||
#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
|
||||
#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
|
||||
|
||||
/****************** Bit definition for ADC_JOFR3 register *******************/
|
||||
#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
|
||||
#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
|
||||
|
||||
/****************** Bit definition for ADC_JOFR4 register *******************/
|
||||
#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
|
||||
#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
|
||||
|
||||
/******************* Bit definition for ADC_HTR register ********************/
|
||||
#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
|
||||
#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
|
||||
|
||||
/******************* Bit definition for ADC_LTR register ********************/
|
||||
#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
|
||||
#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
|
||||
|
||||
/******************* Bit definition for ADC_SQR1 register *******************/
|
||||
#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
|
||||
|
|
@ -1212,25 +1209,25 @@ typedef struct
|
|||
#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
|
||||
#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
|
||||
/* COMPx bits definition */
|
||||
#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
|
||||
#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
|
||||
#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
|
||||
#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
|
||||
#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
|
||||
#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
|
||||
#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
|
||||
#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
|
||||
#define COMP_CSR_COMPxWNDWEN ((uint16_t)0x0080) /*!< COMPx window mode enable */
|
||||
#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
|
||||
#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
|
||||
#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
|
||||
#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
|
||||
#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
|
||||
#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
|
||||
#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
|
||||
#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x2000) /*!< COMPx hysteresis bit 1 */
|
||||
#define COMP_CSR_COMPxOUT ((uint32_t)0x4000) /*!< COMPx output level */
|
||||
#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
|
||||
#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
|
||||
#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
|
||||
#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
|
||||
#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
|
||||
#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
|
||||
#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
|
||||
#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
|
||||
#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
|
||||
#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000080) /*!< COMPx window mode enable */
|
||||
#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
|
||||
#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
|
||||
#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
|
||||
#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
|
||||
#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
|
||||
#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
|
||||
#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
|
||||
#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
|
||||
#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
|
||||
#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -2497,7 +2494,7 @@ typedef struct
|
|||
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
||||
|
||||
/******************* Bit definition for CRC_IDR register ********************/
|
||||
#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||||
|
||||
/******************** Bit definition for CRC_CR register ********************/
|
||||
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
|
||||
|
|
@ -2835,17 +2832,7 @@ typedef struct
|
|||
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
|
||||
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
|
||||
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
|
||||
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
|
||||
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
|
||||
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
||||
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
||||
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
||||
#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
|
||||
#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
|
||||
#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
|
||||
#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
|
||||
#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
|
||||
#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||||
|
|
@ -2866,17 +2853,7 @@ typedef struct
|
|||
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
|
||||
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
|
||||
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
|
||||
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
|
||||
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
|
||||
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
||||
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
||||
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
||||
#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
|
||||
#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
|
||||
#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
|
||||
#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
|
||||
#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
|
||||
#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||||
|
|
@ -2897,17 +2874,7 @@ typedef struct
|
|||
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
|
||||
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
|
||||
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
|
||||
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
|
||||
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
|
||||
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
||||
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
||||
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
||||
#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
|
||||
#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
|
||||
#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
|
||||
#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
|
||||
#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
|
||||
#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
|
||||
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
||||
|
|
@ -2928,18 +2895,7 @@ typedef struct
|
|||
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
|
||||
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
|
||||
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
|
||||
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
|
||||
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
|
||||
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
|
||||
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
|
||||
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
|
||||
#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
|
||||
#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
|
||||
#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
|
||||
#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
|
||||
#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
|
||||
#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* FLASH */
|
||||
|
|
@ -2994,13 +2950,18 @@ typedef struct
|
|||
#define FLASH_OBR_LEVEL2_PROT ((uint32_t)0x00000004) /*!< Level 2 Read protection status */
|
||||
|
||||
#define FLASH_OBR_USER ((uint32_t)0x0000F700) /*!< User Option Bytes */
|
||||
#define FLASH_OBR_WDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
|
||||
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
|
||||
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
|
||||
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
|
||||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
|
||||
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
|
||||
#define FLASH_OBR_SDADC12_VDD_MONITOR ((uint32_t)0x00008000) /*!< SDADC12_VDD_MONITOR */
|
||||
#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
|
||||
#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
|
||||
|
||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
||||
|
|
@ -3030,6 +2991,7 @@ typedef struct
|
|||
/****************** Bit definition for FLASH_WRP3 register ******************/
|
||||
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
|
||||
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* General Purpose I/O (GPIO) */
|
||||
|
|
@ -3344,7 +3306,7 @@ typedef struct
|
|||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||||
|
|
@ -3358,6 +3320,9 @@ typedef struct
|
|||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||||
|
||||
/* Legacy defines */
|
||||
#define I2C_CR1_DFN I2C_CR1_DNF
|
||||
|
||||
/****************** Bit definition for I2C_CR2 register ********************/
|
||||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||||
|
|
@ -3377,9 +3342,17 @@ typedef struct
|
|||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||||
|
||||
/******************* Bit definition for I2C_OAR2 register *******************/
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||||
#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
|
||||
#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
||||
#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
||||
#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
||||
#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
||||
#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
||||
#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
||||
#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
|
||||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||||
|
||||
/******************* Bit definition for I2C_TIMINGR register *****************/
|
||||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||||
|
|
@ -3850,7 +3823,6 @@ typedef struct
|
|||
/******************** Bit definition for RCC_CSR register *******************/
|
||||
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
|
||||
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
|
||||
#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
|
||||
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
|
||||
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
|
||||
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
|
||||
|
|
@ -3899,10 +3871,12 @@ typedef struct
|
|||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||||
/* Legacy defines */
|
||||
#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
|
||||
|
||||
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
|
||||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||||
|
|
@ -3922,7 +3896,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
|
||||
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
|
||||
|
|
@ -3931,7 +3905,7 @@ typedef struct
|
|||
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||||
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||||
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
|
||||
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
|
||||
|
|
@ -4349,7 +4323,7 @@ typedef struct
|
|||
#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
|
||||
|
||||
/******************** Number of backup registers ******************************/
|
||||
#define RTC_BKP_NUMBER ((uint32_t)0x00000020)
|
||||
#define RTC_BKP_NUMBER 32
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -4719,7 +4693,7 @@ typedef struct
|
|||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00008000) /*!< PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
|
||||
|
|
@ -4806,8 +4780,8 @@ typedef struct
|
|||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM15/16/17 */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM15/16/17 */
|
||||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
|
||||
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
|
||||
|
||||
/******************************************************************************/
|
||||
|
|
@ -4832,7 +4806,6 @@ typedef struct
|
|||
#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
|
||||
|
||||
/******************* Bit definition for TIM_CR2 register ********************/
|
||||
#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
|
||||
#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
|
||||
|
|
@ -5554,7 +5527,7 @@ typedef struct
|
|||
/****************************** DAC Instances *********************************/
|
||||
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
|
||||
((INSTANCE) == DAC2))
|
||||
|
||||
|
||||
#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
|
||||
((((INSTANCE) == DAC1) && \
|
||||
(((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
|
|
@ -5578,12 +5551,23 @@ typedef struct
|
|||
((INSTANCE) == DMA2_Channel5))
|
||||
|
||||
/****************************** GPIO Instances ********************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE) || \
|
||||
((INSTANCE) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOD))
|
||||
|
||||
/****************************** I2C Instances *********************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
||||
|
|
@ -5981,6 +5965,9 @@ typedef struct
|
|||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == USART3))
|
||||
|
||||
/******************** UART Instances : Support of continuous communication using DMA ****/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
|
||||
|
||||
/****************************** WWDG Instances ********************************/
|
||||
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
||||
|
||||
|
|
@ -5998,25 +5985,46 @@ typedef struct
|
|||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
|
||||
#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
|
||||
#define USBWakeUp_IRQn CEC_IRQn
|
||||
#define COMP1_2_IRQn COMP_IRQn
|
||||
#define COMP1_2_3_IRQn COMP_IRQn
|
||||
#define COMP2_IRQn COMP_IRQn
|
||||
#define ADC4_IRQn SDADC1_IRQn
|
||||
#define TIM8_BRK_IRQn TIM12_IRQn
|
||||
#define TIM8_UP_IRQn TIM13_IRQn
|
||||
#define TIM8_TRG_COM_IRQn TIM14_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM15_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM16_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM17_IRQn
|
||||
#define TIM1_CC_IRQn TIM18_DAC2_IRQn
|
||||
#define TIM20_UP_IRQn TIM19_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
|
||||
#define TIM7_DAC2_IRQn TIM7_IRQn
|
||||
|
||||
#define ADC1_2_IRQn ADC1_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM15_IRQn
|
||||
#define TIM1_UP_TIM16_IRQn TIM16_IRQn
|
||||
#define TIM1_TRG_COM_TIM17_IRQn TIM17_IRQn
|
||||
#define COMP2_IRQn COMP_IRQn
|
||||
#define COMP1_2_IRQn COMP_IRQn
|
||||
#define COMP1_2_3_IRQn COMP_IRQn
|
||||
#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM15_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM16_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM17_IRQHandler
|
||||
#define COMP2_IRQHandler COMP_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
|
||||
#define ADC1_2_IRQHandler ADC1_IRQHandler
|
||||
#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
|
||||
#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
|
||||
#define USBWakeUp_IRQHandler CEC_IRQHandler
|
||||
#define COMP1_2_IRQHandler COMP_IRQHandler
|
||||
#define COMP1_2_3_IRQHandler COMP_IRQHandler
|
||||
#define COMP2_IRQHandler COMP_IRQHandler
|
||||
#define ADC4_IRQHandler SDADC1_IRQHandler
|
||||
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
|
||||
#define TIM8_UP_IRQHandler TIM13_IRQHandler
|
||||
#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM15_IRQHandler
|
||||
#define TIM1_UP_TIM16_IRQHandler TIM16_IRQHandler
|
||||
#define TIM1_TRG_COM_TIM17_IRQHandler TIM17_IRQHandler
|
||||
#define TIM1_CC_IRQHandler TIM18_DAC2_IRQHandler
|
||||
#define TIM20_UP_IRQHandler TIM19_IRQHandler
|
||||
#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
|
||||
#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f3xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -18,7 +18,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -64,31 +64,47 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32F3)
|
||||
#define STM32F3
|
||||
#endif /* STM32F3 */
|
||||
|
||||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/
|
||||
|
||||
#if !defined (STM32F301x8) && !defined (STM32F318xx) && \
|
||||
!defined (STM32F302x8) && !defined (STM32F302xC) && \
|
||||
!defined (STM32F303x8) && \
|
||||
!defined (STM32F303xC) && !defined (STM32F358xx) && \
|
||||
!defined (STM32F373xC) && !defined (STM32F378xx) && \
|
||||
!defined (STM32F334x8) && !defined (STM32F328xx)
|
||||
#if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \
|
||||
!defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \
|
||||
!defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \
|
||||
!defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \
|
||||
!defined (STM32F373xC) && !defined (STM32F378xx)
|
||||
|
||||
/* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8,
|
||||
STM32F301R6 and STM32F301R8 Devices */
|
||||
/* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8,
|
||||
STM32F302R6 and STM32F302R8 Devices */
|
||||
/* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB and STM32F302VC Devices */
|
||||
/* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC,
|
||||
STM32F302VB and STM32F302VC Devices */
|
||||
/* #define STM32F302xE */ /*!< STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD,
|
||||
STM32F302VD and STM32F302ZD Devices */
|
||||
/* #define STM32F303x8 */ /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8,
|
||||
STM32F303R6 and STM32F303R8 Devices */
|
||||
/* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */
|
||||
/* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC, STM32F373R8, STM32F373RB, STM32F373RC,
|
||||
/* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC,
|
||||
STM32F303VB and STM32F303VC Devices */
|
||||
/* #define STM32F303xE */ /*!< STM32F303RE, STM32F303VE, STM32F303ZE, STM32F303RD,
|
||||
STM32F303VD and STM32F303ZD Devices */
|
||||
/* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC,
|
||||
STM32F373R8, STM32F373RB, STM32F373RC,
|
||||
STM32F373V8, STM32F373VB and STM32F373VC Devices */
|
||||
/* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
|
||||
/* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8,
|
||||
STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
|
||||
/* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */
|
||||
/* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */
|
||||
/* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */
|
||||
/* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */
|
||||
/* #define STM32F398xx */ /*!< STM32F398CE, STM32F398RE, STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
|
|
@ -104,11 +120,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.0.1
|
||||
* @brief CMSIS Device version number V2.2.0
|
||||
*/
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F3xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|
||||
|
|
@ -129,10 +145,14 @@
|
|||
#include "stm32f302x8.h"
|
||||
#elif defined(STM32F302xC)
|
||||
#include "stm32f302xc.h"
|
||||
#elif defined(STM32F302xE)
|
||||
#include "stm32f302xe.h"
|
||||
#elif defined(STM32F303x8)
|
||||
#include "stm32f303x8.h"
|
||||
#elif defined(STM32F303xC)
|
||||
#include "stm32f303xc.h"
|
||||
#elif defined(STM32F303xE)
|
||||
#include "stm32f303xe.h"
|
||||
#elif defined(STM32F373xC)
|
||||
#include "stm32f373xc.h"
|
||||
#elif defined(STM32F334x8)
|
||||
|
|
@ -145,6 +165,8 @@
|
|||
#include "stm32f358xx.h"
|
||||
#elif defined(STM32F378xx)
|
||||
#include "stm32f378xx.h"
|
||||
#elif defined(STM32F398xx)
|
||||
#include "stm32f398xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f3xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.1
|
||||
* @date 18-June-2014
|
||||
* @version V2.2.0
|
||||
* @date 13-November-2015
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -29,12 +29,15 @@
|
|||
* - STM32F301x8 for Analog & DSP devices.
|
||||
* - STM32F302x8 for Analog & DSP devices.
|
||||
* - STM32F302xC for Analog & DSP devices.
|
||||
* - STM32F302xE for Analog & DSP devices.
|
||||
* - STM32F303x8 for Analog & DSP devices.
|
||||
* - STM32F303xC for Analog & DSP devices.
|
||||
* - STM32F303xE for Analog & DSP devices.
|
||||
* - STM32F318xx for Analog & DSP devices.
|
||||
* - STM32F328xx for Analog & DSP devices.
|
||||
* - STM32F334x8 for Analog & DSP devices.
|
||||
* - STM32F358xx for Analog & DSP devices.
|
||||
* - STM32F398xx for Analog & DSP devices.
|
||||
* .
|
||||
*
|
||||
* @addtogroup HAL
|
||||
|
|
|
|||
|
|
@ -59,6 +59,11 @@
|
|||
#define STM32_I2C2_EVENT_NUMBER 33
|
||||
#define STM32_I2C2_ERROR_NUMBER 34
|
||||
|
||||
#define STM32_I2C3_EVENT_HANDLER Vector160
|
||||
#define STM32_I2C3_ERROR_HANDLER Vector164
|
||||
#define STM32_I2C3_EVENT_NUMBER 72
|
||||
#define STM32_I2C3_ERROR_NUMBER 73
|
||||
|
||||
/*
|
||||
* TIM units.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -208,11 +208,11 @@
|
|||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
|
|
@ -277,6 +277,256 @@
|
|||
#define STM32_CRC_PROGRAMMABLE TRUE
|
||||
#endif /* defined(STM32F303xC) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32F303xE. */
|
||||
/*===========================================================================*/
|
||||
#if defined(STM32F303xE)
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_HAS_ADC3 TRUE
|
||||
#define STM32_HAS_ADC4 TRUE
|
||||
|
||||
#define STM32_HAS_SDADC1 FALSE
|
||||
#define STM32_HAS_SDADC2 FALSE
|
||||
#define STM32_HAS_SDADC3 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
#define STM32_CAN_MAX_FILTERS 14
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC1_CH1 TRUE
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
|
||||
#define STM32_HAS_DAC1_CH2 TRUE
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||||
|
||||
#define STM32_HAS_DAC2_CH1 FALSE
|
||||
#define STM32_HAS_DAC2_CH2 FALSE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
||||
|
||||
#define STM32_DMA1_NUM_CHANNELS 7
|
||||
#define STM32_DMA1_CH1_HANDLER Vector6C
|
||||
#define STM32_DMA1_CH2_HANDLER Vector70
|
||||
#define STM32_DMA1_CH3_HANDLER Vector74
|
||||
#define STM32_DMA1_CH4_HANDLER Vector78
|
||||
#define STM32_DMA1_CH5_HANDLER Vector7C
|
||||
#define STM32_DMA1_CH6_HANDLER Vector80
|
||||
#define STM32_DMA1_CH7_HANDLER Vector84
|
||||
#define STM32_DMA1_CH1_NUMBER 11
|
||||
#define STM32_DMA1_CH2_NUMBER 12
|
||||
#define STM32_DMA1_CH3_NUMBER 13
|
||||
#define STM32_DMA1_CH4_NUMBER 14
|
||||
#define STM32_DMA1_CH5_NUMBER 15
|
||||
#define STM32_DMA1_CH6_NUMBER 16
|
||||
#define STM32_DMA1_CH7_NUMBER 17
|
||||
|
||||
#define STM32_DMA2_NUM_CHANNELS 5
|
||||
#define STM32_DMA2_CH1_HANDLER Vector120
|
||||
#define STM32_DMA2_CH2_HANDLER Vector124
|
||||
#define STM32_DMA2_CH3_HANDLER Vector128
|
||||
#define STM32_DMA2_CH4_HANDLER Vector12C
|
||||
#define STM32_DMA2_CH5_HANDLER Vector130
|
||||
#define STM32_DMA2_CH1_NUMBER 56
|
||||
#define STM32_DMA2_CH2_NUMBER 57
|
||||
#define STM32_DMA2_CH3_NUMBER 58
|
||||
#define STM32_DMA2_CH4_NUMBER 59
|
||||
#define STM32_DMA2_CH5_NUMBER 60
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_LINES 34
|
||||
#define STM32_EXTI_IMR_MASK 0x1F800000U
|
||||
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG TRUE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_HAS_GPIOJ FALSE
|
||||
#define STM32_HAS_GPIOK FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
||||
RCC_AHBENR_GPIOBEN | \
|
||||
RCC_AHBENR_GPIOCEN | \
|
||||
RCC_AHBENR_GPIODEN | \
|
||||
RCC_AHBENR_GPIOEEN | \
|
||||
RCC_AHBENR_GPIOFEN | \
|
||||
RCC_AHBENR_GPIOGEN | \
|
||||
RCC_AHBENR_GPIOHEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
|
||||
#define STM32_HAS_I2C3 TRUE
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
|
||||
#define STM32_HAS_I2C4 FALSE
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
||||
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
||||
#define STM32_RTC_NUM_ALARMS 2
|
||||
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
||||
|
||||
/* SDIO attributes.*/
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_SUPPORTS_I2S TRUE
|
||||
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
#define STM32_SPI3_SUPPORTS_I2S TRUE
|
||||
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
|
||||
#define STM32_HAS_SPI4 TRUE
|
||||
#define STM32_SPI4_SUPPORTS_I2S FALSE
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_TIM_MAX_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_TIM1_IS_32BITS FALSE
|
||||
#define STM32_TIM1_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_TIM2_IS_32BITS TRUE
|
||||
#define STM32_TIM2_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_TIM3_IS_32BITS FALSE
|
||||
#define STM32_TIM3_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_TIM4_IS_32BITS FALSE
|
||||
#define STM32_TIM4_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_TIM6_IS_32BITS FALSE
|
||||
#define STM32_TIM6_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_TIM7_IS_32BITS FALSE
|
||||
#define STM32_TIM7_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM8 TRUE
|
||||
#define STM32_TIM8_IS_32BITS FALSE
|
||||
#define STM32_TIM8_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_TIM15_IS_32BITS FALSE
|
||||
#define STM32_TIM15_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM20 TRUE
|
||||
#define STM32_TIM20_IS_32BITS FALSE
|
||||
#define STM32_TIM20_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
#define STM32_HAS_TIM21 FALSE
|
||||
#define STM32_HAS_TIM22 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
|
||||
#define STM32_HAS_UART5 TRUE
|
||||
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_HAS_UART7 FALSE
|
||||
#define STM32_HAS_UART8 FALSE
|
||||
#define STM32_HAS_LPUART1 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
|
||||
#define STM32_USB_PMA_SIZE 768
|
||||
#define STM32_USB_HAS_BCDR FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* IWDG attributes.*/
|
||||
#define STM32_HAS_IWDG TRUE
|
||||
#define STM32_IWDG_IS_WINDOWED TRUE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define STM32_HAS_CRC TRUE
|
||||
#define STM32_CRC_PROGRAMMABLE TRUE
|
||||
#endif /* defined(STM32F303xE) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32F303x8. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -420,11 +670,11 @@
|
|||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
|
|
@ -622,11 +872,11 @@
|
|||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM3 FALSE
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
|
|
@ -827,11 +1077,11 @@
|
|||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM3 FALSE
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
|
|
@ -1055,11 +1305,11 @@
|
|||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
|
|
@ -1126,6 +1376,245 @@
|
|||
#define STM32_CRC_PROGRAMMABLE TRUE
|
||||
#endif /* defined(STM32F302xC) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32F302xE. */
|
||||
/*===========================================================================*/
|
||||
#if defined(STM32F302xE)
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
#define STM32_HAS_ADC4 FALSE
|
||||
|
||||
#define STM32_HAS_SDADC1 FALSE
|
||||
#define STM32_HAS_SDADC2 FALSE
|
||||
#define STM32_HAS_SDADC3 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
#define STM32_CAN_MAX_FILTERS 14
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC1_CH1 TRUE
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
|
||||
#define STM32_HAS_DAC1_CH2 FALSE
|
||||
#define STM32_HAS_DAC2_CH1 FALSE
|
||||
#define STM32_HAS_DAC2_CH2 FALSE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
||||
|
||||
#define STM32_DMA1_NUM_CHANNELS 7
|
||||
#define STM32_DMA1_CH1_HANDLER Vector6C
|
||||
#define STM32_DMA1_CH2_HANDLER Vector70
|
||||
#define STM32_DMA1_CH3_HANDLER Vector74
|
||||
#define STM32_DMA1_CH4_HANDLER Vector78
|
||||
#define STM32_DMA1_CH5_HANDLER Vector7C
|
||||
#define STM32_DMA1_CH6_HANDLER Vector80
|
||||
#define STM32_DMA1_CH7_HANDLER Vector84
|
||||
#define STM32_DMA1_CH1_NUMBER 11
|
||||
#define STM32_DMA1_CH2_NUMBER 12
|
||||
#define STM32_DMA1_CH3_NUMBER 13
|
||||
#define STM32_DMA1_CH4_NUMBER 14
|
||||
#define STM32_DMA1_CH5_NUMBER 15
|
||||
#define STM32_DMA1_CH6_NUMBER 16
|
||||
#define STM32_DMA1_CH7_NUMBER 17
|
||||
|
||||
#define STM32_DMA2_NUM_CHANNELS 5
|
||||
#define STM32_DMA2_CH1_HANDLER Vector120
|
||||
#define STM32_DMA2_CH2_HANDLER Vector124
|
||||
#define STM32_DMA2_CH3_HANDLER Vector128
|
||||
#define STM32_DMA2_CH4_HANDLER Vector12C
|
||||
#define STM32_DMA2_CH5_HANDLER Vector130
|
||||
#define STM32_DMA2_CH1_NUMBER 56
|
||||
#define STM32_DMA2_CH2_NUMBER 57
|
||||
#define STM32_DMA2_CH3_NUMBER 58
|
||||
#define STM32_DMA2_CH4_NUMBER 59
|
||||
#define STM32_DMA2_CH5_NUMBER 60
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_LINES 34
|
||||
#define STM32_EXTI_IMR_MASK 0x1F800000U
|
||||
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG TRUE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_HAS_GPIOJ FALSE
|
||||
#define STM32_HAS_GPIOK FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
||||
RCC_AHBENR_GPIOBEN | \
|
||||
RCC_AHBENR_GPIOCEN | \
|
||||
RCC_AHBENR_GPIODEN | \
|
||||
RCC_AHBENR_GPIOEEN | \
|
||||
RCC_AHBENR_GPIOFEN | \
|
||||
RCC_AHBENR_GPIOGEN | \
|
||||
RCC_AHBENR_GPIOHEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
|
||||
#define STM32_HAS_I2C3 TRUE
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
|
||||
#define STM32_HAS_I2C4 FALSE
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
||||
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
||||
#define STM32_RTC_NUM_ALARMS 2
|
||||
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
||||
|
||||
/* SDIO attributes.*/
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_SUPPORTS_I2S TRUE
|
||||
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
#define STM32_SPI3_SUPPORTS_I2S TRUE
|
||||
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
|
||||
#define STM32_HAS_SPI4 TRUE
|
||||
#define STM32_SPI4_SUPPORTS_I2S FALSE
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_TIM_MAX_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_TIM1_IS_32BITS FALSE
|
||||
#define STM32_TIM1_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_TIM2_IS_32BITS TRUE
|
||||
#define STM32_TIM2_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_TIM3_IS_32BITS FALSE
|
||||
#define STM32_TIM3_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_TIM4_IS_32BITS FALSE
|
||||
#define STM32_TIM4_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_TIM6_IS_32BITS FALSE
|
||||
#define STM32_TIM6_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_TIM15_IS_32BITS FALSE
|
||||
#define STM32_TIM15_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
#define STM32_HAS_TIM20 FALSE
|
||||
#define STM32_HAS_TIM21 FALSE
|
||||
#define STM32_HAS_TIM22 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
|
||||
#define STM32_HAS_UART5 TRUE
|
||||
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_HAS_UART7 FALSE
|
||||
#define STM32_HAS_UART8 FALSE
|
||||
#define STM32_HAS_LPUART1 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
|
||||
#define STM32_USB_PMA_SIZE 768
|
||||
#define STM32_USB_HAS_BCDR FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* IWDG attributes.*/
|
||||
#define STM32_HAS_IWDG TRUE
|
||||
#define STM32_IWDG_IS_WINDOWED TRUE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define STM32_HAS_CRC TRUE
|
||||
#define STM32_CRC_PROGRAMMABLE TRUE
|
||||
#endif /* defined(STM32F302xE) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32F318x8. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -1264,11 +1753,11 @@
|
|||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM3 FALSE
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
|
|
@ -1469,11 +1958,11 @@
|
|||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
|
|
@ -1536,7 +2025,7 @@
|
|||
/*===========================================================================*/
|
||||
/* STM32F358xC. */
|
||||
/*===========================================================================*/
|
||||
#if defined(STM32F358xC) || defined(__DOXYGEN__)
|
||||
#if defined(STM32F358xC)
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
|
|
@ -1694,11 +2183,11 @@
|
|||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
|
|
@ -1768,7 +2257,7 @@
|
|||
/*===========================================================================*/
|
||||
/* STM32F334x8. */
|
||||
/*===========================================================================*/
|
||||
#if defined(STM32F334x8) || defined(__DOXYGEN__)
|
||||
#if defined(STM32F334x8)
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
|
|
@ -1904,11 +2393,11 @@
|
|||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
|
|
@ -1968,6 +2457,254 @@
|
|||
#define STM32_CRC_PROGRAMMABLE TRUE
|
||||
#endif /* defined(STM32F334x8) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32F398xx. */
|
||||
/*===========================================================================*/
|
||||
#if defined(STM32F398xx)
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_HAS_ADC3 TRUE
|
||||
#define STM32_HAS_ADC4 TRUE
|
||||
|
||||
#define STM32_HAS_SDADC1 FALSE
|
||||
#define STM32_HAS_SDADC2 FALSE
|
||||
#define STM32_HAS_SDADC3 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
#define STM32_CAN_MAX_FILTERS 14
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC1_CH1 TRUE
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
|
||||
#define STM32_HAS_DAC1_CH2 TRUE
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||||
|
||||
#define STM32_HAS_DAC2_CH1 FALSE
|
||||
#define STM32_HAS_DAC2_CH2 FALSE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
||||
|
||||
#define STM32_DMA1_NUM_CHANNELS 7
|
||||
#define STM32_DMA1_CH1_HANDLER Vector6C
|
||||
#define STM32_DMA1_CH2_HANDLER Vector70
|
||||
#define STM32_DMA1_CH3_HANDLER Vector74
|
||||
#define STM32_DMA1_CH4_HANDLER Vector78
|
||||
#define STM32_DMA1_CH5_HANDLER Vector7C
|
||||
#define STM32_DMA1_CH6_HANDLER Vector80
|
||||
#define STM32_DMA1_CH7_HANDLER Vector84
|
||||
#define STM32_DMA1_CH1_NUMBER 11
|
||||
#define STM32_DMA1_CH2_NUMBER 12
|
||||
#define STM32_DMA1_CH3_NUMBER 13
|
||||
#define STM32_DMA1_CH4_NUMBER 14
|
||||
#define STM32_DMA1_CH5_NUMBER 15
|
||||
#define STM32_DMA1_CH6_NUMBER 16
|
||||
#define STM32_DMA1_CH7_NUMBER 17
|
||||
|
||||
#define STM32_DMA2_NUM_CHANNELS 5
|
||||
#define STM32_DMA2_CH1_HANDLER Vector120
|
||||
#define STM32_DMA2_CH2_HANDLER Vector124
|
||||
#define STM32_DMA2_CH3_HANDLER Vector128
|
||||
#define STM32_DMA2_CH4_HANDLER Vector12C
|
||||
#define STM32_DMA2_CH5_HANDLER Vector130
|
||||
#define STM32_DMA2_CH1_NUMBER 56
|
||||
#define STM32_DMA2_CH2_NUMBER 57
|
||||
#define STM32_DMA2_CH3_NUMBER 58
|
||||
#define STM32_DMA2_CH4_NUMBER 59
|
||||
#define STM32_DMA2_CH5_NUMBER 60
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_LINES 34
|
||||
#define STM32_EXTI_IMR_MASK 0x1F800000U
|
||||
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG TRUE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_HAS_GPIOJ FALSE
|
||||
#define STM32_HAS_GPIOK FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
||||
RCC_AHBENR_GPIOBEN | \
|
||||
RCC_AHBENR_GPIOCEN | \
|
||||
RCC_AHBENR_GPIODEN | \
|
||||
RCC_AHBENR_GPIOEEN | \
|
||||
RCC_AHBENR_GPIOFEN | \
|
||||
RCC_AHBENR_GPIOGEN | \
|
||||
RCC_AHBENR_GPIOHEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
|
||||
#define STM32_HAS_I2C3 TRUE
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
|
||||
#define STM32_HAS_I2C4 FALSE
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
||||
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
||||
#define STM32_RTC_NUM_ALARMS 2
|
||||
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
||||
|
||||
/* SDIO attributes.*/
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_SUPPORTS_I2S TRUE
|
||||
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
#define STM32_SPI3_SUPPORTS_I2S TRUE
|
||||
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
|
||||
#define STM32_HAS_SPI4 TRUE
|
||||
#define STM32_SPI4_SUPPORTS_I2S FALSE
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_TIM_MAX_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_TIM1_IS_32BITS FALSE
|
||||
#define STM32_TIM1_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_TIM2_IS_32BITS TRUE
|
||||
#define STM32_TIM2_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_TIM3_IS_32BITS FALSE
|
||||
#define STM32_TIM3_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_TIM4_IS_32BITS FALSE
|
||||
#define STM32_TIM4_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_TIM6_IS_32BITS FALSE
|
||||
#define STM32_TIM6_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_TIM7_IS_32BITS FALSE
|
||||
#define STM32_TIM7_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM8 TRUE
|
||||
#define STM32_TIM8_IS_32BITS FALSE
|
||||
#define STM32_TIM8_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_TIM15_IS_32BITS FALSE
|
||||
#define STM32_TIM15_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM20 TRUE
|
||||
#define STM32_TIM20_IS_32BITS FALSE
|
||||
#define STM32_TIM20_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
#define STM32_HAS_TIM21 FALSE
|
||||
#define STM32_HAS_TIM22 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
|
||||
#define STM32_HAS_UART5 TRUE
|
||||
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_HAS_UART7 FALSE
|
||||
#define STM32_HAS_UART8 FALSE
|
||||
#define STM32_HAS_LPUART1 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* IWDG attributes.*/
|
||||
#define STM32_HAS_IWDG TRUE
|
||||
#define STM32_IWDG_IS_WINDOWED TRUE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC TRUE
|
||||
#define STM32_FSMC_IS_FMC FALSE
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define STM32_HAS_CRC TRUE
|
||||
#define STM32_CRC_PROGRAMMABLE TRUE
|
||||
#endif /* defined(STM32F398xx) */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* _STM32_REGISTRY_H_ */
|
||||
|
|
|
|||
|
|
@ -746,6 +746,7 @@
|
|||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC TRUE
|
||||
#define STM32_FSMC_IS_FMC FALSE
|
||||
#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
||||
|
|
|
|||
|
|
@ -85,6 +85,7 @@
|
|||
- HAL: Added "lines" handling to PAL driver, lines are identifiers of both
|
||||
ports and pins encoded in a single value. Added a set of macros
|
||||
operating on lines.
|
||||
- HAL: Merged the latest STM32F3xx CMSIS headers.
|
||||
- HAL: Merged the latest STM32F2xx CMSIS headers and fixed the support
|
||||
broken in 3.0.x.
|
||||
- RT: Added new function chVTGetTimersStateI() returning the state of the
|
||||
|
|
|
|||
Loading…
Reference in New Issue