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WDG driver works, update of all registries, halconf.h and mcuconf.h to be performed. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8557 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
Giovanni Di Sirio 2015-12-03 14:44:18 +00:00
parent c39cfd28fd
commit c1e7f8c6c7
3 changed files with 18 additions and 4 deletions
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16
os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c
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@ -81,19 +81,33 @@ void wdg_lld_init(void) {
*/ */
void wdg_lld_start(WDGDriver *wdgp) { void wdg_lld_start(WDGDriver *wdgp) {
#if 1
/* Enable IWDG and unlock for write.*/
wdgp->wdg->KR = KR_KEY_ENABLE;
wdgp->wdg->KR = KR_KEY_WRITE;
/* Write configuration.*/
wdgp->wdg->PR = wdgp->config->pr;
wdgp->wdg->RLR = wdgp->config->rlr;
while (wdgp->wdg->SR != 0)
;
/* This also triggers a refresh.*/
wdgp->wdg->WINR = wdgp->config->winr;
#else
/* Unlock IWDG.*/ /* Unlock IWDG.*/
wdgp->wdg->KR = KR_KEY_WRITE; wdgp->wdg->KR = KR_KEY_WRITE;
/* Write configuration.*/ /* Write configuration.*/
wdgp->wdg->PR = wdgp->config->pr; wdgp->wdg->PR = wdgp->config->pr;
wdgp->wdg->RLR = wdgp->config->rlr; wdgp->wdg->RLR = wdgp->config->rlr;
wdgp->wdg->WINR = wdgp->config->winr;
while (wdgp->wdg->SR != 0) while (wdgp->wdg->SR != 0)
; ;
/* Start operations.*/ /* Start operations.*/
wdgp->wdg->KR = KR_KEY_RELOAD; wdgp->wdg->KR = KR_KEY_RELOAD;
wdgp->wdg->KR = KR_KEY_ENABLE; wdgp->wdg->KR = KR_KEY_ENABLE;
#endif
} }
/** /**

2
testhal/STM32/STM32F3xx/WDG/Makefile
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@ -5,7 +5,7 @@
# Compiler options here. # Compiler options here.
ifeq ($(USE_OPT),) ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
endif endif
# C specific options here (added to USE_OPT). # C specific options here (added to USE_OPT).

4
testhal/STM32/STM32F3xx/WDG/main.c
View File

@ -18,10 +18,10 @@
#include "hal.h" #include "hal.h"
/* /*
* Watchdog deadline set to one second (LSI=40000 / 4 / 1000). * Watchdog deadline set to more than one second (LSI=40000 / (64 * 1000)).
*/ */
static const WDGConfig wdgcfg = { static const WDGConfig wdgcfg = {
STM32_IWDG_PR_4, STM32_IWDG_PR_64,
STM32_IWDG_RL(1000), STM32_IWDG_RL(1000),
STM32_IWDG_WIN_DISABLED STM32_IWDG_WIN_DISABLED
}; };