Add LPC17xx MAC driver and LWIP demo for LPC1769 LPCXpresso.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6738 35acf78f-673a-0410-8e92-d51de3d6d3f4master
theshed
parent
3565edd4cd
commit
c0aab7fd96
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@ -32,6 +32,26 @@ const PALConfig pal_default_config = {
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};
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#endif
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/*
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* Board Ethernet pins configuration.
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* ENET_REF_CLK pin must be set before macInit().
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*/
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static void board_eth_pin_config(void) {
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/* Ethernet pin config */
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LPC_PINCON->PINSEL2 |= (1UL << 30) | (1UL << 28) | (1UL << 20) | (1UL << 18) \
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| (1UL << 16) | (1UL << 8) | (1UL << 2) | (1UL << 0); /* Set Ethernet ENET_REF_CLK P1.15, ENET_RX_ER P1.14,
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ENET_RXD1 P1.10, ENET_RXD0 P1.9, ENET_CRS P1.8, ENET_TX_EN P1.4,
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ENET_TXD1 P1.1, ENET_TXD0 P1.0 pins. */
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LPC_PINCON->PINMODE2 |= (2UL << 30) | (2UL << 28) | (2UL << 20) | (2UL << 18) \
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| (2UL << 16) | (2UL << 8) | (2UL << 2) | (2UL << 0); /* Disable pull-up on ENET_REF_CLK P1.15, ENET_RX_ER P1.14,
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ENET_RXD1 P1.10, ENET_RXD0 P1.9, ENET_CRS P1.8, ENET_TX_EN P1.4,
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ENET_TXD1 P1.1, ENET_TXD0 P1.0 pins. */
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LPC_PINCON->PINSEL3 |= (1UL << 2) | (1UL << 0); /* Set ENET_MDIO P1.17, ENET_MDC P1.16 */
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LPC_PINCON->PINMODE3 |= (2UL << 2) | (2UL << 0); /* Disable pull-up on ENET_MDIO P1.17, ENET_MDC P1.16 */
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}
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/*
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* Early initialization code.
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* This initialization must be performed just after stack setup and before
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@ -40,6 +60,9 @@ const PALConfig pal_default_config = {
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void __early_init(void) {
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LPC17xx_clock_init();
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#if HAL_USE_MAC
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board_eth_pin_config();
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#endif
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}
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/*
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@ -50,19 +73,19 @@ void boardInit(void) {
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/*
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* Extra, board-specific, initializations.
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*/
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/* UART0 pin config */
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LPC_PINCON->PINSEL0 |= (1UL << 4) | (1UL << 6); /* Set UART0 TXD0 P0.2 and RXD0 P0.3 pins.*/
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LPC_PINCON->PINMODE0 |= (2UL << 4) | (2UL << 6); /* Disable pull-up on UART0 TXD0 and RXD0 pins.*/
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LPC_PINCON->PINSEL3 |= (1UL << 22); /* Set CLKOUT P1.27 pin.*/
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LPC_PINCON->PINMODE3 |= (2UL << 22); /* Disable pull-up on CLKOUT pin. */
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/* CLKOUT pin config */
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/* LPC_PINCON->PINSEL3 |= (1UL << 22); */ /* Set CLKOUT P1.27 pin.*/
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/* LPC_PINCON->PINMODE3 |= (2UL << 22); */ /* Disable pull-up on CLKOUT pin. */
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/* I2C1 config */
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/* I2C1 pin config */
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LPC_PINCON->PINSEL1 |= (3UL << 8) | (3UL << 6); /* Set I2C1 SCL1 P0.20, SDA1 P0.19 pins. */
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LPC_PINCON->PINMODE1 |= (2UL << 8) | (2UL << 6); /* Disable pull-up on I2C1 SCL1 P0.20, SDA1 P0.19 pins. */
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LPC_PINCON->PINMODE_OD0 |= (1UL << 20) | (1UL << 19); /* Set I2C1 SCL1 P0.20, SDA1 P0.19 as open drain pins. */
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/* ADC config */
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LPC_PINCON->PINMODE1 |= (2UL << 16) | (2UL << 14); /* Disable pull-up on AD0.1 P0.24 and AD0.0 P0.23 pins.*/
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LPC_PINCON->PINSEL1 |= (1UL << 16) | (1UL << 14); /* Set AD0.1 P0.24 and AD0.0 P0.23 pins.*/
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/* DAC pin config */
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/* DAC pin set in dac_lld_start() */
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}
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@ -76,7 +76,7 @@
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*/
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#define GPIO0_LED2_RED 22
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#define GPIO2_SW_TO_GND 12
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#define GPIO2_PIN12_TO_GND 12
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#if !defined(_FROM_ASM_)
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#ifdef __cplusplus
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@ -0,0 +1,198 @@
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##############################################################################
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# Build global options
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# NOTE: Can be overridden externally.
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#
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# Compiler options here.
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ifeq ($(USE_OPT),)
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USE_OPT = -O2 -ggdb -fomit-frame-pointer
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endif
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# C specific options here (added to USE_OPT).
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ifeq ($(USE_COPT),)
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USE_COPT =
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endif
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# C++ specific options here (added to USE_OPT).
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ifeq ($(USE_CPPOPT),)
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USE_CPPOPT = -fno-rtti
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endif
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# Enable this if you want the linker to remove unused code and data
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ifeq ($(USE_LINK_GC),)
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USE_LINK_GC = yes
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endif
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# If enabled, this option allows to compile the application in THUMB mode.
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ifeq ($(USE_THUMB),)
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USE_THUMB = yes
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endif
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# Enable this if you want to see the full log while compiling.
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ifeq ($(USE_VERBOSE_COMPILE),)
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USE_VERBOSE_COMPILE = no
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endif
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#
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# Build global options
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##############################################################################
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##############################################################################
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# Architecture or project specific options
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#
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#
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# Architecture or project specific options
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##############################################################################
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##############################################################################
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# Project, sources and paths
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#
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# Define project name here
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PROJECT = ch
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# Imported source files and paths
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CHIBIOS = ../..
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include $(CHIBIOS)/boards/EA_LPCXPRESSO_LPC1769/board.mk
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include $(CHIBIOS)/os/hal/platforms/LPC17xx/platform.mk
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include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC17xx/port.mk
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include $(CHIBIOS)/os/kernel/kernel.mk
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include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk
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include $(CHIBIOS)/test/test.mk
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# Define linker script file here
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LDSCRIPT= $(PORTLD)/LPC1769.ld
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# C sources that can be compiled in ARM or THUMB mode depending on the global
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# setting.
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CSRC = $(PORTSRC) \
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$(KERNSRC) \
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$(TESTSRC) \
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$(HALSRC) \
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$(PLATFORMSRC) \
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$(BOARDSRC) \
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$(LWSRC) \
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$(CHIBIOS)/os/various/evtimer.c \
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web/web.c main.c
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# C++ sources that can be compiled in ARM or THUMB mode depending on the global
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# setting.
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CPPSRC =
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# C sources to be compiled in ARM mode regardless of the global setting.
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# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
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# option that results in lower performance and larger code size.
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ACSRC =
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# C++ sources to be compiled in ARM mode regardless of the global setting.
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# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
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# option that results in lower performance and larger code size.
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ACPPSRC =
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# C sources to be compiled in THUMB mode regardless of the global setting.
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# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
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# option that results in lower performance and larger code size.
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TCSRC =
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# C sources to be compiled in THUMB mode regardless of the global setting.
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# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
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# option that results in lower performance and larger code size.
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TCPPSRC =
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# List ASM source files here
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ASMSRC = $(PORTASM)
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INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
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$(HALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \
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$(CHIBIOS)/os/various
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#
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# Project, sources and paths
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##############################################################################
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##############################################################################
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# Compiler settings
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#
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MCU = cortex-m3
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#TRGT = arm-elf-
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TRGT = arm-none-eabi-
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CC = $(TRGT)gcc
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CPPC = $(TRGT)g++
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# Enable loading with g++ only if you need C++ runtime support.
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# NOTE: You can use C++ even without C++ support if you are careful. C++
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# runtime support makes code size explode.
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LD = $(TRGT)gcc
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#LD = $(TRGT)g++
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CP = $(TRGT)objcopy
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AS = $(TRGT)gcc -x assembler-with-cpp
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OD = $(TRGT)objdump
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HEX = $(CP) -O ihex
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BIN = $(CP) -O binary
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# ARM-specific options here
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AOPT =
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# THUMB-specific options here
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TOPT = -mthumb -DTHUMB
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# Define C warning options here
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CWARN = -Wall -Wextra -Wstrict-prototypes
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# Define C++ warning options here
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CPPWARN = -Wall -Wextra
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#
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# Compiler settings
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##############################################################################
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##############################################################################
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# Start of default section
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#
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# List all default C defines here, like -D_DEBUG=1
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DDEFS = -DLPC17XX -D__NEWLIB__
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# List all default ASM defines here, like -D_DEBUG=1
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DADEFS =
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# List all default directories to look for include files here
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DINCDIR =
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# List the default directory to look for the libraries here
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DLIBDIR =
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# List all default libraries here
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DLIBS =
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#
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# End of default section
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##############################################################################
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##############################################################################
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# Start of user section
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#
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# List all user C define here, like -D_DEBUG=1
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UDEFS =
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# Define ASM defines here
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UADEFS =
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# List all user directories here
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UINCDIR =
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# List the user directory to look for the libraries here
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ULIBDIR =
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# List all user libraries here
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ULIBS =
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#
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# End of user defines
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##############################################################################
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include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk
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@ -0,0 +1,531 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file templates/chconf.h
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* @brief Configuration file template.
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* @details A copy of this file must be placed in each project directory, it
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* contains the application specific kernel settings.
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*
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* @addtogroup config
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* @details Kernel related settings and hooks.
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* @{
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*/
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#ifndef _CHCONF_H_
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#define _CHCONF_H_
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/*===========================================================================*/
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/**
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* @name Kernel parameters and options
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* @{
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*/
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/*===========================================================================*/
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/**
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* @brief System tick frequency.
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* @details Frequency of the system timer that drives the system ticks. This
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* setting also defines the system tick time unit.
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*/
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#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
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#define CH_FREQUENCY 1000
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#endif
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/**
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* @brief Round robin interval.
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* @details This constant is the number of system ticks allowed for the
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* threads before preemption occurs. Setting this value to zero
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* disables the preemption for threads with equal priority and the
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* round robin becomes cooperative. Note that higher priority
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* threads can still preempt, the kernel is always preemptive.
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*
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* @note Disabling the round robin preemption makes the kernel more compact
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* and generally faster.
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*/
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#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
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#define CH_TIME_QUANTUM 20
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#endif
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/**
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* @brief Managed RAM size.
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* @details Size of the RAM area to be managed by the OS. If set to zero
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* then the whole available RAM is used. The core memory is made
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* available to the heap allocator and/or can be used directly through
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* the simplified core memory allocator.
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*
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* @note In order to let the OS manage the whole RAM the linker script must
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* provide the @p __heap_base__ and @p __heap_end__ symbols.
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* @note Requires @p CH_USE_MEMCORE.
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*/
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#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
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#define CH_MEMCORE_SIZE 0
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#endif
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/**
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* @brief Idle thread automatic spawn suppression.
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* @details When this option is activated the function @p chSysInit()
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* does not spawn the idle thread automatically. The application has
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* then the responsibility to do one of the following:
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* - Spawn a custom idle thread at priority @p IDLEPRIO.
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* - Change the main() thread priority to @p IDLEPRIO then enter
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* an endless loop. In this scenario the @p main() thread acts as
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* the idle thread.
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* .
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* @note Unless an idle thread is spawned the @p main() thread must not
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* enter a sleep state.
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*/
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#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
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#define CH_NO_IDLE_THREAD FALSE
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#endif
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/** @} */
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/*===========================================================================*/
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/**
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* @name Performance options
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* @{
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*/
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/*===========================================================================*/
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/**
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* @brief OS optimization.
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* @details If enabled then time efficient rather than space efficient code
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* is used when two possible implementations exist.
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*
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* @note This is not related to the compiler optimization options.
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* @note The default is @p TRUE.
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*/
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#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
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#define CH_OPTIMIZE_SPEED TRUE
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#endif
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/** @} */
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/*===========================================================================*/
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/**
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* @name Subsystem options
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* @{
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*/
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/*===========================================================================*/
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/**
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* @brief Threads registry APIs.
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* @details If enabled then the registry APIs are included in the kernel.
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*
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* @note The default is @p TRUE.
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*/
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#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
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#define CH_USE_REGISTRY TRUE
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#endif
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/**
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* @brief Threads synchronization APIs.
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* @details If enabled then the @p chThdWait() function is included in
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* the kernel.
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*
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* @note The default is @p TRUE.
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*/
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#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
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#define CH_USE_WAITEXIT TRUE
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#endif
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/**
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* @brief Semaphores APIs.
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* @details If enabled then the Semaphores APIs are included in the kernel.
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*
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* @note The default is @p TRUE.
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*/
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#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
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#define CH_USE_SEMAPHORES TRUE
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#endif
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/**
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* @brief Semaphores queuing mode.
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* @details If enabled then the threads are enqueued on semaphores by
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* priority rather than in FIFO order.
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*
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* @note The default is @p FALSE. Enable this if you have special requirements.
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* @note Requires @p CH_USE_SEMAPHORES.
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*/
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#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
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#define CH_USE_SEMAPHORES_PRIORITY FALSE
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#endif
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/**
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* @brief Atomic semaphore API.
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* @details If enabled then the semaphores the @p chSemSignalWait() API
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* is included in the kernel.
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*
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* @note The default is @p TRUE.
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* @note Requires @p CH_USE_SEMAPHORES.
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*/
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#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
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#define CH_USE_SEMSW TRUE
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#endif
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/**
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* @brief Mutexes APIs.
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* @details If enabled then the mutexes APIs are included in the kernel.
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*
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* @note The default is @p TRUE.
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*/
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#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
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#define CH_USE_MUTEXES TRUE
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#endif
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/**
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* @brief Conditional Variables APIs.
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* @details If enabled then the conditional variables APIs are included
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* in the kernel.
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*
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* @note The default is @p TRUE.
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* @note Requires @p CH_USE_MUTEXES.
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*/
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#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
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#define CH_USE_CONDVARS TRUE
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#endif
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||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs with timeout.
|
||||
* @details If enabled then the conditional variables APIs with timeout
|
||||
* specification are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_USE_CONDVARS.
|
||||
*/
|
||||
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
|
||||
#define CH_USE_CONDVARS_TIMEOUT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Events Flags APIs.
|
||||
* @details If enabled then the event flags APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
|
||||
#define CH_USE_EVENTS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Events Flags APIs with timeout.
|
||||
* @details If enabled then the events APIs with timeout specification
|
||||
* are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_USE_EVENTS.
|
||||
*/
|
||||
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
|
||||
#define CH_USE_EVENTS_TIMEOUT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Synchronous Messages APIs.
|
||||
* @details If enabled then the synchronous messages APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
|
||||
#define CH_USE_MESSAGES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Synchronous Messages queuing mode.
|
||||
* @details If enabled then messages are served by priority rather than in
|
||||
* FIFO order.
|
||||
*
|
||||
* @note The default is @p FALSE. Enable this if you have special requirements.
|
||||
* @note Requires @p CH_USE_MESSAGES.
|
||||
*/
|
||||
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define CH_USE_MESSAGES_PRIORITY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Mailboxes APIs.
|
||||
* @details If enabled then the asynchronous messages (mailboxes) APIs are
|
||||
* included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_USE_SEMAPHORES.
|
||||
*/
|
||||
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
|
||||
#define CH_USE_MAILBOXES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief I/O Queues APIs.
|
||||
* @details If enabled then the I/O queues APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
|
||||
#define CH_USE_QUEUES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Core Memory Manager APIs.
|
||||
* @details If enabled then the core memory manager APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
|
||||
#define CH_USE_MEMCORE TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Heap Allocator APIs.
|
||||
* @details If enabled then the memory heap allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
|
||||
* @p CH_USE_SEMAPHORES.
|
||||
* @note Mutexes are recommended.
|
||||
*/
|
||||
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
|
||||
#define CH_USE_HEAP TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief C-runtime allocator.
|
||||
* @details If enabled the the heap allocator APIs just wrap the C-runtime
|
||||
* @p malloc() and @p free() functions.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note Requires @p CH_USE_HEAP.
|
||||
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
|
||||
* appropriate documentation.
|
||||
*/
|
||||
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
|
||||
#define CH_USE_MALLOC_HEAP FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Memory Pools Allocator APIs.
|
||||
* @details If enabled then the memory pools allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
|
||||
#define CH_USE_MEMPOOLS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Dynamic Threads APIs.
|
||||
* @details If enabled then the dynamic threads creation APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_USE_WAITEXIT.
|
||||
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
|
||||
*/
|
||||
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
|
||||
#define CH_USE_DYNAMIC TRUE
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Debug options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Debug option, system state check.
|
||||
* @details If enabled the correct call protocol for system APIs is checked
|
||||
* at runtime.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, parameters checks.
|
||||
* @details If enabled then the checks on the API functions input
|
||||
* parameters are activated.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_ENABLE_CHECKS FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, consistency checks.
|
||||
* @details If enabled then all the assertions in the kernel code are
|
||||
* activated. This includes consistency checks inside the kernel,
|
||||
* runtime anomalies and port-defined checks.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_ENABLE_ASSERTS FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, trace buffer.
|
||||
* @details If enabled then the context switch circular trace buffer is
|
||||
* activated.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_ENABLE_TRACE FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, stack checks.
|
||||
* @details If enabled then a runtime stack check is performed.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note The stack check is performed in a architecture/port dependent way.
|
||||
* It may not be implemented or some ports.
|
||||
* @note The default failure mode is to halt the system with the global
|
||||
* @p panic_msg variable set to @p NULL.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_ENABLE_STACK_CHECK FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, stacks initialization.
|
||||
* @details If enabled then the threads working area is filled with a byte
|
||||
* value when a thread is created. This can be useful for the
|
||||
* runtime measurement of the used stack.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_FILL_THREADS FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, threads profiling.
|
||||
* @details If enabled then a field is added to the @p Thread structure that
|
||||
* counts the system ticks occurred while executing the thread.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note This debug option is defaulted to TRUE because it is required by
|
||||
* some test cases into the test suite.
|
||||
*/
|
||||
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_THREADS_PROFILING TRUE
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Kernel hooks
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Threads descriptor structure extension.
|
||||
* @details User fields added to the end of the @p Thread structure.
|
||||
*/
|
||||
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
|
||||
#define THREAD_EXT_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Threads initialization hook.
|
||||
* @details User initialization code added to the @p chThdInit() API.
|
||||
*
|
||||
* @note It is invoked from within @p chThdInit() and implicitly from all
|
||||
* the threads creation APIs.
|
||||
*/
|
||||
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
|
||||
#define THREAD_EXT_INIT_HOOK(tp) { \
|
||||
/* Add threads initialization code here.*/ \
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Threads finalization hook.
|
||||
* @details User finalization code added to the @p chThdExit() API.
|
||||
*
|
||||
* @note It is inserted into lock zone.
|
||||
* @note It is also invoked when the threads simply return in order to
|
||||
* terminate.
|
||||
*/
|
||||
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
|
||||
#define THREAD_EXT_EXIT_HOOK(tp) { \
|
||||
/* Add threads finalization code here.*/ \
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Context switch hook.
|
||||
* @details This hook is invoked just before switching between threads.
|
||||
*/
|
||||
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
|
||||
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
|
||||
/* System halt code here.*/ \
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Idle Loop hook.
|
||||
* @details This hook is continuously invoked by the idle thread loop.
|
||||
*/
|
||||
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
|
||||
#define IDLE_LOOP_HOOK() { \
|
||||
/* Idle loop code here.*/ \
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System tick event hook.
|
||||
* @details This hook is invoked in the system tick handler immediately
|
||||
* after processing the virtual timers queue.
|
||||
*/
|
||||
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
|
||||
#define SYSTEM_TICK_EVENT_HOOK() { \
|
||||
/* System tick event code here.*/ \
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System halt hook.
|
||||
* @details This hook is invoked in case to a system halting error before
|
||||
* the system is halted.
|
||||
*/
|
||||
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
|
||||
#define SYSTEM_HALT_HOOK() { \
|
||||
/* System halt code here.*/ \
|
||||
}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Port-specific settings (override port settings defaulted in chcore.h). */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _CHCONF_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,312 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file templates/halconf.h
|
||||
* @brief HAL configuration header.
|
||||
* @details HAL configuration file, this file allows to enable or disable the
|
||||
* various device drivers from your application. You may also use
|
||||
* this file in order to override the device drivers default settings.
|
||||
*
|
||||
* @addtogroup HAL_CONF
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _HALCONF_H_
|
||||
#define _HALCONF_H_
|
||||
|
||||
#include "mcuconf.h"
|
||||
|
||||
/**
|
||||
* @brief Enables the TM subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_TM TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the PAL subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_PAL TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ADC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ADC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the CAN subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CAN FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the EXT subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_EXT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the GPT subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_GPT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2C subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2C FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ICU subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ICU FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the MAC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_MAC TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the MMC_SPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_MMC_SPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the PWM subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_PWM FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the RTC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_RTC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SDC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SDC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SERIAL subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SERIAL over USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL_USB FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the UART subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_UART FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_USB FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* ADC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define ADC_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define ADC_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CAN driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Sleep mode related APIs inclusion switch.
|
||||
*/
|
||||
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
|
||||
#define CAN_USE_SLEEP_MODE TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I2C driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the mutual exclusion APIs on the I2C bus.
|
||||
*/
|
||||
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define I2C_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* MAC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables an event sources for incoming packets.
|
||||
*/
|
||||
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
|
||||
#define MAC_USE_ZERO_COPY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables an event sources for incoming packets.
|
||||
*/
|
||||
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
|
||||
#define MAC_USE_EVENTS TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* MMC_SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Delays insertions.
|
||||
* @details If enabled this options inserts delays into the MMC waiting
|
||||
* routines releasing some extra CPU time for the threads with
|
||||
* lower priority, this may slow down the driver a bit however.
|
||||
* This option is recommended also if the SPI driver does not
|
||||
* use a DMA channel and heavily loads the CPU.
|
||||
*/
|
||||
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||
#define MMC_NICE_WAITING TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SDC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Number of initialization attempts before rejecting the card.
|
||||
* @note Attempts are performed at 10mS intervals.
|
||||
*/
|
||||
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
|
||||
#define SDC_INIT_RETRY 100
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Include support for MMC cards.
|
||||
* @note MMC support is not yet implemented so this option must be kept
|
||||
* at @p FALSE.
|
||||
*/
|
||||
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
|
||||
#define SDC_MMC_SUPPORT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Delays insertions.
|
||||
* @details If enabled this options inserts delays into the MMC waiting
|
||||
* routines releasing some extra CPU time for the threads with
|
||||
* lower priority, this may slow down the driver a bit however.
|
||||
*/
|
||||
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||
#define SDC_NICE_WAITING TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Default bit rate.
|
||||
* @details Configuration parameter, this is the baud rate selected for the
|
||||
* default configuration.
|
||||
*/
|
||||
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_DEFAULT_BITRATE 38400
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Serial buffers size.
|
||||
* @details Configuration parameter, you can change the depth of the queue
|
||||
* buffers depending on the requirements of your application.
|
||||
* @note The default is 64 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_BUFFERS_SIZE 16
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
#endif /* _HALCONF_H_ */
|
||||
|
||||
/** @} */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
#include "test.h"
|
||||
|
||||
#include "lwipthread.h"
|
||||
|
||||
#include "web/web.h"
|
||||
|
||||
/*
|
||||
* Green LED blinker thread, times are in milliseconds.
|
||||
*/
|
||||
static WORKING_AREA(waThread1, 128);
|
||||
static msg_t Thread1(void *arg) {
|
||||
|
||||
(void)arg;
|
||||
chRegSetThreadName("blinker");
|
||||
while (TRUE) {
|
||||
palClearPad(GPIO0, GPIO0_LED2_RED);
|
||||
chThdSleepMilliseconds(500);
|
||||
palSetPad(GPIO0, GPIO0_LED2_RED);
|
||||
chThdSleepMilliseconds(500);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Application entry point.
|
||||
*/
|
||||
int main(void) {
|
||||
|
||||
/*
|
||||
* System initializations.
|
||||
* - HAL initialization, this also initializes the configured device drivers
|
||||
* and performs the board-specific initializations.
|
||||
* - Kernel initialization, the main() function becomes a thread and the
|
||||
* RTOS is active.
|
||||
*/
|
||||
halInit();
|
||||
chSysInit();
|
||||
|
||||
/*
|
||||
* Activates the serial driver 6 using the driver default configuration.
|
||||
*/
|
||||
sdStart(&SD1, NULL);
|
||||
|
||||
/*
|
||||
* Creates the blinker thread.
|
||||
*/
|
||||
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
|
||||
|
||||
/*
|
||||
* Creates the LWIP threads (it changes priority internally).
|
||||
*/
|
||||
chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 1,
|
||||
lwip_thread, NULL);
|
||||
|
||||
/*
|
||||
* Creates the HTTP thread (it changes priority internally).
|
||||
*/
|
||||
chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1,
|
||||
http_server, NULL);
|
||||
|
||||
/*
|
||||
* Normal main() thread activity, in this demo it does nothing except
|
||||
* sleeping in a loop and check the button state.
|
||||
*/
|
||||
while (TRUE) {
|
||||
if (palReadPad(GPIO2, GPIO2_PIN12_TO_GND) == 0)
|
||||
TestThread(&SD1);
|
||||
chThdSleepMilliseconds(500);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* LPC17xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the driver
|
||||
* is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 7...0 Lowest...highest.
|
||||
*/
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define LPC17xx_MAINOSC_ENABLE TRUE
|
||||
#define LPC17xx_SYSCLK_SELECT CLKSRCSEL_MAINOSC
|
||||
#define LPC17xx_MAINPLL_ENABLE TRUE
|
||||
#define LPC17xx_MAINPLL_MUL 30
|
||||
#define LPC17xx_MAINPLL_PREDIV 1
|
||||
#define LPC17xx_USBPLL_ENABLE FALSE
|
||||
#define LPC17xx_USBPLL_MUL 4
|
||||
#define LPC17xx_USBPLL_DIV 4
|
||||
#define LPC17xx_CCLK_DIV 3
|
||||
#define LPC17xx_PCLK_SELECT PCLKSEL_CCLK
|
||||
#define LPC17xx_CLKOUT_ENABLE FALSE
|
||||
#define LPC17xx_CLKOUT_DIV 4
|
||||
#define LPC17xx_CLKOUT_SELECT CLKOUTSEL_CCLK
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define LPC17xx_GPT_USE_TIM0 TRUE
|
||||
#define LPC17xx_GPT_USE_TIM1 TRUE
|
||||
#define LPC17xx_GPT_USE_TIM2 TRUE
|
||||
#define LPC17xx_GPT_USE_TIM3 TRUE
|
||||
#define LPC17xx_GPT_TIM0_IRQ_PRIORITY 2
|
||||
#define LPC17xx_GPT_TIM1_IRQ_PRIORITY 6
|
||||
#define LPC17xx_GPT_TIM2_IRQ_PRIORITY 2
|
||||
#define LPC17xx_GPT_TIM3_IRQ_PRIORITY 2
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define LPC17xx_SERIAL_USE_UART0 TRUE
|
||||
#define LPC17xx_SERIAL_USE_UART1 FALSE
|
||||
#define LPC17xx_SERIAL_USE_UART2 FALSE
|
||||
#define LPC17xx_SERIAL_USE_UART3 FALSE
|
||||
#define LPC17xx_SERIAL_FIFO_PRELOAD 16
|
||||
#define LPC17xx_SERIAL_UART0_IRQ_PRIORITY 3
|
||||
#define LPC17xx_SERIAL_UART1_IRQ_PRIORITY 3
|
||||
#define LPC17xx_SERIAL_UART2_IRQ_PRIORITY 3
|
||||
#define LPC17xx_SERIAL_UART3_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define LPC17xx_I2C_USE_I2C0 FALSE
|
||||
#define LPC17xx_I2C_USE_I2C1 FALSE
|
||||
#define LPC17xx_I2C_USE_I2C2 FALSE
|
||||
#define LPC17xx_I2C_I2C0_IRQ_PRIORITY 3
|
||||
#define LPC17xx_I2C_I2C1_IRQ_PRIORITY 3
|
||||
#define LPC17xx_I2C_I2C2_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define LPC17xx_SPI_USE_SSP0 TRUE
|
||||
#define LPC17xx_SPI_USE_SSP1 FALSE
|
||||
#define LPC17xx_SPI_SSP0CLKDIV 1
|
||||
#define LPC17xx_SPI_SSP1CLKDIV 1
|
||||
#define LPC17xx_SPI_SSP0_IRQ_PRIORITY 5
|
||||
#define LPC17xx_SPI_SSP1_IRQ_PRIORITY 5
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define LPC17xx_RTC_IS_CALENDAR TRUE
|
||||
#define LPC17xx_RTC_USE_ALARM TRUE
|
||||
#define LPC17xx_RTC_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define LPC17xx_DAC_DMA_CHANNEL DMA_CHANNEL5
|
||||
|
||||
/*
|
||||
* MAC driver system settings.
|
||||
*/
|
||||
#define LPC17xx_MAC_TRANSMIT_BUFFERS 2
|
||||
#define LPC17xx_MAC_RECEIVE_BUFFERS 4
|
||||
#define LPC17xx_MAC_BUFFERS_SIZE 1522
|
||||
#define LPC17xx_MAC_PHY_TIMEOUT 100
|
||||
#define LPC17xx_MAC_ETH_IRQ_PRIORITY 13
|
||||
#define LPC17xx_MAC_RESET_DELAY 100
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is a modified version of the lwIP web server demo. The original
|
||||
* author is unknown because the file didn't contain any license information.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file web.c
|
||||
* @brief HTTP server wrapper thread code.
|
||||
* @addtogroup WEB_THREAD
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
|
||||
#include "lwip/opt.h"
|
||||
#include "lwip/arch.h"
|
||||
#include "lwip/api.h"
|
||||
|
||||
#include "web.h"
|
||||
|
||||
#if LWIP_NETCONN
|
||||
|
||||
static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n";
|
||||
static const char http_index_html[] = "<html><head><title>Congrats!</title></head><body><h1>Welcome to our lwIP HTTP server!</h1><p>This is a small test page.</body></html>";
|
||||
|
||||
static void http_server_serve(struct netconn *conn) {
|
||||
struct netbuf *inbuf;
|
||||
char *buf;
|
||||
u16_t buflen;
|
||||
err_t err;
|
||||
|
||||
/* Read the data from the port, blocking if nothing yet there.
|
||||
We assume the request (the part we care about) is in one netbuf */
|
||||
err = netconn_recv(conn, &inbuf);
|
||||
|
||||
if (err == ERR_OK) {
|
||||
netbuf_data(inbuf, (void **)&buf, &buflen);
|
||||
|
||||
/* Is this an HTTP GET command? (only check the first 5 chars, since
|
||||
there are other formats for GET, and we're keeping it very simple )*/
|
||||
if (buflen>=5 &&
|
||||
buf[0]=='G' &&
|
||||
buf[1]=='E' &&
|
||||
buf[2]=='T' &&
|
||||
buf[3]==' ' &&
|
||||
buf[4]=='/' ) {
|
||||
|
||||
/* Send the HTML header
|
||||
* subtract 1 from the size, since we dont send the \0 in the string
|
||||
* NETCONN_NOCOPY: our data is const static, so no need to copy it
|
||||
*/
|
||||
netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY);
|
||||
|
||||
/* Send our HTML page */
|
||||
netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY);
|
||||
}
|
||||
}
|
||||
/* Close the connection (server closes in HTTP) */
|
||||
netconn_close(conn);
|
||||
|
||||
/* Delete the buffer (netconn_recv gives us ownership,
|
||||
so we have to make sure to deallocate the buffer) */
|
||||
netbuf_delete(inbuf);
|
||||
}
|
||||
|
||||
/**
|
||||
* Stack area for the http thread.
|
||||
*/
|
||||
WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
|
||||
|
||||
/**
|
||||
* HTTP server thread.
|
||||
*/
|
||||
msg_t http_server(void *p) {
|
||||
struct netconn *conn, *newconn;
|
||||
err_t err;
|
||||
|
||||
(void)p;
|
||||
|
||||
/* Create a new TCP connection handle */
|
||||
conn = netconn_new(NETCONN_TCP);
|
||||
LWIP_ERROR("http_server: invalid conn", (conn != NULL), return RDY_RESET;);
|
||||
|
||||
/* Bind to port 80 (HTTP) with default IP address */
|
||||
netconn_bind(conn, NULL, WEB_THREAD_PORT);
|
||||
|
||||
/* Put the connection into LISTEN state */
|
||||
netconn_listen(conn);
|
||||
|
||||
/* Goes to the final priority after initialization.*/
|
||||
chThdSetPriority(WEB_THREAD_PRIORITY);
|
||||
|
||||
while(1) {
|
||||
err = netconn_accept(conn, &newconn);
|
||||
if (err != ERR_OK)
|
||||
continue;
|
||||
http_server_serve(newconn);
|
||||
netconn_delete(newconn);
|
||||
}
|
||||
return RDY_OK;
|
||||
}
|
||||
|
||||
#endif /* LWIP_NETCONN */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file web.h
|
||||
* @brief HTTP server wrapper thread macros and structures.
|
||||
* @addtogroup WEB_THREAD
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _WEB_H_
|
||||
#define _WEB_H_
|
||||
|
||||
#ifndef WEB_THREAD_STACK_SIZE
|
||||
#define WEB_THREAD_STACK_SIZE 1024
|
||||
#endif
|
||||
|
||||
#ifndef WEB_THREAD_PORT
|
||||
#define WEB_THREAD_PORT 80
|
||||
#endif
|
||||
|
||||
#ifndef WEB_THREAD_PRIORITY
|
||||
#define WEB_THREAD_PRIORITY (LOWPRIO + 2)
|
||||
#endif
|
||||
|
||||
extern WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
msg_t http_server(void *p);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _WEB_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -65,9 +65,8 @@ int main(void) {
|
|||
*/
|
||||
|
||||
while (TRUE) {
|
||||
if (!palReadPad(GPIO2, GPIO2_SW_TO_GND))
|
||||
if (!palReadPad(GPIO2, GPIO2_PIN12_TO_GND))
|
||||
TestThread(&SD1);
|
||||
|
||||
}
|
||||
chThdSleepMilliseconds(100);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,784 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
This file has been contributed by:
|
||||
Marcin Jokel.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file LPC17xx/mac_lld.c
|
||||
* @brief LPC17xx low level MAC driver code.
|
||||
*
|
||||
* @addtogroup MAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
#include "mii.h"
|
||||
|
||||
#if HAL_USE_MAC || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#define BUFFER_SIZE ((((LPC17xx_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
|
||||
|
||||
/* MII divider optimal value.*/
|
||||
#if (LPC17xx_CCLK <= 50000000)
|
||||
#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_20
|
||||
#elif (LPC17xx_CCLK <= 70000000)
|
||||
#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_28
|
||||
#elif (LPC17xx_CCLK <= 80000000)
|
||||
#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_36
|
||||
#elif (LPC17xx_CCLK <= 90000000)
|
||||
#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_40
|
||||
#elif (LPC17xx_CCLK <= 100000000)
|
||||
#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_44
|
||||
#elif (LPC17xx_CCLK <= 120000000)
|
||||
#define MAC_MII_MCFG_CLK_SEL EMAC_MCFG_CLK_DIV_48
|
||||
#else
|
||||
#error "LPC17xx_CCLK over maximum frequency for ETH operations (120MHz)"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Ethernet driver 1.
|
||||
*/
|
||||
MACDriver ETHD1;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
|
||||
0x37, 0x01, 0x10};
|
||||
|
||||
static lpc17xx_eth_rx_descriptor_t rd[LPC17xx_MAC_RECEIVE_BUFFERS]
|
||||
__attribute__((aligned(4))) __attribute__((section(".eth_ram")));
|
||||
static lpc17xx_eth_tx_descriptor_t td[LPC17xx_MAC_TRANSMIT_BUFFERS]
|
||||
__attribute__((aligned(4))) __attribute__((section(".eth_ram")));
|
||||
|
||||
static lpc17xx_eth_tx_descriptor_t td_tmp[LPC17xx_MAC_TRANSMIT_BUFFERS]
|
||||
__attribute__((aligned(4))) __attribute__((section(".eth_ram")));
|
||||
|
||||
static lpc17xx_eth_rx_status_t rd_stat[LPC17xx_MAC_RECEIVE_BUFFERS]
|
||||
__attribute__((aligned(8))) __attribute__((section(".eth_ram")));
|
||||
static lpc17xx_eth_tx_status_t td_stat[LPC17xx_MAC_TRANSMIT_BUFFERS]
|
||||
__attribute__((aligned(4))) __attribute__((section(".eth_ram")));
|
||||
|
||||
static uint32_t rb[LPC17xx_MAC_RECEIVE_BUFFERS][BUFFER_SIZE]
|
||||
__attribute__((aligned(4))) __attribute__((section(".eth_ram")));
|
||||
static uint32_t tb[LPC17xx_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]
|
||||
__attribute__((aligned(4))) __attribute__((section(".eth_ram")));
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Writes a PHY register.
|
||||
*
|
||||
* @param[in] macp pointer to the @p MACDriver object
|
||||
* @param[in] reg register number
|
||||
* @param[in] value new register value
|
||||
*/
|
||||
void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) {
|
||||
|
||||
LPC_EMAC->MCMD = 0;
|
||||
LPC_EMAC->MADR = macp->phyaddr | reg; /* Write PHY address and register address */
|
||||
LPC_EMAC->MWTD = value; /* Write data */
|
||||
while((LPC_EMAC->MIND & EMAC_MIND_BUSY) != 0)
|
||||
; /* Wait for busy bit to be cleared in MIND */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads a PHY register.
|
||||
*
|
||||
* @param[in] macp pointer to the @p MACDriver object
|
||||
* @param[in] reg register number
|
||||
*
|
||||
* @return The PHY register content.
|
||||
*/
|
||||
uint32_t mii_read(MACDriver *macp, uint32_t reg) {
|
||||
|
||||
LPC_EMAC->MCMD = 1;
|
||||
LPC_EMAC->MADR = macp->phyaddr | reg; /* Write PHY address and register address */
|
||||
while((LPC_EMAC->MIND & EMAC_MIND_BUSY) != 0)
|
||||
; /* Wait for busy bit to be cleared in MIND */
|
||||
LPC_EMAC->MCMD = 0;
|
||||
return LPC_EMAC->MRDD;
|
||||
}
|
||||
|
||||
#if !defined(BOARD_PHY_ADDRESS)
|
||||
/**
|
||||
* @brief PHY address detection.
|
||||
*
|
||||
* @param[in] macp pointer to the @p MACDriver object
|
||||
*/
|
||||
void mii_find_phy(MACDriver *macp) {
|
||||
uint32_t i;
|
||||
|
||||
#if LPC17xx_MAC_PHY_TIMEOUT > 0
|
||||
halrtcnt_t start = halGetCounterValue();
|
||||
halrtcnt_t timeout = start + MS2RTT(LPC17xx_MAC_PHY_TIMEOUT);
|
||||
while (halIsCounterWithin(start, timeout)) {
|
||||
#endif
|
||||
for (i = 0; i < 31; i++) {
|
||||
macp->phyaddr = i << 8;
|
||||
if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) &&
|
||||
((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
|
||||
return;
|
||||
}
|
||||
}
|
||||
#if LPC17xx_MAC_PHY_TIMEOUT > 0
|
||||
}
|
||||
#endif
|
||||
/* Wrong or defective board.*/
|
||||
chSysHalt();
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MAC address setup.
|
||||
*
|
||||
* @param[in] p pointer to a six bytes buffer containing the MAC
|
||||
* address
|
||||
*/
|
||||
static void mac_lld_set_address(const uint8_t *p) {
|
||||
|
||||
/* MAC address configuration, only a single address comparator is used,
|
||||
hash table not used.*/
|
||||
|
||||
LPC_EMAC->SA0 = ((uint32_t)p[5] << 8) |
|
||||
((uint32_t)p[4] << 0);
|
||||
LPC_EMAC->SA1 = ((uint32_t)p[3] << 8) |
|
||||
((uint32_t)p[2] << 0);
|
||||
LPC_EMAC->SA2 = ((uint32_t)p[1] << 8) |
|
||||
((uint32_t)p[0] << 0);
|
||||
|
||||
LPC_EMAC->HashFilterL = 0;
|
||||
LPC_EMAC->HashFilterH = 0;
|
||||
|
||||
LPC_EMAC->RxFilterCtrl = EMAC_RXFILCTRL_PERFECT_EN | EMAC_RXFILCTRL_BROADCAST_EN;
|
||||
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
CH_IRQ_HANDLER(VectorB0) {
|
||||
|
||||
uint32_t intstatus;
|
||||
uint32_t consume_index;
|
||||
uint32_t txdescn;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
intstatus = LPC_EMAC->IntStatus;
|
||||
LPC_EMAC->IntClear = intstatus;
|
||||
|
||||
if (intstatus & EMAC_INTSTAT_RX_OVERRUN) {
|
||||
/* Reset receive logic. */
|
||||
LPC_EMAC->MAC1 |= EMAC_MAC1_RESET_RX | EMAC_MAC1_RESET_MCS_RX;
|
||||
__NOP();
|
||||
LPC_EMAC->MAC1 &= ~(EMAC_MAC1_RESET_RX | EMAC_MAC1_RESET_MCS_RX);
|
||||
}
|
||||
|
||||
if (intstatus & EMAC_INTSTAT_TX_UNDERRUN) {
|
||||
/* Reset transmit logic. */
|
||||
LPC_EMAC->MAC1 |= EMAC_MAC1_RESET_TX | EMAC_MAC1_RESET_MCS_TX;
|
||||
__NOP();
|
||||
LPC_EMAC->MAC1 &= ~(EMAC_MAC1_RESET_TX | EMAC_MAC1_RESET_MCS_TX);
|
||||
}
|
||||
|
||||
if (intstatus & EMAC_INTSTAT_RX_DONE) {
|
||||
/* Data Received.*/
|
||||
chSysLockFromIsr();
|
||||
chSemResetI(ÐD1.rdsem, 0);
|
||||
#if MAC_USE_EVENTS
|
||||
chEvtBroadcastI(ÐD1.rdevent);
|
||||
#endif
|
||||
chSysUnlockFromIsr();
|
||||
}
|
||||
|
||||
if (intstatus & EMAC_INTSTAT_TX_DONE) {
|
||||
/* Data Transmitted.*/
|
||||
consume_index = LPC_EMAC->TxConsumeIndex;
|
||||
if (consume_index == 0)
|
||||
consume_index = LPC17xx_MAC_TRANSMIT_BUFFERS - 1;
|
||||
else
|
||||
consume_index--;
|
||||
txdescn = (td[consume_index].control >> 12) & 0x000000FF;
|
||||
td_tmp[txdescn].control = 0; /* Unlock temporary descriptor. */
|
||||
chSysLockFromIsr();
|
||||
chSemResetI(ÐD1.tdsem, 0);
|
||||
chSysUnlockFromIsr();
|
||||
}
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Low level MAC initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void mac_lld_init(void) {
|
||||
unsigned i;
|
||||
|
||||
macObjectInit(ÐD1);
|
||||
ETHD1.link_up = FALSE;
|
||||
|
||||
LPC_SC->PCONP |= (1 << 30); /* Power up MAC */
|
||||
|
||||
/* Rx desciptor and Rx status tables are initialized. */
|
||||
for (i = 0; i < LPC17xx_MAC_RECEIVE_BUFFERS; i++) {
|
||||
rd[i].packet = (uint32_t) &rb[i];
|
||||
rd[i].control = EMAC_RXSTATUS_CTRL_INT | (LPC17xx_MAC_BUFFERS_SIZE - 1);
|
||||
|
||||
rd_stat[i].info = 0;
|
||||
rd_stat[i].hashcrc = 0;
|
||||
}
|
||||
|
||||
/* Tx desciptor and Tx status tables are cleared. They are set up every time
|
||||
when transmission starts. */
|
||||
for (i = 0; i < LPC17xx_MAC_TRANSMIT_BUFFERS; i++) {
|
||||
td[i].packet = 0;
|
||||
td[i].control = 0;
|
||||
td_stat[i] = 0;
|
||||
|
||||
td_tmp[i].packet = (uint32_t) &tb[i];
|
||||
td_tmp[i].control = 0;
|
||||
}
|
||||
|
||||
/* Reset all EMAC internal modules. */
|
||||
LPC_EMAC->MAC1 = EMAC_MAC1_RESET_TX | EMAC_MAC1_RESET_MCS_TX | EMAC_MAC1_RESET_RX |
|
||||
EMAC_MAC1_RESET_MCS_RX | EMAC_MAC1_SIM_RESET | EMAC_MAC1_SOFT_RESET;
|
||||
LPC_EMAC->Command = EMAC_COMMAND_REG_RESET | EMAC_COMMAND_TX_RESET | EMAC_COMMAND_RX_RESET;
|
||||
LPC_EMAC->MCFG = EMAC_MCFG_RESET_MII_MGMT; /* Reset MII Managment hardware. */
|
||||
|
||||
halPolledDelay(LPC17XX_MAC_RESET_DELAY);
|
||||
|
||||
LPC_EMAC->MAC1 = 0; /* MAC reset de-asserted. */
|
||||
|
||||
/* Selection of the RMII or MII mode based on info exported by board.h.*/
|
||||
#if defined(BOARD_PHY_RMII)
|
||||
LPC_EMAC->Command = EMAC_COMMAND_RMII | EMAC_COMMAND_PASS_RUN_FRAME;
|
||||
#else
|
||||
LPC_EMAC->Command = EMAC_COMMAND_PASS_RUN_FRAME;
|
||||
#endif
|
||||
|
||||
LPC_EMAC->MCFG = MAC_MII_MCFG_CLK_SEL; /* Set MII clock divider. */
|
||||
|
||||
/* PHY address setup.*/
|
||||
#if defined(BOARD_PHY_ADDRESS)
|
||||
ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11;
|
||||
#else
|
||||
mii_find_phy(ÐD1);
|
||||
#endif
|
||||
|
||||
#if defined(BOARD_PHY_RESET)
|
||||
/* PHY board-specific reset procedure.*/
|
||||
BOARD_PHY_RESET();
|
||||
#else
|
||||
/* PHY soft reset procedure.*/
|
||||
mii_write(ÐD1, MII_BMCR, BMCR_RESET);
|
||||
#if defined(BOARD_PHY_RESET_DELAY)
|
||||
halPolledDelay(BOARD_PHY_RESET_DELAY);
|
||||
#endif
|
||||
while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET)
|
||||
;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures and activates the MAC peripheral.
|
||||
*
|
||||
* @param[in] macp pointer to the @p MACDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void mac_lld_start(MACDriver *macp) {
|
||||
|
||||
/* PHY in power up mode.*/
|
||||
mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
|
||||
|
||||
/* MAC registers configuration.*/
|
||||
LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL_REC;
|
||||
LPC_EMAC->MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_CRC_EN;
|
||||
LPC_EMAC->MAXF = LPC17XX_MAC_MAX_FLEN;
|
||||
LPC_EMAC->CLRT = LPC17XX_MAC_CLRT_DEF;
|
||||
LPC_EMAC->IPGR = LPC17XX_MAC_IPGR_DEF;
|
||||
|
||||
/* MAC descriptor registers configuration. */
|
||||
macp->rxsoftindex = 0;
|
||||
LPC_EMAC->RxDescriptor = (uint32_t) &rd[0];
|
||||
LPC_EMAC->RxDescriptorNumber = LPC17xx_MAC_RECEIVE_BUFFERS - 1;
|
||||
LPC_EMAC->RxConsumeIndex = 0;
|
||||
LPC_EMAC->RxStatus = (uint32_t) &rd_stat[0];
|
||||
|
||||
macp->txsoftindex = 0;
|
||||
LPC_EMAC->TxDescriptor = (uint32_t) &td[0];
|
||||
LPC_EMAC->TxDescriptorNumber = LPC17xx_MAC_TRANSMIT_BUFFERS - 1;
|
||||
LPC_EMAC->TxProduceIndex = 0;
|
||||
LPC_EMAC->TxStatus = (uint32_t) &td_stat[0];
|
||||
|
||||
/* MAC address setup.*/
|
||||
if (macp->config->mac_address == NULL)
|
||||
mac_lld_set_address(default_mac_address);
|
||||
else
|
||||
mac_lld_set_address(macp->config->mac_address);
|
||||
|
||||
/* Enable EMAC interrupts. */
|
||||
LPC_EMAC->IntEnable = EMAC_INTEN_TX_DONE | EMAC_INTEN_RX_DONE |
|
||||
EMAC_INTEN_RX_OVERRUN | EMAC_INTEN_TX_UNDERRUN;
|
||||
|
||||
/* Reset all interrupts. */
|
||||
LPC_EMAC->IntClear = 0xFFFF;
|
||||
|
||||
/* ISR vector enabled.*/
|
||||
nvicEnableVector(ENET_IRQn, CORTEX_PRIORITY_MASK(LPC17xx_MAC_ETH_IRQ_PRIORITY));
|
||||
|
||||
/* Enable receive and transmit mode. */
|
||||
LPC_EMAC->Command |= EMAC_COMMAND_TX_ENABLE | EMAC_COMMAND_RX_ENABLE;
|
||||
LPC_EMAC->MAC1 |= EMAC_MAC1_RECEIVE_EN;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivates the MAC peripheral.
|
||||
*
|
||||
* @param[in] macp pointer to the @p MACDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void mac_lld_stop(MACDriver *macp) {
|
||||
|
||||
if (macp->state != MAC_STOP) {
|
||||
|
||||
/* MAC and DMA stopped.*/
|
||||
LPC_EMAC->MAC1 = 0;
|
||||
LPC_EMAC->Command = 0;
|
||||
LPC_EMAC->IntEnable = 0;
|
||||
|
||||
/* PHY in power down mode until the driver will be restarted.*/
|
||||
mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
|
||||
|
||||
/* ISR vector disabled.*/
|
||||
nvicDisableVector(ENET_IRQn);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns a transmission descriptor.
|
||||
* @details One of the available transmission descriptors is locked and
|
||||
* returned.
|
||||
*
|
||||
* @param[in] macp pointer to the @p MACDriver object
|
||||
* @param[out] tdp pointer to a @p MACTransmitDescriptor structure
|
||||
* @return The operation status.
|
||||
* @retval RDY_OK the descriptor has been obtained.
|
||||
* @retval RDY_TIMEOUT descriptor not available.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
|
||||
MACTransmitDescriptor *tdp) {
|
||||
uint32_t produce_index;
|
||||
uint32_t produce_index_next;
|
||||
|
||||
if (!macp->link_up)
|
||||
return RDY_TIMEOUT;
|
||||
|
||||
chSysLock();
|
||||
|
||||
/* Get Current TX descriptor.*/
|
||||
produce_index = macp->txsoftindex;
|
||||
|
||||
produce_index_next = (produce_index + 1) % LPC17xx_MAC_TRANSMIT_BUFFERS;
|
||||
if (produce_index_next == LPC_EMAC->TxConsumeIndex) {
|
||||
/* Full */
|
||||
chSysUnlock();
|
||||
return RDY_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Ensure that descriptor isn't locked by the Ethernet DMA or
|
||||
another thread.*/
|
||||
if (td_tmp[produce_index].control == EMAC_TXSTATUS_CTRL_LOCK) {
|
||||
chSysUnlock();
|
||||
return RDY_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Marks the current descriptor as locked using a reserved bit.*/
|
||||
td_tmp[produce_index].control = EMAC_TXSTATUS_CTRL_LOCK;
|
||||
|
||||
/* Next TX descriptor to use.*/
|
||||
macp->txsoftindex = produce_index_next;
|
||||
|
||||
chSysUnlock();
|
||||
|
||||
/* Set the buffer size and configuration.*/
|
||||
tdp->offset = 0;
|
||||
tdp->size = LPC17xx_MAC_BUFFERS_SIZE;
|
||||
tdp->txdescn = produce_index;
|
||||
|
||||
return RDY_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Releases a transmit descriptor and starts the transmission of the
|
||||
* enqueued data as a single frame.
|
||||
*
|
||||
* @param[in] tdp the pointer to the @p MACTransmitDescriptor structure
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
|
||||
|
||||
uint32_t produce_index;
|
||||
uint32_t descn;
|
||||
|
||||
chSysLock();
|
||||
|
||||
produce_index = LPC_EMAC->TxProduceIndex;
|
||||
descn = tdp->txdescn;
|
||||
|
||||
/* Set control bits and save temporary descriptor number. */
|
||||
td[produce_index].control = EMAC_TXSTATUS_CTRL_INT | EMAC_TXSTATUS_CTRL_LAST | (descn << 12) |
|
||||
(tdp->offset - 1);
|
||||
|
||||
td[produce_index].packet = td_tmp[descn].packet;
|
||||
LPC_EMAC->TxProduceIndex = (LPC_EMAC->TxProduceIndex + 1) % LPC17xx_MAC_TRANSMIT_BUFFERS;
|
||||
chSysUnlock();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns a receive descriptor.
|
||||
*
|
||||
* @param[in] macp pointer to the @p MACDriver object
|
||||
* @param[out] rdp pointer to a @p MACReceiveDescriptor structure
|
||||
* @return The operation status.
|
||||
* @retval RDY_OK the descriptor has been obtained.
|
||||
* @retval RDY_TIMEOUT descriptor not available.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
|
||||
MACReceiveDescriptor *rdp) {
|
||||
uint32_t consume_index;
|
||||
uint32_t status;
|
||||
|
||||
chSysLock();
|
||||
|
||||
/* Get current rx descriptor number.*/
|
||||
consume_index = macp->rxsoftindex;
|
||||
|
||||
if (LPC_EMAC->RxProduceIndex != consume_index) {
|
||||
status = rd_stat[consume_index].info;
|
||||
if (status != EMAC_RXSTATUS_INFO_ERROR) {
|
||||
/* Found a valid one.*/
|
||||
rdp->offset = 0;
|
||||
rdp->size = (status & EMAC_RXSTATUS_INFO_SIZE_MASK) + 1;
|
||||
rdp->rxdescn = consume_index;
|
||||
|
||||
macp->rxsoftindex = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS;
|
||||
|
||||
chSysUnlock();
|
||||
return RDY_OK;
|
||||
}
|
||||
else {
|
||||
/* Invalid frame found. */
|
||||
if (LPC_EMAC->RxConsumeIndex == consume_index) {
|
||||
consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS;
|
||||
LPC_EMAC->RxConsumeIndex = consume_index;
|
||||
}
|
||||
else {
|
||||
rd[consume_index].control |= EMAC_RXSTATUS_CTRL_READY;
|
||||
consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS;
|
||||
}
|
||||
macp->rxsoftindex = consume_index;
|
||||
}
|
||||
}
|
||||
|
||||
chSysUnlock();
|
||||
|
||||
return RDY_TIMEOUT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Releases a receive descriptor.
|
||||
* @details The descriptor and its buffer are made available for more incoming
|
||||
* frames.
|
||||
*
|
||||
* @param[in] rdp the pointer to the @p MACReceiveDescriptor structure
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
|
||||
|
||||
uint32_t consume_index;
|
||||
|
||||
chSysLock();
|
||||
|
||||
/* Only descriptor with number match RxConsumeIndex can release receive descriptors. */
|
||||
consume_index = LPC_EMAC->RxConsumeIndex;
|
||||
|
||||
if (rdp->rxdescn == consume_index) {
|
||||
consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS;
|
||||
|
||||
while (LPC_EMAC->RxProduceIndex != consume_index) {
|
||||
if (rd[consume_index].control & EMAC_RXSTATUS_CTRL_READY) {
|
||||
rd[consume_index].control &= ~EMAC_RXSTATUS_CTRL_READY;
|
||||
consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS;
|
||||
}
|
||||
else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
LPC_EMAC->RxConsumeIndex = consume_index;
|
||||
}
|
||||
else {
|
||||
rd[rdp->rxdescn].control |= EMAC_RXSTATUS_CTRL_READY;
|
||||
}
|
||||
|
||||
chSysUnlock();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Updates and returns the link status.
|
||||
*
|
||||
* @param[in] macp pointer to the @p MACDriver object
|
||||
* @return The link status.
|
||||
* @retval TRUE if the link is active.
|
||||
* @retval FALSE if the link is down.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
bool_t mac_lld_poll_link_status(MACDriver *macp) {
|
||||
uint32_t mac2, cmd, ipgt, supp, bmsr, bmcr;
|
||||
|
||||
mac2 = LPC_EMAC->MAC2;
|
||||
cmd = LPC_EMAC->Command;
|
||||
|
||||
/* PHY CR and SR registers read.*/
|
||||
(void)mii_read(macp, MII_BMSR);
|
||||
bmsr = mii_read(macp, MII_BMSR);
|
||||
bmcr = mii_read(macp, MII_BMCR);
|
||||
|
||||
/* Check on auto-negotiation mode.*/
|
||||
if (bmcr & BMCR_ANENABLE) {
|
||||
uint32_t lpa;
|
||||
|
||||
/* Auto-negotiation must be finished without faults and link established.*/
|
||||
if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
|
||||
(BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
|
||||
return macp->link_up = FALSE;
|
||||
|
||||
/* Auto-negotiation enabled, checks the LPA register.*/
|
||||
lpa = mii_read(macp, MII_LPA);
|
||||
|
||||
/* Check on link speed.*/
|
||||
if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
|
||||
supp = EMAC_SUPP_SPEED;
|
||||
else
|
||||
supp = 0;
|
||||
|
||||
/* Check on link mode.*/
|
||||
if (lpa & (LPA_10FULL | LPA_100FULL)) {
|
||||
mac2 |= EMAC_MAC2_FULL_DUPLEX;
|
||||
cmd |= EMAC_COMMAND_FULL_DUPLEX;
|
||||
ipgt = LPC17XX_MAC_IPGT_FULL_DUPLEX_DEF;
|
||||
}
|
||||
else {
|
||||
mac2 &= ~EMAC_MAC2_FULL_DUPLEX;
|
||||
cmd &= ~EMAC_COMMAND_FULL_DUPLEX;
|
||||
ipgt = LPC17XX_MAC_IPGT_HALF_DUPLEX_DEF;
|
||||
}
|
||||
}
|
||||
else {
|
||||
/* Link must be established.*/
|
||||
if (!(bmsr & BMSR_LSTATUS))
|
||||
return macp->link_up = FALSE;
|
||||
|
||||
/* Check on link speed.*/
|
||||
if (bmcr & BMCR_SPEED100)
|
||||
supp = EMAC_SUPP_SPEED;
|
||||
else
|
||||
supp = 0;
|
||||
|
||||
/* Check on link mode.*/
|
||||
if (bmcr & BMCR_FULLDPLX) {
|
||||
mac2 |= EMAC_MAC2_FULL_DUPLEX;
|
||||
cmd |= EMAC_COMMAND_FULL_DUPLEX;
|
||||
ipgt = LPC17XX_MAC_IPGT_FULL_DUPLEX_DEF;
|
||||
}
|
||||
else {
|
||||
mac2 &= ~EMAC_MAC2_FULL_DUPLEX;
|
||||
cmd &= ~EMAC_COMMAND_FULL_DUPLEX;
|
||||
ipgt = LPC17XX_MAC_IPGT_HALF_DUPLEX_DEF;
|
||||
}
|
||||
}
|
||||
|
||||
LPC_EMAC->MAC2 = mac2;
|
||||
LPC_EMAC->SUPP = supp;
|
||||
LPC_EMAC->Command = cmd;
|
||||
LPC_EMAC->IPGT = ipgt;
|
||||
|
||||
/* Returns the link status.*/
|
||||
return macp->link_up = TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes to a transmit descriptor's stream.
|
||||
*
|
||||
* @param[in] tdp pointer to a @p MACTransmitDescriptor structure
|
||||
* @param[in] buf pointer to the buffer containing the data to be
|
||||
* written
|
||||
* @param[in] size number of bytes to be written
|
||||
* @return The number of bytes written into the descriptor's
|
||||
* stream, this value can be less than the amount
|
||||
* specified in the parameter @p size if the maximum
|
||||
* frame size is reached.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
|
||||
uint8_t *buf,
|
||||
size_t size) {
|
||||
|
||||
if (size > tdp->size - tdp->offset)
|
||||
size = tdp->size - tdp->offset;
|
||||
|
||||
if (size > 0) {
|
||||
memcpy((uint8_t *)td_tmp[tdp->txdescn].packet + tdp->offset, buf, size);
|
||||
tdp->offset += size;
|
||||
}
|
||||
return size;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads from a receive descriptor's stream.
|
||||
*
|
||||
* @param[in] rdp pointer to a @p MACReceiveDescriptor structure
|
||||
* @param[in] buf pointer to the buffer that will receive the read data
|
||||
* @param[in] size number of bytes to be read
|
||||
* @return The number of bytes read from the descriptor's
|
||||
* stream, this value can be less than the amount
|
||||
* specified in the parameter @p size if there are
|
||||
* no more bytes to read.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
|
||||
uint8_t *buf,
|
||||
size_t size) {
|
||||
|
||||
if (size > rdp->size - rdp->offset)
|
||||
size = rdp->size - rdp->offset;
|
||||
|
||||
if (size > 0) {
|
||||
memcpy(buf, (uint8_t *)rd[rdp->rxdescn].packet + rdp->offset, size);
|
||||
rdp->offset += size;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Returns a pointer to the next transmit buffer in the descriptor
|
||||
* chain.
|
||||
* @note The API guarantees that enough buffers can be requested to fill
|
||||
* a whole frame.
|
||||
*
|
||||
* @param[in] tdp pointer to a @p MACTransmitDescriptor structure
|
||||
* @param[in] size size of the requested buffer. Specify the frame size
|
||||
* on the first call then scale the value down subtracting
|
||||
* the amount of data already copied into the previous
|
||||
* buffers.
|
||||
* @param[out] sizep pointer to variable receiving the buffer size, it is
|
||||
* zero when the last buffer has already been returned.
|
||||
* Note that a returned size lower than the amount
|
||||
* requested means that more buffers must be requested
|
||||
* in order to fill the frame data entirely.
|
||||
* @return Pointer to the returned buffer.
|
||||
* @retval NULL if the buffer chain has been entirely scanned.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
|
||||
size_t size,
|
||||
size_t *sizep) {
|
||||
|
||||
if (tdp->offset == 0) {
|
||||
*sizep = tdp->size;
|
||||
tdp->offset = size;
|
||||
return (uint8_t *)td_tmp[tdp->txdescn].packet;
|
||||
}
|
||||
*sizep = 0;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns a pointer to the next receive buffer in the descriptor
|
||||
* chain.
|
||||
* @note The API guarantees that the descriptor chain contains a whole
|
||||
* frame.
|
||||
*
|
||||
* @param[in] rdp pointer to a @p MACReceiveDescriptor structure
|
||||
* @param[out] sizep pointer to variable receiving the buffer size, it is
|
||||
* zero when the last buffer has already been returned.
|
||||
* @return Pointer to the returned buffer.
|
||||
* @retval NULL if the buffer chain has been entirely scanned.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
|
||||
size_t *sizep) {
|
||||
|
||||
if (rdp->size > 0) {
|
||||
*sizep = rdp->size;
|
||||
rdp->offset = rdp->size;
|
||||
rdp->size = 0;
|
||||
return (uint8_t *)rd[rdp->rxdescn].packet;
|
||||
}
|
||||
*sizep = 0;
|
||||
return NULL;
|
||||
}
|
||||
#endif /* MAC_USE_ZERO_COPY */
|
||||
|
||||
#endif /* HAL_USE_MAC */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,661 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
This file has been contributed by:
|
||||
Marcin Jokel.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file LPC17xx/mac_lld.h
|
||||
* @brief LPC17xx low level MAC driver header.
|
||||
*
|
||||
* @addtogroup MAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _MAC_LLD_H_
|
||||
#define _MAC_LLD_H_
|
||||
|
||||
#if HAL_USE_MAC || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief This implementation supports the zero-copy mode API.
|
||||
*/
|
||||
#define MAC_SUPPORTS_ZERO_COPY TRUE
|
||||
|
||||
/**
|
||||
* @name MAC Configuration Register 1 bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_MAC1_RECEIVE_EN (1UL << 0)
|
||||
#define EMAC_MAC1_PASS_ALL_REC (1UL << 1)
|
||||
#define EMAC_MAC1_RX_FLOW_CTRL (1UL << 2)
|
||||
#define EMAC_MAC1_TX_FLOW_CTRL (1UL << 3)
|
||||
#define EMAC_MAC1_LOOPBACK (1UL << 4)
|
||||
#define EMAC_MAC1_RESET_TX (1UL << 8)
|
||||
#define EMAC_MAC1_RESET_MCS_TX (1UL << 9)
|
||||
#define EMAC_MAC1_RESET_RX (1UL << 10)
|
||||
#define EMAC_MAC1_RESET_MCS_RX (1UL << 11)
|
||||
#define EMAC_MAC1_SIM_RESET (1UL << 14)
|
||||
#define EMAC_MAC1_SOFT_RESET (1UL << 15)
|
||||
|
||||
/**
|
||||
* @name MAC Configuration Register 2 bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_MAC2_FULL_DUPLEX (1UL << 0)
|
||||
#define EMAC_MAC2_FRAME_LEN_CHECK (1UL << 1)
|
||||
#define EMAC_MAC2_HUGE_FRAME_EN (1UL << 2)
|
||||
#define EMAC_MAC2_DELAYED_CRC (1UL << 3)
|
||||
#define EMAC_MAC2_CRC_EN (1UL << 4)
|
||||
#define EMAC_MAC2_PAD_CRC_EN (1UL << 5)
|
||||
#define EMAC_MAC2_VLAN_PAN_EN (1UL << 6)
|
||||
#define EMAC_MAC2_AUTO_DET_PAD_EN (1UL << 7)
|
||||
#define EMAC_MAC2_PURE_PREA_ENF (1UL << 8)
|
||||
#define EMAC_MAC2_LONG_PRE_ENF (1UL << 9)
|
||||
#define EMAC_MAC2_NO_BACKOFF (1UL << 12)
|
||||
#define EMAC_MAC2_BACK_PRESSURE (1UL << 13)
|
||||
#define EMAC_MAC2_EXCESS_DEFFER (1UL << 14)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name PHY Support Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_SUPP_SPEED (1UL << 8)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Test Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_TEST_SHORTCUT_PAUSE_QUANTA (1UL << 0)
|
||||
#define EMAC_TEST_PAUSE (1UL << 1)
|
||||
#define EMAC_TEST_BACKPRESSURE (1UL << 2)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Test Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_TEST_SHORTCUT_PAUSE_QUANTA (1UL << 0)
|
||||
#define EMAC_TEST_PAUSE (1UL << 1)
|
||||
#define EMAC_TEST_BACKPRESSURE (1UL << 2)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name MII Mgmt Configuration Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_MCFG_SCAN_INCR (1UL << 0)
|
||||
#define EMAC_MCFG_SUPPRESS_PREAMBLE (1UL << 1)
|
||||
#define EMAC_MCFG_CLK_DIV_4 (1UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_6 (2UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_8 (3UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_10 (4UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_14 (5UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_20 (6UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_28 (7UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_36 (8UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_40 (9UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_44 (10UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_48 (11UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_52 (12UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_56 (13UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_60 (14UL << 2)
|
||||
#define EMAC_MCFG_CLK_DIV_64 (15UL << 2)
|
||||
#define EMAC_MCFG_RESET_MII_MGMT (1UL << 15)
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name MII Mgmt Command Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_MCMD_READ (1UL << 0)
|
||||
#define EMAC_MCMD_SCAN (1UL << 1)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name MIND MII Mgmt Indicators Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_MIND_BUSY (1UL << 0)
|
||||
#define EMAC_MIND_SCANNING (1UL << 1)
|
||||
#define EMAC_MIND_NOT_VALID (1UL << 2)
|
||||
#define EMAC_MIND_LINK_FAIL (1UL << 3)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Command Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_COMMAND_RX_ENABLE (1UL << 0)
|
||||
#define EMAC_COMMAND_TX_ENABLE (1UL << 1)
|
||||
#define EMAC_COMMAND_REG_RESET (1UL << 3)
|
||||
#define EMAC_COMMAND_TX_RESET (1UL << 4)
|
||||
#define EMAC_COMMAND_RX_RESET (1UL << 5)
|
||||
#define EMAC_COMMAND_PASS_RUN_FRAME (1UL << 6)
|
||||
#define EMAC_COMMAND_PASS_RX_FILTER (1UL << 7)
|
||||
#define EMAC_COMMAND_PASS_TX_FLOW_CTRL (1UL << 8)
|
||||
#define EMAC_COMMAND_RMII (1UL << 9)
|
||||
#define EMAC_COMMAND_FULL_DUPLEX (1UL << 10)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Status Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_STATUS_RX (1UL << 0)
|
||||
#define EMAC_STATUS_TX (1UL << 1)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Transmit Status Vector 0 Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_TSV0_CRC_ERROR (1UL << 0)
|
||||
#define EMAC_TSV0_LEN_CHECK_ERROR (1UL << 1)
|
||||
#define EMAC_TSV0_LEN_OUT_OF_RANGE (1UL << 2)
|
||||
#define EMAC_TSV0_DONE (1UL << 3)
|
||||
#define EMAC_TSV0_MULTICAST (1UL << 4)
|
||||
#define EMAC_TSV0_BROADCAST (1UL << 5)
|
||||
#define EMAC_TSV0_PACKET_DEFER (1UL << 6)
|
||||
#define EMAC_TSV0_EXCESSIVE_DEFER (1UL << 7)
|
||||
#define EMAC_TSV0_EXCESSIVE_COLLISION (1UL << 8)
|
||||
#define EMAC_TSV0_LATE_COLLISION (1UL << 9)
|
||||
#define EMAC_TSV0_GIANT (1UL << 10)
|
||||
#define EMAC_TSV0_UNDERRUN (1UL << 11)
|
||||
#define EMAC_TSV0_CONTROL_FRAME (1UL << 28)
|
||||
#define EMAC_TSV0_PAUSE (1UL << 29)
|
||||
#define EMAC_TSV0_BACKPRESSURE (1UL << 30)
|
||||
#define EMAC_TSV0_VLAN (1UL << 31)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Receive Status Vector Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_RSV_PACKET_PREV_IGN (1UL << 16)
|
||||
#define EMAC_RSV_RXDV_EVENT (1UL << 17)
|
||||
#define EMAC_RSV_CARRIER_EVENT (1UL << 18)
|
||||
#define EMAC_RSV_RECEIVE_CODE (1UL << 19)
|
||||
#define EMAC_RSV_CRC_ERROR (1UL << 20)
|
||||
#define EMAC_RSV_LEN_CHECK_ERROR (1UL << 21)
|
||||
#define EMAC_RSV_LEN_OUT_OF_RANGE (1UL << 22)
|
||||
#define EMAC_RSV_RECEIVE_OK (1UL << 23)
|
||||
#define EMAC_RSV_MULTICAST (1UL << 24)
|
||||
#define EMAC_RSV_BROADCAST (1UL << 25)
|
||||
#define EMAC_RSV_DRIBBLE_NIBBLE (1UL << 26)
|
||||
#define EMAC_RSV_CTRL_FRAME (1UL << 27)
|
||||
#define EMAC_RSV_PAUSE (1UL << 28)
|
||||
#define EMAC_RSV_UNSUPPORTED_OPCODE (1UL << 29)
|
||||
#define EMAC_RSV_VLAN (1UL << 30)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Receive Filter Control Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_RXFILCTRL_UNICAST_EN (1UL << 0)
|
||||
#define EMAC_RXFILCTRL_BROADCAST_EN (1UL << 1)
|
||||
#define EMAC_RXFILCTRL_MULTICAST_EN (1UL << 2)
|
||||
#define EMAC_RXFILCTRL_UNICAST_HASH_EN (1UL << 3)
|
||||
#define EMAC_RXFILCTRL_MULTICAST_HASH_EN (1UL << 4)
|
||||
#define EMAC_RXFILCTRL_PERFECT_EN (1UL << 5)
|
||||
#define EMAC_RXFILCTRL_MAGIC_PACKET_EN (1UL << 12)
|
||||
#define EMAC_RXFILCTRL_RX_FILTER_EN (1UL << 13)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Receive Filter WoL Status bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_RXFILWOLSTAT_UNICAST (1UL << 0)
|
||||
#define EMAC_RXFILWOLSTAT_BROADCAST (1UL << 1)
|
||||
#define EMAC_RXFILWOLSTAT_MULTICAST (1UL << 2)
|
||||
#define EMAC_RXFILWOLSTAT_UNICAST_HASH (1UL << 3)
|
||||
#define EMAC_RXFILWOLSTAT_MULTICAST_HASH (1UL << 4)
|
||||
#define EMAC_RXFILWOLSTAT_PERFECT (1UL << 5)
|
||||
#define EMAC_RXFILWOLSTAT_RX_FILTER (1UL << 7)
|
||||
#define EMAC_RXFILWOLSTAT_MAGIC_PACKET (1UL << 8)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Receive Filter WoL Clear bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_RXFILWOLCLR_UNICAST (1UL << 0)
|
||||
#define EMAC_RXFILWOLCLR_BROADCAST (1UL << 1)
|
||||
#define EMAC_RXFILWOLCLR_MULTICAST (1UL << 2)
|
||||
#define EMAC_RXFILWOLCLR_UNICAST_HASH (1UL << 3)
|
||||
#define EMAC_RXFILWOLCLR_MULTICAST_HASH (1UL << 4)
|
||||
#define EMAC_RXFILWOLCLR_PERFECT (1UL << 5)
|
||||
#define EMAC_RXFILWOLCLR_RX_FILTER (1UL << 7)
|
||||
#define EMAC_RXFILWOLCLR_MAGIC_PACKET (1UL << 8)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Interrupt Status Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_INTSTAT_RX_OVERRUN (1UL << 0)
|
||||
#define EMAC_INTSTAT_RX_ERROR (1UL << 1)
|
||||
#define EMAC_INTSTAT_RX_FINISHED (1UL << 2)
|
||||
#define EMAC_INTSTAT_RX_DONE (1UL << 3)
|
||||
#define EMAC_INTSTAT_TX_UNDERRUN (1UL << 4)
|
||||
#define EMAC_INTSTAT_TX_ERROR (1UL << 5)
|
||||
#define EMAC_INTSTAT_TX_FINISHED (1UL << 6)
|
||||
#define EMAC_INTSTAT_TX_DONE (1UL << 7)
|
||||
#define EMAC_INTSTAT_SOFT (1UL << 12)
|
||||
#define EMAC_INTSTAT_WAKEUP (1UL << 13)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Interrupt Enable Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_INTEN_RX_OVERRUN (1UL << 0)
|
||||
#define EMAC_INTEN_RX_ERROR (1UL << 1)
|
||||
#define EMAC_INTEN_RX_FINISHED (1UL << 2)
|
||||
#define EMAC_INTEN_RX_DONE (1UL << 3)
|
||||
#define EMAC_INTEN_TX_UNDERRUN (1UL << 4)
|
||||
#define EMAC_INTEN_TX_ERROR (1UL << 5)
|
||||
#define EMAC_INTEN_TX_FINISHED (1UL << 6)
|
||||
#define EMAC_INTEN_TX_DONE (1UL << 7)
|
||||
#define EMAC_INTEN_SOFT (1UL << 12)
|
||||
#define EMAC_INTEN_WAKEUP (1UL << 13)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Interrupt Clear Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_INTCLR_RX_OVERRUN (1UL << 0)
|
||||
#define EMAC_INTCLR_RX_ERROR (1UL << 1)
|
||||
#define EMAC_INTCLR_RX_FINISHED (1UL << 2)
|
||||
#define EMAC_INTCLR_RX_DONE (1UL << 3)
|
||||
#define EMAC_INTCLR_TX_UNDERRUN (1UL << 4)
|
||||
#define EMAC_INTCLR_TX_ERROR (1UL << 5)
|
||||
#define EMAC_INTCLR_TX_FINISHED (1UL << 6)
|
||||
#define EMAC_INTCLR_TX_DONE (1UL << 7)
|
||||
#define EMAC_INTCLR_SOFT (1UL << 12)
|
||||
#define EMAC_INTCLR_WAKEUP (1UL << 13)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Interrupt Set Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_INTSET_RX_OVERRUN (1UL << 0)
|
||||
#define EMAC_INTSET_RX_ERROR (1UL << 1)
|
||||
#define EMAC_INTSET_RX_FINISHED (1UL << 2)
|
||||
#define EMAC_INTSET_RX_DONE (1UL << 3)
|
||||
#define EMAC_INTSET_TX_UNDERRUN (1UL << 4)
|
||||
#define EMAC_INTSET_TX_ERROR (1UL << 5)
|
||||
#define EMAC_INTSET_TX_FINISHED (1UL << 6)
|
||||
#define EMAC_INTSET_TX_DONE (1UL << 7)
|
||||
#define EMAC_INTSET_SOFT (1UL << 12)
|
||||
#define EMAC_INTSET_WAKEUP (1UL << 13)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Power-Down Register bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_PWRDOWN_MAC_AHB (1UL << 31)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Receive Descriptor Control bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_RXSTATUS_CTRL_SIZE_MASK 0x000007FF
|
||||
#define EMAC_RXSTATUS_CTRL_LOCK (1UL << 11)
|
||||
#define EMAC_RXSTATUS_CTRL_READY (1UL << 12)
|
||||
#define EMAC_RXSTATUS_RELEASE (1UL << 12)
|
||||
#define EMAC_RXSTATUS_CTRL_INT (1UL << 31)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Receive Descriptor Status bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_RXSTATUS_INFO_SIZE_MASK 0x000007FF
|
||||
#define EMAC_RXSTATUS_INFO_CTRL_FRAME (1UL << 18)
|
||||
#define EMAC_RXSTATUS_INFO_VLAN (1UL << 19)
|
||||
#define EMAC_RXSTATUS_INFO_FAIL_FILTER (1UL << 20)
|
||||
#define EMAC_RXSTATUS_INFO_MULTICAST (1UL << 21)
|
||||
#define EMAC_RXSTATUS_INFO_BROADCAST (1UL << 22)
|
||||
#define EMAC_RXSTATUS_INFO_CRC_ERROR (1UL << 23)
|
||||
#define EMAC_RXSTATUS_INFO_SYMBOL_ERROR (1UL << 24)
|
||||
#define EMAC_RXSTATUS_INFO_LENGTH_ERROR (1UL << 25)
|
||||
#define EMAC_RXSTATUS_INFO_RANGE_ERROR (1UL << 26)
|
||||
#define EMAC_RXSTATUS_INFO_ALLIG_ERROR (1UL << 27)
|
||||
#define EMAC_RXSTATUS_INFO_OVERRUN (1UL << 28)
|
||||
#define EMAC_RXSTATUS_INFO_NO_DESCRIPTOR (1UL << 29)
|
||||
#define EMAC_RXSTATUS_INFO_LAST_FLAG (1UL << 30)
|
||||
#define EMAC_RXSTATUS_INFO_ERROR (1UL << 31)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Transmit Descriptor Control bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_TXSTATUS_CTRL_SIZE_MASK 0x000007FF
|
||||
#define EMAC_TXSTATUS_CTRL_LOCK (1UL << 11)
|
||||
#define EMAC_TXSTATUS_CTRL_OVERRIDE (1UL << 26)
|
||||
#define EMAC_TXSTATUS_CTRL_HUGE (1UL << 27)
|
||||
#define EMAC_TXSTATUS_CTRL_PAD (1UL << 28)
|
||||
#define EMAC_TXSTATUS_CTRL_CRC (1UL << 29)
|
||||
#define EMAC_TXSTATUS_CTRL_LAST (1UL << 30)
|
||||
#define EMAC_TXSTATUS_CTRL_INT (1UL << 31)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Transmit Descriptor Status bits
|
||||
* @{
|
||||
*/
|
||||
#define EMAC_RXSTATUS_INFO_COL_COUNT_MASK (0x0FUL << 21)
|
||||
#define EMAC_RXSTATUS_INFO_DEFER (1UL << 25)
|
||||
#define EMAC_RXSTATUS_INFO_EXC_DEFER (1UL << 26)
|
||||
#define EMAC_RXSTATUS_INFO_EXC_COL (1UL << 27)
|
||||
#define EMAC_RXSTATUS_INFO_LATE_COL (1UL << 28)
|
||||
#define EMAC_RXSTATUS_INFO_UNDERRUN (1UL << 29)
|
||||
#define EMAC_RXSTATUS_INFO_NO_DESC (1UL << 30)
|
||||
#define EMAC_RXSTATUS_INFO_ERROR (1UL << 31)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Collision Window / Retry register default value
|
||||
*/
|
||||
#define LPC17XX_MAC_CLRT_DEF 0x0000370F
|
||||
|
||||
/**
|
||||
* @brief Non Back-to-Back Inter-Packet-Gap register default value
|
||||
*/
|
||||
#define LPC17XX_MAC_IPGR_DEF 0x00000015
|
||||
|
||||
/**
|
||||
* @brief Back-to-Back Inter-Packet-Gap register default value
|
||||
*/
|
||||
#define LPC17XX_MAC_IPGT_FULL_DUPLEX_DEF 0x00000015
|
||||
#define LPC17XX_MAC_IPGT_HALF_DUPLEX_DEF 0x00000012
|
||||
|
||||
/** @} */
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Number of available transmit buffers.
|
||||
*/
|
||||
#if !defined(LPC17xx_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
|
||||
#define LPC17xx_MAC_TRANSMIT_BUFFERS 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Number of available receive buffers.
|
||||
*/
|
||||
#if !defined(LPC17xx_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
|
||||
#define LPC17xx_MAC_RECEIVE_BUFFERS 4
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Maximum supported frame size.
|
||||
*/
|
||||
#if !defined(LPC17xx_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define LPC17xx_MAC_BUFFERS_SIZE 1522
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PHY detection timeout.
|
||||
* @details Timeout, in milliseconds, for PHY address detection, if a PHY
|
||||
* is not detected within the timeout then the driver halts during
|
||||
* initialization. This setting applies only if the PHY address is
|
||||
* not explicitly set in the board header file using
|
||||
* @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a
|
||||
* single search path is performed.
|
||||
*/
|
||||
#if !defined(LPC17xx_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
|
||||
#define LPC17xx_MAC_PHY_TIMEOUT 100
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Change the PHY power state inside the driver.
|
||||
*/
|
||||
#if !defined(LPC17xx_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
|
||||
#define LPC17xx_MAC_ETH1_CHANGE_PHY_STATE TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ETHD1 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(LPC17xx_MAC_ETH_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define LPC17xx_MAC_ETH_IRQ_PRIORITY 13
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MAC number of ticks of delay after reset.
|
||||
*/
|
||||
#if !defined(LPC17XX_MAC_RESET_DELAY) || defined(__DOXYGEN__)
|
||||
#define LPC17XX_MAC_RESET_DELAY 100
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MAC maximum frame length.
|
||||
*/
|
||||
#if !defined(LPC17XX_MAC_MAX_FLEN) || defined(__DOXYGEN__)
|
||||
#define LPC17XX_MAC_MAX_FLEN 1536
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if (LPC17xx_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS
|
||||
#error "LPC17xx_MAC_PHY_TIMEOUT requires the realtime counter service"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Type of an LPC17xx Ethernet receive descriptor.
|
||||
*/
|
||||
typedef struct {
|
||||
volatile uint32_t packet;
|
||||
volatile uint32_t control;
|
||||
} lpc17xx_eth_rx_descriptor_t;
|
||||
|
||||
/**
|
||||
* @brief Type of an LPC17xx Ethernet transmit descriptor.
|
||||
*/
|
||||
typedef struct {
|
||||
volatile uint32_t packet;
|
||||
volatile uint32_t control;
|
||||
} lpc17xx_eth_tx_descriptor_t;
|
||||
|
||||
/**
|
||||
* @brief Type of an LPC17xx Ethernet receive status.
|
||||
*/
|
||||
typedef struct {
|
||||
volatile uint32_t info;
|
||||
volatile uint32_t hashcrc;
|
||||
} lpc17xx_eth_rx_status_t;
|
||||
|
||||
/**
|
||||
* @brief Type of an LPC17xx Ethernet transmit status.
|
||||
*/
|
||||
typedef volatile uint32_t lpc17xx_eth_tx_status_t;
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief MAC address.
|
||||
*/
|
||||
uint8_t *mac_address;
|
||||
/* End of the mandatory fields.*/
|
||||
} MACConfig;
|
||||
|
||||
/**
|
||||
* @brief Structure representing a MAC driver.
|
||||
*/
|
||||
struct MACDriver {
|
||||
/**
|
||||
* @brief Driver state.
|
||||
*/
|
||||
macstate_t state;
|
||||
/**
|
||||
* @brief Current configuration data.
|
||||
*/
|
||||
const MACConfig *config;
|
||||
/**
|
||||
* @brief Transmit semaphore.
|
||||
*/
|
||||
Semaphore tdsem;
|
||||
/**
|
||||
* @brief Receive semaphore.
|
||||
*/
|
||||
Semaphore rdsem;
|
||||
#if MAC_USE_EVENTS || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Receive event.
|
||||
*/
|
||||
EventSource rdevent;
|
||||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Link status flag.
|
||||
*/
|
||||
bool_t link_up;
|
||||
/**
|
||||
* @brief PHY address (pre shifted).
|
||||
*/
|
||||
uint32_t phyaddr;
|
||||
/**
|
||||
* @brief Software receive descriptor number.
|
||||
*/
|
||||
uint32_t rxsoftindex;
|
||||
/**
|
||||
* @brief Software transmit descriptor number.
|
||||
*/
|
||||
uint32_t txsoftindex;
|
||||
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Structure representing a transmit descriptor.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief Current write offset.
|
||||
*/
|
||||
size_t offset;
|
||||
/**
|
||||
* @brief Available space size.
|
||||
*/
|
||||
size_t size;
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Physical descriptor number.
|
||||
*/
|
||||
uint32_t txdescn;
|
||||
} MACTransmitDescriptor;
|
||||
|
||||
/**
|
||||
* @brief Structure representing a receive descriptor.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief Current read offset.
|
||||
*/
|
||||
size_t offset;
|
||||
/**
|
||||
* @brief Available data size.
|
||||
*/
|
||||
size_t size;
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Physical descriptor number.
|
||||
*/
|
||||
uint32_t rxdescn;
|
||||
} MACReceiveDescriptor;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern MACDriver ETHD1;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void mac_lld_init(void);
|
||||
void mac_lld_start(MACDriver *macp);
|
||||
void mac_lld_stop(MACDriver *macp);
|
||||
msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
|
||||
MACTransmitDescriptor *tdp);
|
||||
void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
|
||||
msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
|
||||
MACReceiveDescriptor *rdp);
|
||||
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
|
||||
bool_t mac_lld_poll_link_status(MACDriver *macp);
|
||||
size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
|
||||
uint8_t *buf,
|
||||
size_t size);
|
||||
size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
|
||||
uint8_t *buf,
|
||||
size_t size);
|
||||
|
||||
uint32_t mii_read(MACDriver *macp, uint32_t reg);
|
||||
void mii_write(MACDriver *macp, uint32_t reg, uint32_t value);
|
||||
void mii_find_phy(MACDriver *macp);
|
||||
#if MAC_USE_ZERO_COPY
|
||||
uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
|
||||
size_t size,
|
||||
size_t *sizep);
|
||||
const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
|
||||
size_t *sizep);
|
||||
#endif /* MAC_USE_ZERO_COPY */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_MAC */
|
||||
|
||||
#endif /* _MAC_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -8,7 +8,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC17xx/hal_lld.c \
|
|||
${CHIBIOS}/os/hal/platforms/LPC17xx/rtc_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/LPC17xx/i2c_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/LPC17xx/spi_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/LPC17xx/dac_lld.c
|
||||
${CHIBIOS}/os/hal/platforms/LPC17xx/dac_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/LPC17xx/mac_lld.c
|
||||
|
||||
|
||||
# Required include directories
|
||||
|
|
|
|||
|
|
@ -104,6 +104,15 @@ SECTIONS
|
|||
_etext = .;
|
||||
_textdata = _etext;
|
||||
|
||||
.eth_ram (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_eth_ram_start = .);
|
||||
*(.eth_ram)
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_eth_ram_end = .);
|
||||
} > ramahb
|
||||
|
||||
.stacks :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* LPC1766 memory setup.
|
||||
* LPC1769 memory setup.
|
||||
*/
|
||||
__main_stack_size__ = 0x0200;
|
||||
__process_stack_size__ = 0x0200;
|
||||
|
|
@ -104,6 +104,15 @@ SECTIONS
|
|||
_etext = .;
|
||||
_textdata = _etext;
|
||||
|
||||
.eth_ram (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_eth_ram_start = .);
|
||||
*(.eth_ram)
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_eth_ram_end = .);
|
||||
} > ramahb
|
||||
|
||||
.stacks :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
|
|
|
|||
Loading…
Reference in New Issue