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RCC DAC macros 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7978 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
Giovanni Di Sirio 2015-05-13 12:48:51 +00:00
parent 6da1914915
commit c0690a36e1
6 changed files with 200 additions and 1 deletions
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30
os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
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@ -198,6 +198,36 @@
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) #define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
/** @} */ /** @} */
/**
* @name DAC peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
/**
* @brief Disables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
/**
* @brief Resets the DAC1 peripheral.
*
* @api
*/
#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
/** @} */
/** /**
* @name PWR interface specific RCC operations * @name PWR interface specific RCC operations
* @{ * @{

30
os/hal/ports/STM32/STM32F1xx/stm32_rcc.h
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@ -198,6 +198,36 @@
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) #define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
/** @} */ /** @} */
/**
* @name DAC peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
/**
* @brief Disables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
/**
* @brief Resets the DAC1 peripheral.
*
* @api
*/
#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
/** @} */
/** /**
* @name Backup domain interface specific RCC operations * @name Backup domain interface specific RCC operations
* @{ * @{

55
os/hal/ports/STM32/STM32F37x/stm32_rcc.h
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@ -190,6 +190,61 @@
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) #define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
/** @} */ /** @} */
/**
* @name DAC peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DAC1EN, lp)
/**
* @brief Disables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DAC1EN, lp)
/**
* @brief Resets the DAC1 peripheral.
*
* @api
*/
#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DAC1RST)
/**
* @brief Enables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDAC2(lp) rccEnableAPB1(RCC_APB1ENR_DAC2EN, lp)
/**
* @brief Disables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableDAC2(lp) rccDisableAPB1(RCC_APB1ENR_DAC2EN, lp)
/**
* @brief Resets the DAC1 peripheral.
*
* @api
*/
#define rccResetDAC2() rccResetAPB1(RCC_APB1RSTR_DAC2RST)
/** @} */
/** /**
* @name CAN peripherals specific RCC operations * @name CAN peripherals specific RCC operations
* @{ * @{

55
os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
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@ -215,6 +215,61 @@
#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST) #define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
/** @} */ /** @} */
/**
* @name DAC peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DAC1EN, lp)
/**
* @brief Disables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DAC1EN, lp)
/**
* @brief Resets the DAC1 peripheral.
*
* @api
*/
#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DAC1RST)
/**
* @brief Enables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDAC2(lp) rccEnableAPB1(RCC_APB1ENR_DAC2EN, lp)
/**
* @brief Disables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableDAC2(lp) rccDisableAPB1(RCC_APB1ENR_DAC2EN, lp)
/**
* @brief Resets the DAC1 peripheral.
*
* @api
*/
#define rccResetDAC2() rccResetAPB1(RCC_APB1RSTR_DAC2RST)
/** @} */
/** /**
* @name CAN peripherals specific RCC operations * @name CAN peripherals specific RCC operations
* @{ * @{

1
os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
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@ -331,7 +331,6 @@
#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST) #define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
/** @} */ /** @} */
/** /**
* @name DAC peripheral specific RCC operations * @name DAC peripheral specific RCC operations
* @{ * @{

30
os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
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@ -202,6 +202,36 @@
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) #define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
/** @} */ /** @} */
/**
* @name DAC peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
/**
* @brief Disables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
/**
* @brief Resets the DAC1 peripheral.
*
* @api
*/
#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
/** @} */
/** /**
* @name DMA peripheral specific RCC operations * @name DMA peripheral specific RCC operations
* @{ * @{