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STM32F4x clock checks fixed according to RM0090.pdf 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4765 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
barthess 2012-10-21 15:00:18 +00:00
parent 560c8c2591
commit bf5ca6121e
1 changed files with 8 additions and 8 deletions
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16
os/hal/platforms/STM32F4xx/hal_lld.h
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@ -87,9 +87,9 @@
#define STM32_PLLIN_MAX 2000000 #define STM32_PLLIN_MAX 2000000
/** /**
* @brief Maximum PLLs input clock frequency. * @brief Minimum PLLs input clock frequency.
*/ */
#define STM32_PLLIN_MIN 950000 #define STM32_PLLIN_MIN 1000000
/** /**
* @brief Maximum PLLs VCO clock frequency. * @brief Maximum PLLs VCO clock frequency.
@ -97,9 +97,9 @@
#define STM32_PLLVCO_MAX 432000000 #define STM32_PLLVCO_MAX 432000000
/** /**
* @brief Maximum PLLs VCO clock frequency. * @brief Minimum PLLs VCO clock frequency.
*/ */
#define STM32_PLLVCO_MIN 192000000 #define STM32_PLLVCO_MIN 64000000
/** /**
* @brief Maximum PLL output clock frequency. * @brief Maximum PLL output clock frequency.
@ -210,7 +210,7 @@
#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */ #define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */
#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */ #define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */
#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */ #define STM32_I2SSRC_MASK (1 << 23) /**< I2SSRC mask. */
#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */ #define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */ #define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
@ -643,7 +643,7 @@
/** /**
* @brief PLLN multiplier value. * @brief PLLN multiplier value.
* @note The allowed values are 192..432. * @note The allowed values are 64..432.
* @note The default value is calculated for a 168MHz system clock from * @note The default value is calculated for a 168MHz system clock from
* an external 8MHz HSE clock. * an external 8MHz HSE clock.
*/ */
@ -663,7 +663,7 @@
/** /**
* @brief PLLQ multiplier value. * @brief PLLQ multiplier value.
* @note The allowed values are 4..15. * @note The allowed values are 2..15.
* @note The default value is calculated for a 168MHz system clock from * @note The default value is calculated for a 168MHz system clock from
* an external 8MHz HSE clock. * an external 8MHz HSE clock.
*/ */
@ -1011,7 +1011,7 @@
/** /**
* @brief STM32_PLLQ field. * @brief STM32_PLLQ field.
*/ */
#if ((STM32_PLLQ_VALUE >= 4) && (STM32_PLLQ_VALUE <= 15)) || \ #if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \
defined(__DOXYGEN__) defined(__DOXYGEN__)
#define STM32_PLLQ (STM32_PLLQ_VALUE << 24) #define STM32_PLLQ (STM32_PLLQ_VALUE << 24)
#else #else