From bf5ca6121e122e6dc522038e759715790058ded7 Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 21 Oct 2012 15:00:18 +0000
Subject: [PATCH] STM32F4x clock checks fixed according to RM0090.pdf

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4765 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.h | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index 0f19f07f2..90b23f139 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -87,9 +87,9 @@
 #define STM32_PLLIN_MAX         2000000
 
 /**
- * @brief   Maximum PLLs input clock frequency.
+ * @brief   Minimum PLLs input clock frequency.
  */
-#define STM32_PLLIN_MIN         950000
+#define STM32_PLLIN_MIN         1000000
 
 /**
  * @brief   Maximum PLLs VCO clock frequency.
@@ -97,9 +97,9 @@
 #define STM32_PLLVCO_MAX        432000000
 
 /**
- * @brief   Maximum PLLs VCO clock frequency.
+ * @brief   Minimum PLLs VCO clock frequency.
  */
-#define STM32_PLLVCO_MIN        192000000
+#define STM32_PLLVCO_MIN        64000000
 
 /**
  * @brief   Maximum PLL output clock frequency.
@@ -210,7 +210,7 @@
 #define STM32_MCO1SEL_HSE       (2 << 21)   /**< HSE clock on MCO1 pin.     */
 #define STM32_MCO1SEL_PLL       (3 << 21)   /**< PLL clock on MCO1 pin.     */
 
-#define STM32_I2SSRC_MASK       (1 << 23)   /**< I2CSRC mask.               */
+#define STM32_I2SSRC_MASK       (1 << 23)   /**< I2SSRC mask.               */
 #define STM32_I2SSRC_PLLI2S     (0 << 23)   /**< I2SSRC is PLLI2S.          */
 #define STM32_I2SSRC_CKIN       (1 << 23)   /**< I2S_CKIN is PLLI2S.        */
 
@@ -643,7 +643,7 @@
 
 /**
  * @brief   PLLN multiplier value.
- * @note    The allowed values are 192..432.
+ * @note    The allowed values are 64..432.
  * @note    The default value is calculated for a 168MHz system clock from
  *          an external 8MHz HSE clock.
  */
@@ -663,7 +663,7 @@
 
 /**
  * @brief   PLLQ multiplier value.
- * @note    The allowed values are 4..15.
+ * @note    The allowed values are 2..15.
  * @note    The default value is calculated for a 168MHz system clock from
  *          an external 8MHz HSE clock.
  */
@@ -1011,7 +1011,7 @@
 /**
  * @brief   STM32_PLLQ field.
  */
-#if ((STM32_PLLQ_VALUE >= 4) && (STM32_PLLQ_VALUE <= 15)) ||                \
+#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) ||                \
     defined(__DOXYGEN__)
 #define STM32_PLLQ                  (STM32_PLLQ_VALUE << 24)
 #else