Aligned mcuconf.h files for STM32F0xx devices. Removed obsolete settings, added DMA remapping settings.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8125 35acf78f-673a-0410-8e92-d51de3d6d3f4master
Giovanni Di Sirio
parent
b0b485d70c
commit
bbacae2118
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@ -41,6 +41,7 @@
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_HSI_ENABLED TRUE
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#define STM32_HSI14_ENABLED TRUE
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#define STM32_HSI48_ENABLED FALSE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSE_ENABLED FALSE
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@ -50,11 +51,8 @@
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#define STM32_PLLMUL_VALUE 12
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE STM32_PPRE_DIV1
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#define STM32_ADCSW STM32_ADCSW_HSI14
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_ADCSW STM32_ADCSW_HSI14
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#define STM32_USBSW STM32_USBSW_HSI48
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#define STM32_CECSW STM32_CECSW_HSI
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#define STM32_I2C1SW STM32_I2C1SW_HSI
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#define STM32_USART1SW STM32_USART1SW_PCLK
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@ -64,9 +62,10 @@
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* ADC driver system settings.
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*/
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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/*
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* EXT driver system settings.
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@ -101,6 +100,10 @@
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#define STM32_I2C_USE_DMA TRUE
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#define STM32_I2C_I2C1_DMA_PRIORITY 1
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#define STM32_I2C_I2C2_DMA_PRIORITY 1
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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@ -141,6 +144,10 @@
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 2
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#define STM32_SPI_SPI2_IRQ_PRIORITY 2
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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@ -158,6 +165,10 @@
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#define STM32_UART_USART2_IRQ_PRIORITY 3
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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#endif /* _MCUCONF_H_ */
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@ -50,11 +50,7 @@
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#define STM32_PLLMUL_VALUE 12
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE STM32_PPRE_DIV1
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#define STM32_ADCSW STM32_ADCSW_HSI14
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_ADCSW STM32_ADCSW_HSI14
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#define STM32_CECSW STM32_CECSW_HSI
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#define STM32_I2C1SW STM32_I2C1SW_HSI
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#define STM32_USART1SW STM32_USART1SW_PCLK
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@ -64,9 +60,10 @@
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* ADC driver system settings.
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*/
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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/*
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* EXT driver system settings.
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@ -98,6 +95,10 @@
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#define STM32_I2C_USE_DMA TRUE
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#define STM32_I2C_I2C1_DMA_PRIORITY 1
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#define STM32_I2C_I2C2_DMA_PRIORITY 1
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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@ -134,6 +135,10 @@
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 2
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#define STM32_SPI_SPI2_IRQ_PRIORITY 2
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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@ -151,6 +156,10 @@
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#define STM32_UART_USART2_IRQ_PRIORITY 3
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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#endif /* _MCUCONF_H_ */
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@ -41,6 +41,7 @@
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_HSI_ENABLED TRUE
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#define STM32_HSI14_ENABLED TRUE
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#define STM32_HSI48_ENABLED FALSE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSE_ENABLED FALSE
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@ -50,11 +51,8 @@
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#define STM32_PLLMUL_VALUE 12
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE STM32_PPRE_DIV1
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#define STM32_ADCSW STM32_ADCSW_HSI14
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_ADCSW STM32_ADCSW_HSI14
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#define STM32_USBSW STM32_USBSW_HSI48
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#define STM32_CECSW STM32_CECSW_HSI
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#define STM32_I2C1SW STM32_I2C1SW_HSI
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#define STM32_USART1SW STM32_USART1SW_PCLK
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@ -64,9 +62,10 @@
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* ADC driver system settings.
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*/
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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/*
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* EXT driver system settings.
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@ -101,6 +100,10 @@
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#define STM32_I2C_USE_DMA TRUE
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#define STM32_I2C_I2C1_DMA_PRIORITY 1
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#define STM32_I2C_I2C2_DMA_PRIORITY 1
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 2
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#define STM32_SPI_SPI2_IRQ_PRIORITY 2
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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#define STM32_UART_USART2_IRQ_PRIORITY 3
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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#endif /* _MCUCONF_H_ */
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#define STM32_PLLMUL_VALUE 12
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE STM32_PPRE_DIV1
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#define STM32_ADCSW STM32_ADCSW_HSI14
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_ADCSW STM32_ADCSW_HSI14
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#define STM32_USBSW STM32_USBSW_HSI48
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#define STM32_CECSW STM32_CECSW_HSI
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#define STM32_I2C1SW STM32_I2C1SW_HSI
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@ -65,10 +61,17 @@
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_USE_ADC1 TRUE
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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/*
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* CAN driver system settings.
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*/
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#define STM32_CAN_USE_CAN1 FALSE
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#define STM32_CAN_CAN1_IRQ_PRIORITY 3
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/*
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* EXT driver system settings.
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@ -103,6 +106,10 @@
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#define STM32_I2C_USE_DMA TRUE
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#define STM32_I2C_I2C1_DMA_PRIORITY 1
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#define STM32_I2C_I2C2_DMA_PRIORITY 1
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 2
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#define STM32_SPI_SPI2_IRQ_PRIORITY 2
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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#define STM32_UART_USART2_IRQ_PRIORITY 3
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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/* Clock settings.*/
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RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |
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STM32_ADCPRE | STM32_PPRE | STM32_HPRE;
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STM32_PPRE | STM32_HPRE;
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RCC->CFGR2 = STM32_PREDIV;
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RCC->CFGR3 = STM32_ADCSW | STM32_USBSW | STM32_CECSW |
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RCC->CFGR3 = STM32_USBSW | STM32_CECSW |
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STM32_I2C1SW | STM32_USART1SW;
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#if STM32_ACTIVATE_PLL
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* @brief Maximum APB clock frequency.
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*/
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#define STM32_PCLK_MAX 48000000
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/**
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* @brief Maximum ADC clock frequency.
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*/
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#define STM32_ADCCLK_MAX 14000000
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/** @} */
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/**
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#endif
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/**
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* @brief ADC prescaler value.
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*/
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#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#endif
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/**
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* @brief ADC clock source.
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*/
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#if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
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#define STM32_ADCSW STM32_ADCSW_HSI14
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#endif
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/**
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* @brief USB Clock source.
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*/
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#error "invalid source selected for RTC clock"
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#endif
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/**
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* @brief ADC frequency.
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*/
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#if (STM32_ADCSW == STM32_ADCSW_HSI14) || defined(__DOXYGEN__)
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#define STM32_ADCCLK STM32_HSI14CLK
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#elif STM32_ADCSW == STM32_ADCSW_PCLK
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#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
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#define STM32_ADCCLK (STM32_PCLK / 2)
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#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
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#define STM32_ADCCLK (STM32_PCLK / 4)
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#else
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#error "invalid STM32_ADCPRE value specified"
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#endif
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#else
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#error "invalid source selected for ADC clock"
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#endif
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/* ADC frequency check.*/
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#if STM32_ADCCLK > STM32_ADCCLK_MAX
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#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
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#endif
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/**
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* @brief USB frequency.
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*/
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_DAC1_CH1_DMA_CHN 0x00000000
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||||
#define STM32_HAS_DAC1_CH2 FALSE
|
||||
#define STM32_HAS_DAC2_CH1 FALSE
|
||||
|
|
@ -107,12 +108,16 @@
|
|||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_I2C2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_I2C2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
|
|
@ -128,12 +133,16 @@
|
|||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
|
|
@ -192,12 +201,18 @@
|
|||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
|
|
@ -254,19 +269,28 @@
|
|||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC1_CH1 TRUE
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_DAC1_CH1_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_DAC1_CH2 TRUE
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_DAC1_CH2_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_DAC2_CH1 FALSE
|
||||
#define STM32_HAS_DAC2_CH2 FALSE
|
||||
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
#define STM32_DMA_STREAMS 7
|
||||
#define STM32_DMA1_NUM_CHANNELS 7
|
||||
#define STM32_DMA1_CH1_HANDLER Vector64
|
||||
#define STM32_DMA1_CH23_HANDLER Vector68
|
||||
#define STM32_DMA1_CH4567_HANDLER Vector6C
|
||||
#define STM32_DMA1_CH1_NUMBER 9
|
||||
#define STM32_DMA1_CH23_NUMBER 10
|
||||
#define STM32_DMA1_CH4567_NUMBER 11
|
||||
|
||||
#define STM32_DMA2_NUM_CHANNELS 0
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
|
@ -294,12 +318,18 @@
|
|||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_I2C2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_I2C2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
|
|
@ -315,12 +345,18 @@
|
|||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
|
|
@ -379,18 +415,32 @@
|
|||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
||||
#define STM32_USART3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
||||
#define STM32_USART3_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
||||
#define STM32_UART4_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
||||
#define STM32_UART4_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
|
@ -452,9 +502,15 @@
|
|||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
#define STM32_DMA_STREAMS 5
|
||||
#define STM32_DMA1_NUM_CHANNELS 5
|
||||
#define STM32_DMA1_CH1_HANDLER Vector64
|
||||
#define STM32_DMA1_CH23_HANDLER Vector68
|
||||
#define STM32_DMA1_CH4567_HANDLER Vector6C
|
||||
#define STM32_DMA1_CH1_NUMBER 9
|
||||
#define STM32_DMA1_CH23_NUMBER 10
|
||||
#define STM32_DMA1_CH4567_NUMBER 11
|
||||
|
||||
#define STM32_DMA2_NUM_CHANNELS 0
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
|
@ -480,8 +536,10 @@
|
|||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C2 FALSE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
|
@ -498,12 +556,16 @@
|
|||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
|
|
@ -556,12 +618,18 @@
|
|||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
|
|
@ -621,9 +689,15 @@
|
|||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
#define STM32_DMA_STREAMS 5
|
||||
#define STM32_DMA1_NUM_CHANNELS 5
|
||||
#define STM32_DMA1_CH1_HANDLER Vector64
|
||||
#define STM32_DMA1_CH23_HANDLER Vector68
|
||||
#define STM32_DMA1_CH4567_HANDLER Vector6C
|
||||
#define STM32_DMA1_CH1_NUMBER 9
|
||||
#define STM32_DMA1_CH23_NUMBER 10
|
||||
#define STM32_DMA1_CH4567_NUMBER 11
|
||||
|
||||
#define STM32_DMA2_NUM_CHANNELS 0
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
|
@ -649,8 +723,10 @@
|
|||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C2 FALSE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
|
@ -667,8 +743,10 @@
|
|||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI2 FALSE
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
|
|
@ -722,8 +800,12 @@
|
|||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART2 FALSE
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
|
|
@ -782,9 +864,15 @@
|
|||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
#define STM32_DMA_STREAMS 5
|
||||
#define STM32_DMA1_NUM_CHANNELS 5
|
||||
#define STM32_DMA1_CH1_HANDLER Vector64
|
||||
#define STM32_DMA1_CH23_HANDLER Vector68
|
||||
#define STM32_DMA1_CH4567_HANDLER Vector6C
|
||||
#define STM32_DMA1_CH1_NUMBER 9
|
||||
#define STM32_DMA1_CH23_NUMBER 10
|
||||
#define STM32_DMA1_CH4567_NUMBER 11
|
||||
|
||||
#define STM32_DMA2_NUM_CHANNELS 0
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
|
@ -810,8 +898,10 @@
|
|||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C2 FALSE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
|
@ -828,8 +918,10 @@
|
|||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI2 FALSE
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
|
|
@ -883,12 +975,18 @@
|
|||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
|
|
@ -949,9 +1047,15 @@
|
|||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
#define STM32_DMA_STREAMS 5
|
||||
#define STM32_DMA1_NUM_CHANNELS 5
|
||||
#define STM32_DMA1_CH1_HANDLER Vector64
|
||||
#define STM32_DMA1_CH23_HANDLER Vector68
|
||||
#define STM32_DMA1_CH4567_HANDLER Vector6C
|
||||
#define STM32_DMA1_CH1_NUMBER 9
|
||||
#define STM32_DMA1_CH23_NUMBER 10
|
||||
#define STM32_DMA1_CH4567_NUMBER 11
|
||||
|
||||
#define STM32_DMA2_NUM_CHANNELS 0
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
|
@ -978,12 +1082,16 @@
|
|||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_I2C2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_I2C2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
|
|
@ -999,12 +1107,16 @@
|
|||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
|
|
@ -1060,20 +1172,30 @@
|
|||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#if defined(STM32F030xC)
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
|
||||
#define STM32_HAS_UART5 TRUE
|
||||
|
||||
#define STM32_HAS_USART6 TRUE
|
||||
#else
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#endif
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB FALSE
|
||||
|
|
@ -1125,9 +1247,15 @@
|
|||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
#define STM32_DMA_STREAMS 5
|
||||
#define STM32_DMA1_NUM_CHANNELS 5
|
||||
#define STM32_DMA1_CH1_HANDLER Vector64
|
||||
#define STM32_DMA1_CH23_HANDLER Vector68
|
||||
#define STM32_DMA1_CH4567_HANDLER Vector6C
|
||||
#define STM32_DMA1_CH1_NUMBER 9
|
||||
#define STM32_DMA1_CH23_NUMBER 10
|
||||
#define STM32_DMA1_CH4567_NUMBER 11
|
||||
|
||||
#define STM32_DMA2_NUM_CHANNELS 0
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
|
@ -1154,12 +1282,18 @@
|
|||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_I2C2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_I2C2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
|
|
@ -1175,12 +1309,18 @@
|
|||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
|
|
@ -1239,16 +1379,32 @@
|
|||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
||||
#define STM32_USART3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
||||
#define STM32_USART3_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
||||
#define STM32_UART4_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
||||
#define STM32_UART4_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_HSI14_ENABLED TRUE
|
||||
#define STM32_HSI48_ENABLED FALSE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_HSE_ENABLED FALSE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
|
|
@ -50,11 +51,8 @@
|
|||
#define STM32_PLLMUL_VALUE 12
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE STM32_PPRE_DIV1
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_USBSW STM32_USBSW_HSI48
|
||||
#define STM32_CECSW STM32_CECSW_HSI
|
||||
#define STM32_I2C1SW STM32_I2C1SW_HSI
|
||||
#define STM32_USART1SW STM32_USART1SW_PCLK
|
||||
|
|
@ -64,9 +62,10 @@
|
|||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 TRUE
|
||||
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
|
|
@ -101,6 +100,10 @@
|
|||
#define STM32_I2C_USE_DMA TRUE
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -141,6 +144,10 @@
|
|||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -158,6 +165,10 @@
|
|||
#define STM32_UART_USART2_IRQ_PRIORITY 3
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
|
|||
|
|
@ -51,11 +51,7 @@
|
|||
#define STM32_PLLMUL_VALUE 12
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE STM32_PPRE_DIV1
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_USBSW STM32_USBSW_HSI48
|
||||
#define STM32_CECSW STM32_CECSW_HSI
|
||||
#define STM32_I2C1SW STM32_I2C1SW_HSI
|
||||
|
|
@ -66,9 +62,10 @@
|
|||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
|
|
@ -109,6 +106,10 @@
|
|||
#define STM32_I2C_USE_DMA TRUE
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -135,7 +136,7 @@
|
|||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 TRUE
|
||||
#define STM32_SERIAL_USE_USART1 FALSE
|
||||
#define STM32_SERIAL_USE_USART2 FALSE
|
||||
#define STM32_SERIAL_USART1_PRIORITY 3
|
||||
#define STM32_SERIAL_USART2_PRIORITY 3
|
||||
|
|
@ -149,6 +150,10 @@
|
|||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -166,6 +171,10 @@
|
|||
#define STM32_UART_USART2_IRQ_PRIORITY 3
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_HSI14_ENABLED TRUE
|
||||
#define STM32_HSI48_ENABLED FALSE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_HSE_ENABLED FALSE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
|
|
@ -50,11 +51,8 @@
|
|||
#define STM32_PLLMUL_VALUE 12
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE STM32_PPRE_DIV1
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_USBSW STM32_USBSW_HSI48
|
||||
#define STM32_CECSW STM32_CECSW_HSI
|
||||
#define STM32_I2C1SW STM32_I2C1SW_HSI
|
||||
#define STM32_USART1SW STM32_USART1SW_PCLK
|
||||
|
|
@ -64,9 +62,10 @@
|
|||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
|
|
@ -101,6 +100,10 @@
|
|||
#define STM32_I2C_USE_DMA TRUE
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -141,6 +144,10 @@
|
|||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -158,6 +165,10 @@
|
|||
#define STM32_UART_USART2_IRQ_PRIORITY 3
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_HSI14_ENABLED TRUE
|
||||
#define STM32_HSI48_ENABLED FALSE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_HSE_ENABLED FALSE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
|
|
@ -50,11 +51,8 @@
|
|||
#define STM32_PLLMUL_VALUE 12
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE STM32_PPRE_DIV1
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_USBSW STM32_USBSW_HSI48
|
||||
#define STM32_CECSW STM32_CECSW_HSI
|
||||
#define STM32_I2C1SW STM32_I2C1SW_HSI
|
||||
#define STM32_USART1SW STM32_USART1SW_PCLK
|
||||
|
|
@ -64,9 +62,10 @@
|
|||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
|
|
@ -101,6 +100,10 @@
|
|||
#define STM32_I2C_USE_DMA TRUE
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -141,6 +144,10 @@
|
|||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -158,6 +165,10 @@
|
|||
#define STM32_UART_USART2_IRQ_PRIORITY 3
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_HSI14_ENABLED TRUE
|
||||
#define STM32_HSI48_ENABLED FALSE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_HSE_ENABLED FALSE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
|
|
@ -50,11 +51,8 @@
|
|||
#define STM32_PLLMUL_VALUE 12
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE STM32_PPRE_DIV1
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_USBSW STM32_USBSW_HSI48
|
||||
#define STM32_CECSW STM32_CECSW_HSI
|
||||
#define STM32_I2C1SW STM32_I2C1SW_HSI
|
||||
#define STM32_USART1SW STM32_USART1SW_PCLK
|
||||
|
|
@ -64,9 +62,10 @@
|
|||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
|
|
@ -101,6 +100,10 @@
|
|||
#define STM32_I2C_USE_DMA TRUE
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -141,6 +144,10 @@
|
|||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -158,6 +165,10 @@
|
|||
#define STM32_UART_USART2_IRQ_PRIORITY 3
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_HSI14_ENABLED TRUE
|
||||
#define STM32_HSI48_ENABLED FALSE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_HSE_ENABLED FALSE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
|
|
@ -50,11 +51,8 @@
|
|||
#define STM32_PLLMUL_VALUE 12
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE STM32_PPRE_DIV1
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_USBSW STM32_USBSW_HSI48
|
||||
#define STM32_CECSW STM32_CECSW_HSI
|
||||
#define STM32_I2C1SW STM32_I2C1SW_HSI
|
||||
#define STM32_USART1SW STM32_USART1SW_PCLK
|
||||
|
|
@ -64,9 +62,10 @@
|
|||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
|
|
@ -101,6 +100,10 @@
|
|||
#define STM32_I2C_USE_DMA TRUE
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -141,6 +144,10 @@
|
|||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -158,6 +165,10 @@
|
|||
#define STM32_UART_USART2_IRQ_PRIORITY 3
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_HSI14_ENABLED TRUE
|
||||
#define STM32_HSI48_ENABLED FALSE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_HSE_ENABLED FALSE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
|
|
@ -50,11 +51,8 @@
|
|||
#define STM32_PLLMUL_VALUE 12
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE STM32_PPRE_DIV1
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_USBSW STM32_USBSW_HSI48
|
||||
#define STM32_CECSW STM32_CECSW_HSI
|
||||
#define STM32_I2C1SW STM32_I2C1SW_HSI
|
||||
#define STM32_USART1SW STM32_USART1SW_PCLK
|
||||
|
|
@ -64,9 +62,10 @@
|
|||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
|
|
@ -101,6 +100,10 @@
|
|||
#define STM32_I2C_USE_DMA TRUE
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -141,6 +144,10 @@
|
|||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -158,6 +165,10 @@
|
|||
#define STM32_UART_USART2_IRQ_PRIORITY 3
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
|
|||
|
|
@ -51,11 +51,7 @@
|
|||
#define STM32_PLLMUL_VALUE 12
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE STM32_PPRE_DIV1
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_ADCSW STM32_ADCSW_HSI14
|
||||
#define STM32_USBSW STM32_USBSW_HSI48
|
||||
#define STM32_CECSW STM32_CECSW_HSI
|
||||
#define STM32_I2C1SW STM32_I2C1SW_HSI
|
||||
|
|
@ -65,10 +61,17 @@
|
|||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 TRUE
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 FALSE
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
|
|
@ -103,6 +106,10 @@
|
|||
#define STM32_I2C_USE_DMA TRUE
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -143,6 +150,10 @@
|
|||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
@ -160,6 +171,10 @@
|
|||
#define STM32_UART_USART2_IRQ_PRIORITY 3
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in New Issue