From bbacae2118c4c05a477d93ec0aa356e63442f6e2 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Wed, 29 Jul 2015 08:59:55 +0000 Subject: [PATCH] Aligned mcuconf.h files for STM32F0xx devices. Removed obsolete settings, added DMA remapping settings. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8125 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM32/NIL-STM32F051-DISCOVERY/mcuconf.h | 21 +- demos/STM32/RT-STM32F030R8-NUCLEO/mcuconf.h | 19 +- demos/STM32/RT-STM32F051-DISCOVERY/mcuconf.h | 21 +- demos/STM32/RT-STM32F072-DISCOVERY/mcuconf.h | 27 +- os/hal/ports/STM32/STM32F0xx/hal_lld.c | 4 +- os/hal/ports/STM32/STM32F0xx/hal_lld.h | 41 -- os/hal/ports/STM32/STM32F0xx/stm32_registry.h | 352 +++++++++++++----- testhal/STM32/STM32F0xx/ADC/mcuconf.h | 21 +- testhal/STM32/STM32F0xx/CAN/mcuconf.h | 21 +- testhal/STM32/STM32F0xx/EXT/mcuconf.h | 21 +- testhal/STM32/STM32F0xx/IRQ_STORM/mcuconf.h | 21 +- testhal/STM32/STM32F0xx/PWM-ICU/mcuconf.h | 21 +- testhal/STM32/STM32F0xx/SPI/mcuconf.h | 21 +- testhal/STM32/STM32F0xx/UART/mcuconf.h | 21 +- testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h | 27 +- 15 files changed, 455 insertions(+), 204 deletions(-) diff --git a/demos/STM32/NIL-STM32F051-DISCOVERY/mcuconf.h b/demos/STM32/NIL-STM32F051-DISCOVERY/mcuconf.h index 2a494b377..c5d61d726 100644 --- a/demos/STM32/NIL-STM32F051-DISCOVERY/mcuconf.h +++ b/demos/STM32/NIL-STM32F051-DISCOVERY/mcuconf.h @@ -41,6 +41,7 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI_ENABLED TRUE #define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE @@ -50,11 +51,8 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI #define STM32_USART1SW STM32_USART1SW_PCLK @@ -64,9 +62,10 @@ * ADC driver system settings. */ #define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) /* * EXT driver system settings. @@ -101,6 +100,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -141,6 +144,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -158,6 +165,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #endif /* _MCUCONF_H_ */ diff --git a/demos/STM32/RT-STM32F030R8-NUCLEO/mcuconf.h b/demos/STM32/RT-STM32F030R8-NUCLEO/mcuconf.h index b9f7a8c5b..73a87484f 100644 --- a/demos/STM32/RT-STM32F030R8-NUCLEO/mcuconf.h +++ b/demos/STM32/RT-STM32F030R8-NUCLEO/mcuconf.h @@ -50,11 +50,7 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI #define STM32_USART1SW STM32_USART1SW_PCLK @@ -64,9 +60,10 @@ * ADC driver system settings. */ #define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) /* * EXT driver system settings. @@ -98,6 +95,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -134,6 +135,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -151,6 +156,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #endif /* _MCUCONF_H_ */ diff --git a/demos/STM32/RT-STM32F051-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F051-DISCOVERY/mcuconf.h index 2a494b377..c5d61d726 100644 --- a/demos/STM32/RT-STM32F051-DISCOVERY/mcuconf.h +++ b/demos/STM32/RT-STM32F051-DISCOVERY/mcuconf.h @@ -41,6 +41,7 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI_ENABLED TRUE #define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE @@ -50,11 +51,8 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI #define STM32_USART1SW STM32_USART1SW_PCLK @@ -64,9 +62,10 @@ * ADC driver system settings. */ #define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) /* * EXT driver system settings. @@ -101,6 +100,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -141,6 +144,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -158,6 +165,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #endif /* _MCUCONF_H_ */ diff --git a/demos/STM32/RT-STM32F072-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F072-DISCOVERY/mcuconf.h index 95419bd1e..ac561cf71 100644 --- a/demos/STM32/RT-STM32F072-DISCOVERY/mcuconf.h +++ b/demos/STM32/RT-STM32F072-DISCOVERY/mcuconf.h @@ -51,11 +51,7 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 #define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI @@ -65,10 +61,17 @@ /* * ADC driver system settings. */ -#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 3 /* * EXT driver system settings. @@ -103,6 +106,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -143,6 +150,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -160,6 +171,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /* diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c index c472e11e9..bb230edcd 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c @@ -189,9 +189,9 @@ void stm32_clock_init(void) { /* Clock settings.*/ RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC | - STM32_ADCPRE | STM32_PPRE | STM32_HPRE; + STM32_PPRE | STM32_HPRE; RCC->CFGR2 = STM32_PREDIV; - RCC->CFGR3 = STM32_ADCSW | STM32_USBSW | STM32_CECSW | + RCC->CFGR3 = STM32_USBSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW; #if STM32_ACTIVATE_PLL diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/os/hal/ports/STM32/STM32F0xx/hal_lld.h index f15fb5173..d376efe95 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.h @@ -154,11 +154,6 @@ * @brief Maximum APB clock frequency. */ #define STM32_PCLK_MAX 48000000 - -/** - * @brief Maximum ADC clock frequency. - */ -#define STM32_ADCCLK_MAX 14000000 /** @} */ /** @@ -402,20 +397,6 @@ #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #endif -/** - * @brief ADC prescaler value. - */ -#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#endif - -/** - * @brief ADC clock source. - */ -#if !defined(STM32_ADCSW) || defined(__DOXYGEN__) -#define STM32_ADCSW STM32_ADCSW_HSI14 -#endif - /** * @brief USB Clock source. */ @@ -768,28 +749,6 @@ #error "invalid source selected for RTC clock" #endif -/** - * @brief ADC frequency. - */ -#if (STM32_ADCSW == STM32_ADCSW_HSI14) || defined(__DOXYGEN__) -#define STM32_ADCCLK STM32_HSI14CLK -#elif STM32_ADCSW == STM32_ADCSW_PCLK -#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) -#define STM32_ADCCLK (STM32_PCLK / 2) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 -#define STM32_ADCCLK (STM32_PCLK / 4) -#else -#error "invalid STM32_ADCPRE value specified" -#endif -#else -#error "invalid source selected for ADC clock" -#endif - -/* ADC frequency check.*/ -#if STM32_ADCCLK > STM32_ADCCLK_MAX -#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)" -#endif - /** * @brief USB frequency. */ diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h index 4a7798258..35e64026c 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h @@ -64,7 +64,8 @@ /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_DAC1_CH1_DMA_CHN 0x00000000 #define STM32_HAS_DAC1_CH2 FALSE #define STM32_HAS_DAC2_CH1 FALSE @@ -107,12 +108,16 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C3 FALSE @@ -128,12 +133,16 @@ /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE @@ -192,12 +201,18 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART2 TRUE -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_USART2_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART3 FALSE #define STM32_HAS_UART4 FALSE @@ -254,19 +269,28 @@ /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_DAC1_CH1_DMA_CHN 0x00000000 #define STM32_HAS_DAC1_CH2 TRUE -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_DAC1_CH2_DMA_CHN 0x00000000 #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE + /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE -#define STM32_DMA_STREAMS 7 +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector64 +#define STM32_DMA1_CH23_HANDLER Vector68 +#define STM32_DMA1_CH4567_HANDLER Vector6C +#define STM32_DMA1_CH1_NUMBER 9 +#define STM32_DMA1_CH23_NUMBER 10 +#define STM32_DMA1_CH4567_NUMBER 11 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -294,12 +318,18 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C3 FALSE @@ -315,12 +345,18 @@ /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE @@ -379,18 +415,32 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART2 TRUE -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_USART3_TX_DMA_CHN 0x00000000 #define STM32_HAS_UART4 TRUE -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_UART4_TX_DMA_CHN 0x00000000 #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE @@ -452,9 +502,15 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE -#define STM32_DMA_STREAMS 5 +#define STM32_DMA1_NUM_CHANNELS 5 +#define STM32_DMA1_CH1_HANDLER Vector64 +#define STM32_DMA1_CH23_HANDLER Vector68 +#define STM32_DMA1_CH4567_HANDLER Vector6C +#define STM32_DMA1_CH1_NUMBER 9 +#define STM32_DMA1_CH23_NUMBER 10 +#define STM32_DMA1_CH4567_NUMBER 11 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -480,8 +536,10 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C2 FALSE #define STM32_HAS_I2C3 FALSE @@ -498,12 +556,16 @@ /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE @@ -556,12 +618,18 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART2 TRUE -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_USART2_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART3 FALSE #define STM32_HAS_UART4 FALSE @@ -621,9 +689,15 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE -#define STM32_DMA_STREAMS 5 +#define STM32_DMA1_NUM_CHANNELS 5 +#define STM32_DMA1_CH1_HANDLER Vector64 +#define STM32_DMA1_CH23_HANDLER Vector68 +#define STM32_DMA1_CH4567_HANDLER Vector6C +#define STM32_DMA1_CH1_NUMBER 9 +#define STM32_DMA1_CH23_NUMBER 10 +#define STM32_DMA1_CH4567_NUMBER 11 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -649,8 +723,10 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C2 FALSE #define STM32_HAS_I2C3 FALSE @@ -667,8 +743,10 @@ /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI2 FALSE #define STM32_HAS_SPI3 FALSE @@ -722,8 +800,12 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART2 FALSE #define STM32_HAS_USART3 FALSE @@ -782,9 +864,15 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE -#define STM32_DMA_STREAMS 5 +#define STM32_DMA1_NUM_CHANNELS 5 +#define STM32_DMA1_CH1_HANDLER Vector64 +#define STM32_DMA1_CH23_HANDLER Vector68 +#define STM32_DMA1_CH4567_HANDLER Vector6C +#define STM32_DMA1_CH1_NUMBER 9 +#define STM32_DMA1_CH23_NUMBER 10 +#define STM32_DMA1_CH4567_NUMBER 11 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -810,8 +898,10 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C2 FALSE #define STM32_HAS_I2C3 FALSE @@ -828,8 +918,10 @@ /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI2 FALSE #define STM32_HAS_SPI3 FALSE @@ -883,12 +975,18 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART2 TRUE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_USART2_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART3 FALSE #define STM32_HAS_UART4 FALSE @@ -949,9 +1047,15 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE -#define STM32_DMA_STREAMS 5 +#define STM32_DMA1_NUM_CHANNELS 5 +#define STM32_DMA1_CH1_HANDLER Vector64 +#define STM32_DMA1_CH23_HANDLER Vector68 +#define STM32_DMA1_CH4567_HANDLER Vector6C +#define STM32_DMA1_CH1_NUMBER 9 +#define STM32_DMA1_CH23_NUMBER 10 +#define STM32_DMA1_CH4567_NUMBER 11 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -978,12 +1082,16 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C3 FALSE @@ -999,12 +1107,16 @@ /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE @@ -1060,20 +1172,30 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART2 TRUE -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_USART2_TX_DMA_CHN 0x00000000 +#if defined(STM32F030xC) #define STM32_HAS_USART3 TRUE - #define STM32_HAS_UART4 TRUE - #define STM32_HAS_UART5 TRUE - #define STM32_HAS_USART6 TRUE +#else +#define STM32_HAS_USART3 FALSE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE +#endif /* USB attributes.*/ #define STM32_HAS_USB FALSE @@ -1125,9 +1247,15 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE -#define STM32_DMA_STREAMS 5 +#define STM32_DMA1_NUM_CHANNELS 5 +#define STM32_DMA1_CH1_HANDLER Vector64 +#define STM32_DMA1_CH23_HANDLER Vector68 +#define STM32_DMA1_CH4567_HANDLER Vector6C +#define STM32_DMA1_CH1_NUMBER 9 +#define STM32_DMA1_CH23_NUMBER 10 +#define STM32_DMA1_CH4567_NUMBER 11 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -1154,12 +1282,18 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C3 FALSE @@ -1175,12 +1309,18 @@ /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE @@ -1239,16 +1379,32 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART2 TRUE -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_USART3_TX_DMA_CHN 0x00000000 #define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_UART4_TX_DMA_CHN 0x00000000 #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE diff --git a/testhal/STM32/STM32F0xx/ADC/mcuconf.h b/testhal/STM32/STM32F0xx/ADC/mcuconf.h index 18339018d..57cc0e77f 100644 --- a/testhal/STM32/STM32F0xx/ADC/mcuconf.h +++ b/testhal/STM32/STM32F0xx/ADC/mcuconf.h @@ -41,6 +41,7 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI_ENABLED TRUE #define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE @@ -50,11 +51,8 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI #define STM32_USART1SW STM32_USART1SW_PCLK @@ -64,9 +62,10 @@ * ADC driver system settings. */ #define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) /* * EXT driver system settings. @@ -101,6 +100,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -141,6 +144,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -158,6 +165,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #endif /* _MCUCONF_H_ */ diff --git a/testhal/STM32/STM32F0xx/CAN/mcuconf.h b/testhal/STM32/STM32F0xx/CAN/mcuconf.h index 8c812e3fe..0b5e9f9c5 100644 --- a/testhal/STM32/STM32F0xx/CAN/mcuconf.h +++ b/testhal/STM32/STM32F0xx/CAN/mcuconf.h @@ -51,11 +51,7 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 #define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI @@ -66,9 +62,10 @@ * ADC driver system settings. */ #define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) /* * CAN driver system settings. @@ -109,6 +106,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -135,7 +136,7 @@ /* * SERIAL driver system settings. */ -#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART1 FALSE #define STM32_SERIAL_USE_USART2 FALSE #define STM32_SERIAL_USART1_PRIORITY 3 #define STM32_SERIAL_USART2_PRIORITY 3 @@ -149,6 +150,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -166,6 +171,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /* diff --git a/testhal/STM32/STM32F0xx/EXT/mcuconf.h b/testhal/STM32/STM32F0xx/EXT/mcuconf.h index 2a8901048..3afbfc88f 100644 --- a/testhal/STM32/STM32F0xx/EXT/mcuconf.h +++ b/testhal/STM32/STM32F0xx/EXT/mcuconf.h @@ -41,6 +41,7 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI_ENABLED TRUE #define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE @@ -50,11 +51,8 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI #define STM32_USART1SW STM32_USART1SW_PCLK @@ -64,9 +62,10 @@ * ADC driver system settings. */ #define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) /* * EXT driver system settings. @@ -101,6 +100,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -141,6 +144,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -158,6 +165,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #endif /* _MCUCONF_H_ */ diff --git a/testhal/STM32/STM32F0xx/IRQ_STORM/mcuconf.h b/testhal/STM32/STM32F0xx/IRQ_STORM/mcuconf.h index b5fbc69f4..559a6ec12 100644 --- a/testhal/STM32/STM32F0xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32/STM32F0xx/IRQ_STORM/mcuconf.h @@ -41,6 +41,7 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI_ENABLED TRUE #define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE @@ -50,11 +51,8 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI #define STM32_USART1SW STM32_USART1SW_PCLK @@ -64,9 +62,10 @@ * ADC driver system settings. */ #define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) /* * EXT driver system settings. @@ -101,6 +100,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -141,6 +144,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -158,6 +165,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #endif /* _MCUCONF_H_ */ diff --git a/testhal/STM32/STM32F0xx/PWM-ICU/mcuconf.h b/testhal/STM32/STM32F0xx/PWM-ICU/mcuconf.h index 92e871a53..26c39712e 100644 --- a/testhal/STM32/STM32F0xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32/STM32F0xx/PWM-ICU/mcuconf.h @@ -41,6 +41,7 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI_ENABLED TRUE #define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE @@ -50,11 +51,8 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI #define STM32_USART1SW STM32_USART1SW_PCLK @@ -64,9 +62,10 @@ * ADC driver system settings. */ #define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) /* * EXT driver system settings. @@ -101,6 +100,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -141,6 +144,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -158,6 +165,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #endif /* _MCUCONF_H_ */ diff --git a/testhal/STM32/STM32F0xx/SPI/mcuconf.h b/testhal/STM32/STM32F0xx/SPI/mcuconf.h index ac30427b4..8fa797035 100644 --- a/testhal/STM32/STM32F0xx/SPI/mcuconf.h +++ b/testhal/STM32/STM32F0xx/SPI/mcuconf.h @@ -41,6 +41,7 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI_ENABLED TRUE #define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE @@ -50,11 +51,8 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI #define STM32_USART1SW STM32_USART1SW_PCLK @@ -64,9 +62,10 @@ * ADC driver system settings. */ #define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) /* * EXT driver system settings. @@ -101,6 +100,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -141,6 +144,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -158,6 +165,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #endif /* _MCUCONF_H_ */ diff --git a/testhal/STM32/STM32F0xx/UART/mcuconf.h b/testhal/STM32/STM32F0xx/UART/mcuconf.h index 760abd643..f8e6250d2 100644 --- a/testhal/STM32/STM32F0xx/UART/mcuconf.h +++ b/testhal/STM32/STM32F0xx/UART/mcuconf.h @@ -41,6 +41,7 @@ #define STM32_PLS STM32_PLS_LEV0 #define STM32_HSI_ENABLED TRUE #define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE @@ -50,11 +51,8 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI #define STM32_USART1SW STM32_USART1SW_PCLK @@ -64,9 +62,10 @@ * ADC driver system settings. */ #define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) /* * EXT driver system settings. @@ -101,6 +100,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -141,6 +144,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -158,6 +165,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #endif /* _MCUCONF_H_ */ diff --git a/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h b/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h index 0fa6fb9e4..35e91dd27 100644 --- a/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h +++ b/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h @@ -51,11 +51,7 @@ #define STM32_PLLMUL_VALUE 12 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 #define STM32_USBSW STM32_USBSW_HSI48 #define STM32_CECSW STM32_CECSW_HSI #define STM32_I2C1SW STM32_I2C1SW_HSI @@ -65,10 +61,17 @@ /* * ADC driver system settings. */ -#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 3 /* * EXT driver system settings. @@ -103,6 +106,10 @@ #define STM32_I2C_USE_DMA TRUE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -143,6 +150,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -160,6 +171,10 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /*