git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3292 35acf78f-673a-0410-8e92-d51de3d6d3f4
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cd04106a83
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b8ad6dbae6
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@ -178,6 +178,7 @@
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#define MII_DM9161_ID 0x0181b8a0
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#define MII_DM9161_ID 0x0181b8a0
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#define MII_AM79C875_ID 0x00225540
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#define MII_AM79C875_ID 0x00225540
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#define MII_KS8721_ID 0x00221610
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#define MII_KS8721_ID 0x00221610
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#define MII_STE101P_ID 0x00061C50
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#endif /* _MII_H_ */
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#endif /* _MII_H_ */
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@ -29,7 +29,7 @@
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#include "ch.h"
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#include "ch.h"
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#include "hal.h"
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#include "hal.h"
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#include "mii.h"
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#include "mii.h"
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#
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#if HAL_USE_MAC || defined(__DOXYGEN__)
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#if HAL_USE_MAC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/*===========================================================================*/
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@ -38,6 +38,20 @@
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#define BUFFER_SLICE ((((MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
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#define BUFFER_SLICE ((((MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
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/* MII divider optimal value.*/
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#if (STM32_HCLK >= 60000000)
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#define MACMIIDR_CR ETH_MACMIIAR_CR_Div42
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#elif (STM32_HCLK >= 35000000)
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#define MACMIIDR_CR ETH_MACMIIAR_CR_Div26
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#elif (STM32_HCLK >= 20000000)
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#define MACMIIDR_CR ETH_MACMIIAR_CR_Div16
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#else
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#error "STM32_HCLK below minimum frequency for ETH operations (20MHz)"
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#endif
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/* PHY address.*/
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#define MACMIIDR_PA (32 << 11)
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -64,6 +78,55 @@ static uint32_t tb[MAC_TRANSMIT_BUFFERS * BUFFER_SLICE];
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/* Driver local functions. */
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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* @brief Writes a PHY register.
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*
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* @param[in] reg register number
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* @param[in] value new register value
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*/
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static void mii_write_phy(uint16_t reg, uint16_t value) {
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uint32_t miiar;
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miiar = ETH->MACMIIAR | ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;
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miiar = (miiar & ~ETH_MACMIIAR_MR) | (reg << 6);
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ETH->MACMIIDR = value;
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ETH->MACMIIAR = miiar;
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while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)
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;
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}
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/**
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* @brief Reads a PHY register.
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*
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* @param[in] reg register number
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*/
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static uint16_t mii_read_phy(uint16_t reg) {
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uint32_t miiar;
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miiar = ETH->MACMIIAR | ETH_MACMIIAR_MB;
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miiar = (miiar & ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_MW)) | (reg << 6);
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ETH->MACMIIAR = miiar;
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while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)
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;
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return (uint16_t)ETH->MACMIIDR;
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}
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/**
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* @brief MII/RMII interface initialization.
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*/
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static void mii_init(void) {
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uint32_t i;
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for (i = 0; i < 31; i++) {
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ETH->MACMIIDR = (i << 6) | MACMIIDR_CR;
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if ((mii_read_phy(MII_PHYSID1) == (PHY_ID >> 16)) &&
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(mii_read_phy(MII_PHYSID2) == (PHY_ID & 0xFFF0)))
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return;
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}
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/* Wrong or defective board.*/
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chSysHalt();
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}
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -121,6 +184,9 @@ void mac_lld_start(MACDriver *macp) {
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while (ETH->DMABMR & ETH_DMABMR_SR)
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while (ETH->DMABMR & ETH_DMABMR_SR)
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;
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;
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/* MII initialization.*/
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mii_init();
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/* Descriptor chains pointers.*/
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/* Descriptor chains pointers.*/
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ETH->DMARDLAR = (uint32_t)rd;
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ETH->DMARDLAR = (uint32_t)rd;
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ETH->DMATDLAR = (uint32_t)rd;
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ETH->DMATDLAR = (uint32_t)rd;
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