git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4534 35acf78f-673a-0410-8e92-d51de3d6d3f4
parent
0775f8a0df
commit
b736858c5b
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@ -39,14 +39,8 @@ const PALConfig pal_default_config =
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
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{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
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VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}
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{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
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VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
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};
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};
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#endif
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#endif
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@ -34,16 +34,17 @@
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/*
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/*
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* Board oscillators-related settings.
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* Board oscillators-related settings.
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* NOTE: LSE not fitted.
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* NOTE: HSE not fitted.
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*/
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*/
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#if !defined(STM32_LSECLK)
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#if !defined(STM32_LSECLK)
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#define STM32_LSECLK 0
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#define STM32_LSECLK 32768
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#endif
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#endif
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#if !defined(STM32_HSECLK)
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000
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#define STM32_HSECLK 0
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#endif
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#endif
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#define STM32_HSE_BYPASS
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/*
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/*
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* MCU type as defined in the ST header file stm32l1xx.h.
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* MCU type as defined in the ST header file stm32l1xx.h.
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@ -7,9 +7,9 @@
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<board_id>ST_STM32L_DISCOVERY</board_id>
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<board_id>ST_STM32L_DISCOVERY</board_id>
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<board_functions></board_functions>
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<board_functions></board_functions>
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<clocks
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<clocks
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HSEFrequency="8000000"
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HSEFrequency="0"
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HSEBypass="false"
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HSEBypass="true"
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LSEFrequency="0" />
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LSEFrequency="32768" />
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<ports>
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<ports>
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<GPIOA>
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<GPIOA>
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<pin0
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<pin0
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@ -46,7 +46,7 @@ const PALConfig pal_default_config =
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}
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};
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};
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#endif
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#endif
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@ -47,14 +47,8 @@ const PALConfig pal_default_config =
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
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{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
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VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}
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{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
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VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
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};
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};
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#endif
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#endif
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