AT91SAM7A3. I2C basic support added.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4819 35acf78f-673a-0410-8e92-d51de3d6d3f4master
barthess
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5649879b0a
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af931af9e5
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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Concepts and parts of this file have been contributed by Uladzimir Pylinsky
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aka barthess.
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*/
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/**
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* @file SAM7/i2c_lld.c
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* @brief SAM7 I2C subsystem low level driver source.
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* @note I2C peripheral interrupts on SAM7 platform must have highest
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* priority in system.
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*
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* @addtogroup I2C
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_I2C || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief I2C1 driver identifier.*/
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#if SAM7_I2C_USE_I2C1 || defined(__DOXYGEN__)
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I2CDriver I2CD1;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Wakes up the waiting thread.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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* @param[in] msg wakeup message
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*
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* @notapi
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*/
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#define wakeup_isr(i2cp, msg) { \
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chSysLockFromIsr(); \
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if ((i2cp)->thread != NULL) { \
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Thread *tp = (i2cp)->thread; \
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(i2cp)->thread = NULL; \
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tp->p_u.rdymsg = (msg); \
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chSchReadyI(tp); \
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} \
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chSysUnlockFromIsr(); \
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}
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/**
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* @brief Helper function.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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static void _i2c_lld_serve_rx_interrupt(I2CDriver *i2cp){
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if (i2cp->rxbytes == 1)
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AT91C_BASE_TWI->TWI_CR |= AT91C_TWI_STOP;
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*(i2cp->rxbuf) = AT91C_BASE_TWI->TWI_RHR;
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i2cp->rxbuf++;
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i2cp->rxbytes--;
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if (i2cp->rxbytes == 0){
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AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_RXRDY;
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AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXCOMP;
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}
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}
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/**
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* @brief Helper function.
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* @note During write operation you do not need to set STOP manually.
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* It sets automatically when THR and shift registers becomes empty.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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static void _i2c_lld_serve_tx_interrupt(I2CDriver *i2cp){
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if (i2cp->txbytes == 0){
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AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXRDY;
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AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXCOMP;
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}
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else{
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AT91C_BASE_TWI->TWI_THR = *(i2cp->txbuf);
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i2cp->txbuf++;
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i2cp->txbytes--;
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}
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}
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/**
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* @brief I2C shared ISR code.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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static void i2c_lld_serve_interrupt(I2CDriver *i2cp) {
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uint32_t sr;
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sr = AT91C_BASE_TWI->TWI_SR;
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/* this masking doing in official Atmel driver. Is it needed ??? */
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sr &= AT91C_BASE_TWI->TWI_IMR;
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if (sr & AT91C_TWI_NACK){
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i2cp->errors |= I2CD_ACK_FAILURE;
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wakeup_isr(i2cp, RDY_RESET);
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return;
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}
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if (sr & AT91C_TWI_RXRDY){
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_i2c_lld_serve_rx_interrupt(i2cp);
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}
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else if (sr & AT91C_TWI_TXRDY){
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_i2c_lld_serve_tx_interrupt(i2cp);
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}
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else if (sr & AT91C_TWI_TXCOMP){
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AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXCOMP;
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wakeup_isr(i2cp, RDY_OK);
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}
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else
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chDbgPanic("Invalid value");
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if SAM7_I2C_USE_I2C1 || defined(__DOXYGEN__)
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/**
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* @brief I2C1 event interrupt handler.
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*
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* @notapi
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*/
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CH_IRQ_HANDLER(TWI_IRQHandler) {
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CH_IRQ_PROLOGUE();
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i2c_lld_serve_interrupt(&I2CD1);
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AT91C_BASE_AIC->AIC_EOICR = 0;
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_I2C_USE_I2C1 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level I2C driver initialization.
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*
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* @notapi
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*/
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void i2c_lld_init(void) {
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#if SAM7_I2C_USE_I2C1
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i2cObjectInit(&I2CD1);
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I2CD1.thread = NULL;
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I2CD1.txbuf = NULL;
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I2CD1.rxbuf = NULL;
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I2CD1.txbytes = 0;
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I2CD1.rxbytes = 0;
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AT91C_BASE_PIOA->PIO_PDR = AT91C_PA0_TWD | AT91C_PA1_TWCK;
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AT91C_BASE_PIOA->PIO_ASR = AT91C_PA0_TWD | AT91C_PA1_TWCK;
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AT91C_BASE_PIOA->PIO_MDER = AT91C_PA0_TWD | AT91C_PA1_TWCK;
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AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PA0_TWD | AT91C_PA1_TWCK;
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AIC_ConfigureIT(AT91C_ID_TWI,
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AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, TWI_IRQHandler);
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#endif /* STM32_I2C_USE_I2C1 */
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}
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/**
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* @brief Configures and activates the I2C peripheral.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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void i2c_lld_start(I2CDriver *i2cp) {
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volatile uint32_t fake;
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/* If in stopped state then enables the I2C clocks.*/
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if (i2cp->state == I2C_STOP) {
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#if SAM7_I2C_USE_I2C1
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if (&I2CD1 == i2cp) {
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/* enable peripheral clock */
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TWI);
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/* Enables associated interrupt vector.*/
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AIC_EnableIT(AT91C_ID_TWI);
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/* Reset */
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AT91C_BASE_TWI->TWI_CR = AT91C_TWI_SWRST;
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fake = AT91C_BASE_TWI->TWI_RHR;
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/* Set master mode */
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AT91C_BASE_TWI->TWI_CR = AT91C_TWI_MSDIS;
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AT91C_BASE_TWI->TWI_CR = AT91C_TWI_MSEN;
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/* Setup I2C parameters. */
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AT91C_BASE_TWI->TWI_CWGR = i2cp->config->cwgr;
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}
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#endif /* STM32_I2C_USE_I2C1 */
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}
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(void)fake;
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}
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/**
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* @brief Deactivates the I2C peripheral.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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void i2c_lld_stop(I2CDriver *i2cp) {
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/* If not in stopped state then disables the I2C clock.*/
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if (i2cp->state != I2C_STOP) {
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#if SAM7_I2C_USE_I2C1
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if (&I2CD1 == i2cp) {
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AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXCOMP | AT91C_TWI_RXRDY |
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AT91C_TWI_TXRDY | AT91C_TWI_NACK;
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AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_TWI);
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AIC_DisableIT(AT91C_ID_TWI);
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}
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#endif
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}
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}
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/**
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* @brief Receives data via the I2C bus as master.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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* @param[in] addr slave device address
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* @param[out] rxbuf pointer to the receive buffer
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* @param[in] rxbytes number of bytes to be received
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* @param[in] timeout this value is ignored on SAM7 platform.
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* .
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* @return The operation status.
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* @retval RDY_OK if the function succeeded.
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* @retval RDY_RESET if one or more I2C errors occurred, the errors can
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* be retrieved using @p i2cGetErrors().
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*
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* @notapi
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*/
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msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
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uint8_t *rxbuf, size_t rxbytes,
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systime_t timeout) {
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(void)timeout;
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/* delete trash from RHR*/
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volatile uint32_t fake;
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fake = AT91C_BASE_TWI->TWI_RHR;
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(void)fake;
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/* Initializes driver fields.*/
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i2cp->rxbuf = rxbuf;
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i2cp->rxbytes = rxbytes;
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i2cp->txbuf = NULL;
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i2cp->txbytes = 0;
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/* tune master mode register */
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AT91C_BASE_TWI->TWI_MMR = 0;
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AT91C_BASE_TWI->TWI_MMR |= (addr << 16) | AT91C_TWI_MREAD;
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/* enable just needed interrupts */
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AT91C_BASE_TWI->TWI_IER = AT91C_TWI_RXRDY | AT91C_TWI_NACK;
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/* In single data byte master read or write, the START and STOP must both be set. */
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uint32_t cr = AT91C_TWI_START;
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if (rxbytes == 1)
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cr |= AT91C_TWI_STOP;
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AT91C_BASE_TWI->TWI_CR = cr;
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/* Waits for the operation completion.*/
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i2cp->thread = chThdSelf();
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chSchGoSleepS(THD_STATE_SUSPENDED);
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return chThdSelf()->p_u.rdymsg;
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}
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/**
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* @brief Transmits data via the I2C bus as master.
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* @details When performing reading through write you can not write more than
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* 3 bytes of data to I2C slave. This is SAM7 platform limitation.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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* @param[in] addr slave device address
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* @param[in] txbuf pointer to the transmit buffer
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* @param[in] txbytes number of bytes to be transmitted
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* @param[out] rxbuf pointer to the receive buffer
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* @param[in] rxbytes number of bytes to be received
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* @param[in] timeout this value is ignored on SAM7 platform.
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* .
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* @return The operation status.
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* @retval RDY_OK if the function succeeded.
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* @retval RDY_RESET if one or more I2C errors occurred, the errors can
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* be retrieved using @p i2cGetErrors().
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*
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* @notapi
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*/
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msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
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const uint8_t *txbuf, size_t txbytes,
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uint8_t *rxbuf, size_t rxbytes,
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systime_t timeout) {
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(void)timeout;
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/* SAM7 specific check */
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chDbgCheck(((rxbytes == 0) || ((txbytes > 0) && (txbytes < 4) && (rxbuf != NULL))),
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"i2c_lld_master_transmit_timeout");
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/* prepare to read through write operation */
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if (rxbytes > 0){
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AT91C_BASE_TWI->TWI_MMR |= txbytes << 8;
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/* store internal slave address in TWI_IADR registers */
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AT91C_BASE_TWI->TWI_IADR = 0;
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while (txbytes > 0){
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AT91C_BASE_TWI->TWI_IADR = (AT91C_BASE_TWI->TWI_IADR << 8);
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AT91C_BASE_TWI->TWI_IADR |= *(txbuf++);
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txbytes--;
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}
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/* Internal address of I2C slave was set in special Atmel registers.
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* Now we must call read function. The I2C cell automatically sends
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* bytes from IADR register to bus and issues repeated start. */
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return i2c_lld_master_receive_timeout(i2cp, addr, rxbuf, rxbytes, timeout);
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}
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else{
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if (txbytes == 1){
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/* In single data byte master read or write, the START and STOP
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* must both be set. */
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||||||
|
AT91C_BASE_TWI->TWI_CR |= AT91C_TWI_STOP;
|
||||||
|
}
|
||||||
|
AT91C_BASE_TWI->TWI_MMR = 0;
|
||||||
|
AT91C_BASE_TWI->TWI_MMR |= addr << 16;
|
||||||
|
|
||||||
|
/* enable just needed interrupts */
|
||||||
|
AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXRDY | AT91C_TWI_NACK;
|
||||||
|
|
||||||
|
/* correct size and pointer because first byte will be written
|
||||||
|
* for issue start condition */
|
||||||
|
i2cp->txbuf = txbuf + 1;
|
||||||
|
i2cp->txbytes = txbytes - 1;
|
||||||
|
|
||||||
|
/* According to datasheet there is no need to set START manually
|
||||||
|
* we just need to write first byte in THR */
|
||||||
|
AT91C_BASE_TWI->TWI_THR = txbuf[0];
|
||||||
|
|
||||||
|
/* Waits for the operation completion.*/
|
||||||
|
i2cp->thread = chThdSelf();
|
||||||
|
chSchGoSleepS(THD_STATE_SUSPENDED);
|
||||||
|
|
||||||
|
return chThdSelf()->p_u.rdymsg;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* HAL_USE_I2C */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,208 @@
|
||||||
|
/*
|
||||||
|
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||||
|
2011,2012 Giovanni Di Sirio.
|
||||||
|
|
||||||
|
This file is part of ChibiOS/RT.
|
||||||
|
|
||||||
|
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
Concepts and parts of this file have been contributed by Uladzimir Pylinsky
|
||||||
|
aka barthess.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file SAM72/i2c_lld.h
|
||||||
|
* @brief SAM72 I2C subsystem low level driver header.
|
||||||
|
*
|
||||||
|
* @addtogroup I2C
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _I2C_LLD_H_
|
||||||
|
#define _I2C_LLD_H_
|
||||||
|
|
||||||
|
#if HAL_USE_I2C || defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver constants. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Peripheral clock frequency.
|
||||||
|
*/
|
||||||
|
#define I2C_CLK_FREQ ((STM32_PCLK1) / 1000000)
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver pre-compile time settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Configuration options
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief I2C1 driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for I2C1 is included.
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#if !defined(SAM7_I2C_USE_I2C1) || defined(__DOXYGEN__)
|
||||||
|
#define SAM7_I2C_USE_I2C1 FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief I2C1 interrupt priority level setting.
|
||||||
|
*/
|
||||||
|
#if !defined(SAM7_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
|
#define SAM7_I2C_I2C1_IRQ_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Derived constants and error checks. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/** @brief error checks */
|
||||||
|
#if !SAM7_I2C_USE_I2C1
|
||||||
|
#error "I2C driver activated but no I2C peripheral assigned"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver data structures and types. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Type representing I2C address.
|
||||||
|
*/
|
||||||
|
typedef uint16_t i2caddr_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief I2C Driver condition flags type.
|
||||||
|
*/
|
||||||
|
typedef uint32_t i2cflags_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Driver configuration structure.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
/**
|
||||||
|
* @brief CWGR regitster content.
|
||||||
|
*/
|
||||||
|
uint32_t cwgr;
|
||||||
|
} I2CConfig;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Type of a structure representing an I2C driver.
|
||||||
|
*/
|
||||||
|
typedef struct I2CDriver I2CDriver;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Structure representing an I2C driver.
|
||||||
|
*/
|
||||||
|
struct I2CDriver{
|
||||||
|
/**
|
||||||
|
* @brief Driver state.
|
||||||
|
*/
|
||||||
|
i2cstate_t state;
|
||||||
|
/**
|
||||||
|
* @brief Current configuration data.
|
||||||
|
*/
|
||||||
|
const I2CConfig *config;
|
||||||
|
/**
|
||||||
|
* @brief Error flags.
|
||||||
|
*/
|
||||||
|
i2cflags_t errors;
|
||||||
|
/**
|
||||||
|
* @brief Pointer to receive buffer.
|
||||||
|
*/
|
||||||
|
uint8_t *rxbuf;
|
||||||
|
/**
|
||||||
|
* @brief Pointer to transmit buffer.
|
||||||
|
*/
|
||||||
|
const uint8_t *txbuf;
|
||||||
|
/**
|
||||||
|
* @brief Bytes count to be received.
|
||||||
|
*/
|
||||||
|
size_t rxbytes;
|
||||||
|
/**
|
||||||
|
* @brief Bytes count to be transmitted.
|
||||||
|
*/
|
||||||
|
size_t txbytes;
|
||||||
|
#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
||||||
|
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief Mutex protecting the bus.
|
||||||
|
*/
|
||||||
|
Mutex mutex;
|
||||||
|
#elif CH_USE_SEMAPHORES
|
||||||
|
Semaphore semaphore;
|
||||||
|
#endif
|
||||||
|
#endif /* I2C_USE_MUTUAL_EXCLUSION */
|
||||||
|
#if defined(I2C_DRIVER_EXT_FIELDS)
|
||||||
|
I2C_DRIVER_EXT_FIELDS
|
||||||
|
#endif
|
||||||
|
/* End of the mandatory fields.*/
|
||||||
|
/**
|
||||||
|
* @brief Thread waiting for I/O completion.
|
||||||
|
*/
|
||||||
|
Thread *thread;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver macros. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get errors from I2C driver.
|
||||||
|
*
|
||||||
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* External declarations. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
#if SAM7_I2C_USE_I2C1
|
||||||
|
extern I2CDriver I2CD1;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !defined(__DOXYGEN__) */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
void i2c_lld_init(void);
|
||||||
|
void i2c_lld_start(I2CDriver *i2cp);
|
||||||
|
void i2c_lld_stop(I2CDriver *i2cp);
|
||||||
|
msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||||||
|
const uint8_t *txbuf, size_t txbytes,
|
||||||
|
uint8_t *rxbuf, size_t rxbytes,
|
||||||
|
systime_t timeout);
|
||||||
|
msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||||||
|
uint8_t *rxbuf, size_t rxbytes,
|
||||||
|
systime_t timeout);
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* HAL_USE_I2C */
|
||||||
|
|
||||||
|
#endif /* _I2C_LLD_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -1,6 +1,7 @@
|
||||||
# List of all the AT91SAM7 platform files.
|
# List of all the AT91SAM7 platform files.
|
||||||
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AT91SAM7/hal_lld.c \
|
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AT91SAM7/hal_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/AT91SAM7/pal_lld.c \
|
${CHIBIOS}/os/hal/platforms/AT91SAM7/pal_lld.c \
|
||||||
|
${CHIBIOS}/os/hal/platforms/AT91SAM7/i2c_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/AT91SAM7/ext_lld.c \
|
${CHIBIOS}/os/hal/platforms/AT91SAM7/ext_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/AT91SAM7/serial_lld.c \
|
${CHIBIOS}/os/hal/platforms/AT91SAM7/serial_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/AT91SAM7/spi_lld.c \
|
${CHIBIOS}/os/hal/platforms/AT91SAM7/spi_lld.c \
|
||||||
|
|
|
||||||
|
|
@ -133,6 +133,7 @@
|
||||||
(backported to 2.4.3).
|
(backported to 2.4.3).
|
||||||
- FIX: Fixed STM8L, cosmic compiler: c_lreg not saved (bug 3566342)(backported
|
- FIX: Fixed STM8L, cosmic compiler: c_lreg not saved (bug 3566342)(backported
|
||||||
to 2.2.10 and 2.4.3).
|
to 2.2.10 and 2.4.3).
|
||||||
|
- NEW: AT91SAM7A3 I2C support.
|
||||||
- NEW: AT91SAM7A3 basic support.
|
- NEW: AT91SAM7A3 basic support.
|
||||||
- NEW: Unified the STM32F4xx and STM32F2xx platform code. The STM32F2xx now is
|
- NEW: Unified the STM32F4xx and STM32F2xx platform code. The STM32F2xx now is
|
||||||
only supported as an STM32F4xx variant and not tested separately.
|
only supported as an STM32F4xx variant and not tested separately.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue