diff --git a/ports/ARMCM3/nvic.c b/ports/ARMCM3/nvic.c
index a054ed163..4a11cbb39 100644
--- a/ports/ARMCM3/nvic.c
+++ b/ports/ARMCM3/nvic.c
@@ -17,11 +17,19 @@
     along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 
+/**
+ * @file ports/ARMCM3/nvic.c
+ * @brief Cortex-M3 NVIC support code.
+ * @addtogroup ARMCM3_NVIC
+ * @{
+ */
+
 #include <ch.h>
 #include <nvic.h>
 
 /**
- * Sets the priority of an interrupt handler and enables it.
+ * @brief Sets the priority of an interrupt handler and enables it.
+ *
  * @param n the interrupt number
  * @param prio the interrupt priority
  * @note The parameters are not tested for correctness.
@@ -34,7 +42,8 @@ void NVICEnableVector(uint32_t n, uint32_t prio) {
 }
 
 /**
- * Changes the priority of a system handler.
+ * @brief Changes the priority of a system handler.
+ *
  * @param handler the system handler number
  * @param prio the system handler priority
  * @note The parameters are not tested for correctness.
@@ -44,3 +53,5 @@ void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
 
   SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) & ~(0xFF << sh)) | (prio << sh);
 }
+
+/** @} */
diff --git a/ports/ARMCM3/nvic.h b/ports/ARMCM3/nvic.h
index 3876410e5..9d2b79606 100644
--- a/ports/ARMCM3/nvic.h
+++ b/ports/ARMCM3/nvic.h
@@ -17,31 +17,48 @@
     along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 
+/**
+ * @file ports/ARMCM3/nvic.h
+ * @brief Cortex-M3 NVIC support macros and structures.
+ * @addtogroup ARMCM3_NVIC
+ * @{
+ */
+
 #ifndef _NVIC_H_
 #define _NVIC_H_
 
 /*
  * System vector constants for @p NVICSetSystemHandlerPriority().
  */
-#define HANDLER_MEM_MANAGE      0
-#define HANDLER_BUS_FAULT       1
-#define HANDLER_USAGE_FAULT     2
+#define HANDLER_MEM_MANAGE      0       /**< MEM MANAGE vector id.*/
+#define HANDLER_BUS_FAULT       1       /**< BUS FAULT vector id.*/
+#define HANDLER_USAGE_FAULT     2       /**< USAGE FAULT vector id.*/
 #define HANDLER_RESERVED_3      3
 #define HANDLER_RESERVED_4      4
 #define HANDLER_RESERVED_5      5
 #define HANDLER_RESERVED_6      6
-#define HANDLER_SVCALL          7
-#define HANDLER_DEBUG_MONITOR   8
+#define HANDLER_SVCALL          7       /**< SVCALL vector id.*/
+#define HANDLER_DEBUG_MONITOR   8       /**< DEBUG MONITOR vector id.*/
 #define HANDLER_RESERVED_9      9
-#define HANDLER_PENDSV          10
-#define HANDLER_SYSTICK         11
+#define HANDLER_PENDSV          10      /**< PENDSV vector id.*/
+#define HANDLER_SYSTICK         11      /**< SYS TCK vector id.*/
 
-typedef volatile unsigned char IOREG8;
-typedef volatile unsigned int IOREG32;
+typedef volatile unsigned char IOREG8;  /**< 8 bits I/O register type.*/
+typedef volatile unsigned int IOREG32;  /**< 32 bits I/O register type.*/
 
+/**
+ * @brief NVIC ITCR register.
+ */
 #define NVIC_ITCR               (*((IOREG32 *)0xE000E004))
+
+/**
+ * @brief NVIC STIR register.
+ */
 #define NVIC_STIR               (*((IOREG32 *)0xE000EF00))
 
+/**
+ * @brief Structure representing the SYSTICK I/O space.
+ */
 typedef struct {
   IOREG32       CSR;
   IOREG32       RVR;
@@ -49,6 +66,9 @@ typedef struct {
   IOREG32       CBVR;
 } CM3_ST;
 
+/**
+ * @brief SYSTICK peripheral base address.
+ */
 #define STBase                  ((CM3_ST *)0xE000E010)
 #define ST_CSR                  (STBase->CSR)
 #define ST_RVR                  (STBase->RVR)
@@ -74,6 +94,9 @@ typedef struct {
 #define CBVR_SKEW_MASK          (0x1 << 30)
 #define CBVR_NOREF_MASK         (0x1 << 31)
 
+/**
+ * @brief Structure representing the NVIC I/O space.
+ */
 typedef struct {
   IOREG32       ISER[8];
   IOREG32       unused1[24];
@@ -88,6 +111,9 @@ typedef struct {
   IOREG32       IPR[60];
 } CM3_NVIC;
 
+/**
+ * @brief NVIC peripheral base address.
+ */
 #define NVICBase                ((CM3_NVIC *)0xE000E100)
 #define NVIC_ISER(n)            (NVICBase->ISER[n])
 #define NVIC_ICER(n)            (NVICBase->ICER[n])
@@ -96,6 +122,9 @@ typedef struct {
 #define NVIC_IABR(n)            (NVICBase->IABR[n])
 #define NVIC_IPR(n)             (NVICBase->IPR[n])
 
+/**
+ * @brief Structure representing the System Control Block I/O space.
+ */
 typedef struct {
   IOREG32       CPUID;
   IOREG32       ICSR;
@@ -113,6 +142,9 @@ typedef struct {
   IOREG32       AFSR;
 } CM3_SCB;
 
+/**
+ * @brief SCB peripheral base address.
+ */
 #define SCBBase                 ((CM3_SCB *)0xE000ED00)
 #define SCB_CPUID               (SCBBase->CPUID)
 #define SCB_ICSR                (SCBBase->ICSR)
@@ -154,3 +186,5 @@ extern "C" {
 #endif
 
 #endif /* _NVIC_H_ */
+
+/** @} */
diff --git a/ports/ARMCM3/port.dox b/ports/ARMCM3/port.dox
index c1776669d..9756427d5 100644
--- a/ports/ARMCM3/port.dox
+++ b/ports/ARMCM3/port.dox
@@ -102,8 +102,14 @@
  * @brief ARM Cortex-M3 specific port code, structures and macros.
  *
  * @ingroup ARMCM3
- * @file ports/ARMCM3/chtypes.h Port types.
- * @file ports/ARMCM3/chcore.h Port related structures and macros.
- * @file ports/ARMCM3/chcore.c Port related code.
+ */
+/** @} */
+
+/**
+ * @defgroup ARMCM3_NVIC NVIC support
+ * @{
+ * @brief ARM Cortex-M3 NVIC support.
+ *
+ * @ingroup ARMCM3_CORE
  */
 /** @} */