diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c
index 94ab4fe2b..12e8e3329 100644
--- a/os/hal/platforms/STM32F4xx/adc_lld.c
+++ b/os/hal/platforms/STM32F4xx/adc_lld.c
@@ -270,7 +270,8 @@ void adc_lld_start(ADCDriver *adcp) {
 
     /* This is a common register but apparently it requires that at least one
        of the ADCs is clocked in order to allow writing, see bug 3575297.*/
-    ADC->CCR = STM32_ADC_ADCPRE << 16;
+    ADC->CCR = (ADC->CCR & (ADC_CCR_TSVREFE | ADC_CCR_VBATE)) |
+               (STM32_ADC_ADCPRE << 16);
 
     /* ADC initial setup, starting the analog part here in order to reduce
        the latency when starting a conversion.*/
diff --git a/readme.txt b/readme.txt
index f9649a73d..5d838de69 100644
--- a/readme.txt
+++ b/readme.txt
@@ -88,6 +88,8 @@
 *** 2.5.2 ***
 - FIX: Fixed spurious interrupt disabling an STM32 DMA stream (bug 3607518)
   (backported to 2.4.4).
+- FIX: Fixed start of any ADC disables VREF and VBAT (bug 3607467)
+  (backported to 2.4.4).
 - FIX: Fixed surprising non-CRLF lines in source (bug 3607380).
 - FIX: Fixed no entry point defined at link time (bug 3607319).
 - FIX: Fixed sdc_lld_collect_errors does not collect errors (bug 3606743).