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RTC. Code cleanups. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3594 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
barthess 2011-12-11 18:14:30 +00:00
parent 3a0e138e7e
commit a8115a6060
1 changed files with 4 additions and 3 deletions
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7
os/hal/platforms/STM32/RTCv1/rtc_lld.c
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@ -138,7 +138,6 @@ void rtc_lld_init(void){
while (!(RCC->BDCR & RCC_BDCR_LSERDY)) while (!(RCC->BDCR & RCC_BDCR_LSERDY))
; ;
} }
preload = STM32_LSECLK - 1;
#elif STM32_RTC == STM32_RTC_LSI #elif STM32_RTC == STM32_RTC_LSI
#define RTC_CLK STM32_LSICLK #define RTC_CLK STM32_LSICLK
/* TODO: Move the LSI clock initialization in the HAL low level driver.*/ /* TODO: Move the LSI clock initialization in the HAL low level driver.*/
@ -151,12 +150,12 @@ void rtc_lld_init(void){
volatile uint32_t tmo = (STM32_SYSCLK / 1000000) * 100; volatile uint32_t tmo = (STM32_SYSCLK / 1000000) * 100;
while (tmo--) while (tmo--)
; ;
preload = STM32_LSICLK - 1;
#elif STM32_RTC == STM32_RTC_HSE #elif STM32_RTC == STM32_RTC_HSE
#define RTC_CLK (STM32_HSECLK / 128) #define RTC_CLK (STM32_HSECLK / 128)
preload = (STM32_HSECLK / 128) - 1;
#endif #endif
preload = RTC_CLK - 1;
/* Selects clock source (previously enabled and stabilized).*/ /* Selects clock source (previously enabled and stabilized).*/
RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTC; RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTC;
@ -226,8 +225,10 @@ void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
uint32_t time_frac; uint32_t time_frac;
READ_REGISTERS: READ_REGISTERS:
chSysLock();
timespec->tv_sec = ((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL; timespec->tv_sec = ((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL;
time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL; time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL;
chSysUnlock();
/* If second counter updated between reading of integer and fractional parts /* If second counter updated between reading of integer and fractional parts
* we must reread both values. */ * we must reread both values. */