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Added I2S attributes to STM32 registry entries. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8457 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
Giovanni Di Sirio 2015-11-09 10:46:27 +00:00
parent eaf54ee27a
commit a77f1ee722
10 changed files with 333 additions and 8 deletions
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126
os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c
View File

@ -46,6 +46,14 @@
STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_TX_DMA_STREAM, \ STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_TX_DMA_STREAM, \
STM32_SPI2_TX_DMA_CHN) STM32_SPI2_TX_DMA_CHN)
#define I2S3_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_RX_DMA_STREAM, \
STM32_SPI3_RX_DMA_CHN)
#define I2S3_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_TX_DMA_STREAM, \
STM32_SPI3_TX_DMA_CHN)
/* /*
* Static I2S settings for I2S1. * Static I2S settings for I2S1.
*/ */
@ -84,7 +92,27 @@
#define STM32_I2S2_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \ #define STM32_I2S2_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
SPI_I2SCFGR_I2SCFG_0) SPI_I2SCFGR_I2SCFG_0)
#endif #endif
#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SP3_MODE) */ #endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
/*
* Static I2S settings for I2S3.
*/
#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE)
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG 0
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
#endif
#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
SPI_I2SCFGR_I2SCFG_0)
#endif
#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported variables. */ /* Driver exported variables. */
@ -100,6 +128,11 @@ I2SDriver I2SD1;
I2SDriver I2SD2; I2SDriver I2SD2;
#endif #endif
/** @brief I2S3 driver identifier.*/
#if STM32_I2S_USE_SPI3 || defined(__DOXYGEN__)
I2SDriver I2SD3;
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver local variables and types. */ /* Driver local variables and types. */
/*===========================================================================*/ /*===========================================================================*/
@ -109,7 +142,8 @@ I2SDriver I2SD2;
/*===========================================================================*/ /*===========================================================================*/
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) || \ #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) || \
STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__) STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || \
STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
/** /**
* @brief Shared end-of-rx service routine. * @brief Shared end-of-rx service routine.
* *
@ -141,7 +175,8 @@ static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) {
#endif #endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) || \ #if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) || \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__) STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
/** /**
* @brief Shared end-of-tx service routine. * @brief Shared end-of-tx service routine.
* *
@ -266,6 +301,46 @@ void i2s_lld_init(void) {
I2SD2.txdmamode = 0; I2SD2.txdmamode = 0;
#endif #endif
#endif #endif
#if STM32_I2S_USE_SPI3
i2sObjectInit(&I2SD3);
I2SD3.spi = SPI3;
I2SD3.cfg = STM32_I2S3_CFGR_CFG;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM);
I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD3.dmarx = NULL;
I2SD3.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM);
I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#else
I2SD3.dmatx = NULL;
I2SD3.txdmamode = 0;
#endif
#endif
} }
/** /**
@ -313,6 +388,7 @@ void i2s_lld_start(I2SDriver *i2sp) {
#endif #endif
} }
#endif #endif
#if STM32_I2S_USE_SPI2 #if STM32_I2S_USE_SPI2
if (&I2SD2 == i2sp) { if (&I2SD2 == i2sp) {
bool b; bool b;
@ -327,6 +403,8 @@ void i2s_lld_start(I2SDriver *i2sp) {
(void *)i2sp); (void *)i2sp);
osalDbgAssert(!b, "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CR1 = 0; i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_RXDMAEN; i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif #endif
@ -337,6 +415,42 @@ void i2s_lld_start(I2SDriver *i2sp) {
(void *)i2sp); (void *)i2sp);
osalDbgAssert(!b, "stream already allocated"); osalDbgAssert(!b, "stream already allocated");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
#endif
}
#endif
#if STM32_I2S_USE_SPI3
if (&I2SD3 == i2sp) {
bool b;
/* Enabling I2S unit clock.*/
rccEnableSPI3(FALSE);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
b = dmaStreamAllocate(i2sp->dmarx,
STM32_I2S_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
b = dmaStreamAllocate(i2sp->dmatx,
STM32_I2S_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(!b, "stream already allocated");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CR1 = 0; i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_TXDMAEN; i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
#endif #endif
@ -372,10 +486,16 @@ void i2s_lld_stop(I2SDriver *i2sp) {
if (&I2SD1 == i2sp) if (&I2SD1 == i2sp)
rccDisableSPI1(FALSE); rccDisableSPI1(FALSE);
#endif #endif
#if STM32_I2S_USE_SPI2 #if STM32_I2S_USE_SPI2
if (&I2SD2 == i2sp) if (&I2SD2 == i2sp)
rccDisableSPI2(FALSE); rccDisableSPI2(FALSE);
#endif #endif
#if STM32_I2S_USE_SPI3
if (&I2SD3 == i2sp)
rccDisableSPI3(FALSE);
#endif
} }
} }

87
os/hal/ports/STM32/LLD/SPIv2/i2s_lld.h
View File

@ -78,6 +78,15 @@
#define STM32_I2S_USE_SPI2 FALSE #define STM32_I2S_USE_SPI2 FALSE
#endif #endif
/**
* @brief I2S3 driver enable switch.
* @details If set to @p TRUE the support for I2S3 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_I2S_USE_SPI3) || defined(__DOXYGEN__)
#define STM32_I2S_USE_SPI3 FALSE
#endif
/** /**
* @brief I2S1 mode. * @brief I2S1 mode.
*/ */
@ -94,18 +103,33 @@
STM32_I2S_MODE_RX) STM32_I2S_MODE_RX)
#endif #endif
/**
* @brief I2S3 mode.
*/
#if !defined(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
#define STM32_I2S_SPI3_MODE (STM32_I2S_MODE_MASTER | \
STM32_I2S_MODE_RX)
#endif
/** /**
* @brief I2S1 interrupt priority level setting. * @brief I2S1 interrupt priority level setting.
*/ */
#if !defined(STM32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) #if !defined(STM32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI1_IRQ_PRIORITY 2 #define STM32_I2S_SPI1_IRQ_PRIORITY 10
#endif #endif
/** /**
* @brief I2S2 interrupt priority level setting. * @brief I2S2 interrupt priority level setting.
*/ */
#if !defined(STM32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) #if !defined(STM32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI2_IRQ_PRIORITY 2 #define STM32_I2S_SPI2_IRQ_PRIORITY 10
#endif
/**
* @brief I2S3 interrupt priority level setting.
*/
#if !defined(STM32_I2S_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#endif #endif
/** /**
@ -122,6 +146,13 @@
#define STM32_I2S_SPI2_DMA_PRIORITY 1 #define STM32_I2S_SPI2_DMA_PRIORITY 1
#endif #endif
/**
* @brief I2S3 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_I2S_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#endif
/** /**
* @brief I2S DMA error hook. * @brief I2S DMA error hook.
*/ */
@ -134,6 +165,18 @@
/* Derived constants and error checks. */ /* Derived constants and error checks. */
/*===========================================================================*/ /*===========================================================================*/
#if STM32_I2S_USE_SPI1 && !STM32_SPI1_SUPPORTS_I2S
#error "SPI1 does not support I2S mode"
#endif
#if STM32_I2S_USE_SPI2 && !STM32_SPI2_SUPPORTS_I2S
#error "SPI2 does not support I2S mode"
#endif
#if STM32_I2S_USE_SPI3 && !STM32_SPI3_SUPPORTS_I2S
#error "SPI3 does not support I2S mode"
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) && \ #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) && \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
#error "I2S1 RX and TX mode not supported in this driver implementation" #error "I2S1 RX and TX mode not supported in this driver implementation"
@ -144,6 +187,11 @@
#error "I2S2 RX and TX mode not supported in this driver implementation" #error "I2S2 RX and TX mode not supported in this driver implementation"
#endif #endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) && \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
#error "I2S3 RX and TX mode not supported in this driver implementation"
#endif
#if STM32_I2S_USE_SPI1 && !STM32_HAS_SPI1 #if STM32_I2S_USE_SPI1 && !STM32_HAS_SPI1
#error "SPI1 not present in the selected device" #error "SPI1 not present in the selected device"
#endif #endif
@ -152,7 +200,11 @@
#error "SPI2 not present in the selected device" #error "SPI2 not present in the selected device"
#endif #endif
#if !STM32_I2S_USE_SPI1 && !STM32_I2S_USE_SPI2 #if STM32_I2S_USE_SPI3 && !STM32_HAS_SPI3
#error "SPI3 not present in the selected device"
#endif
#if !STM32_I2S_USE_SPI1 && !STM32_I2S_USE_SPI2 && !STM32_I2S_USE_SPI3
#error "I2S driver activated but no SPI peripheral assigned" #error "I2S driver activated but no SPI peripheral assigned"
#endif #endif
@ -166,6 +218,11 @@
#error "Invalid IRQ priority assigned to SPI2" #error "Invalid IRQ priority assigned to SPI2"
#endif #endif
#if STM32_I2S_USE_SPI3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI3"
#endif
#if STM32_I2S_USE_SPI1 && \ #if STM32_I2S_USE_SPI1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI1_DMA_PRIORITY) !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI1" #error "Invalid DMA priority assigned to SPI1"
@ -176,6 +233,11 @@
#error "Invalid DMA priority assigned to SPI2" #error "Invalid DMA priority assigned to SPI2"
#endif #endif
#if STM32_I2S_USE_SPI3 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI3_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI3"
#endif
/* The following checks are only required when there is a DMA able to /* The following checks are only required when there is a DMA able to
reassign streams to different channels.*/ reassign streams to different channels.*/
#if STM32_ADVANCED_DMA #if STM32_ADVANCED_DMA
@ -190,6 +252,11 @@
#error "SPI2 DMA streams not defined" #error "SPI2 DMA streams not defined"
#endif #endif
#if STM32_I2S_USE_SPI3 && (!defined(STM32_I2S_SPI3_RX_DMA_STREAM) || \
!defined(STM32_I2S_SPI3_TX_DMA_STREAM))
#error "SPI3 DMA streams not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/ /* Check on the validity of the assigned DMA channels.*/
#if STM32_I2S_USE_SPI1 && \ #if STM32_I2S_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
@ -210,6 +277,16 @@
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI2 TX" #error "invalid DMA stream associated to SPI2 TX"
#endif #endif
#if STM32_I2S_USE_SPI3 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI3 RX"
#endif
#if STM32_I2S_USE_SPI3 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI3 TX"
#endif
#endif /* STM32_ADVANCED_DMA */ #endif /* STM32_ADVANCED_DMA */
#if !defined(STM32_DMA_REQUIRED) #if !defined(STM32_DMA_REQUIRED)
@ -332,6 +409,10 @@ extern I2SDriver I2SD1;
extern I2SDriver I2SD2; extern I2SDriver I2SD2;
#endif #endif
#if STM32_I2S_USE_SPI3 && !defined(__DOXYGEN__)
extern I2SDriver I2SD3;
#endif
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif

22
os/hal/ports/STM32/STM32F0xx/stm32_registry.h
View File

@ -151,12 +151,15 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX FALSE
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
#define STM32_SPI1_RX_DMA_CHN 0x00000000 #define STM32_SPI1_RX_DMA_CHN 0x00000000
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_SPI1_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S FALSE
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_SPI2_RX_DMA_CHN 0x00000000 #define STM32_SPI2_RX_DMA_CHN 0x00000000
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
@ -382,12 +385,16 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX FALSE
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
#define STM32_SPI1_RX_DMA_CHN 0x00000000 #define STM32_SPI1_RX_DMA_CHN 0x00000000
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_SPI1_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX FALSE
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ #define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
STM32_DMA_STREAM_ID_MSK(1, 6)) STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_SPI2_RX_DMA_CHN 0x00000000 #define STM32_SPI2_RX_DMA_CHN 0x00000000
@ -612,12 +619,15 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX FALSE
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
#define STM32_SPI1_RX_DMA_CHN 0x00000000 #define STM32_SPI1_RX_DMA_CHN 0x00000000
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_SPI1_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S FALSE
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_SPI2_RX_DMA_CHN 0x00000000 #define STM32_SPI2_RX_DMA_CHN 0x00000000
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
@ -818,6 +828,8 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX FALSE
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
#define STM32_SPI1_RX_DMA_CHN 0x00000000 #define STM32_SPI1_RX_DMA_CHN 0x00000000
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
@ -1012,6 +1024,8 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX FALSE
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
#define STM32_SPI1_RX_DMA_CHN 0x00000000 #define STM32_SPI1_RX_DMA_CHN 0x00000000
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
@ -1238,12 +1252,14 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
#define STM32_SPI1_RX_DMA_CHN 0x00000030 #define STM32_SPI1_RX_DMA_CHN 0x00000030
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI1_TX_DMA_CHN 0x00000300 #define STM32_SPI1_TX_DMA_CHN 0x00000300
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S FALSE
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_SPI2_RX_DMA_CHN 0x00003000 #define STM32_SPI2_RX_DMA_CHN 0x00003000
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) #define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
@ -1500,12 +1516,14 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
#define STM32_SPI1_RX_DMA_CHN 0x00000000 #define STM32_SPI1_RX_DMA_CHN 0x00000000
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_SPI1_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S FALSE
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ #define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
STM32_DMA_STREAM_ID_MSK(1, 6)) STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_SPI2_RX_DMA_CHN 0x00000000 #define STM32_SPI2_RX_DMA_CHN 0x00000000
@ -1759,6 +1777,8 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX FALSE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
STM32_DMA_STREAM_ID_MSK(2, 3)) STM32_DMA_STREAM_ID_MSK(2, 3))
#define STM32_SPI1_RX_DMA_CHN 0x00000330 #define STM32_SPI1_RX_DMA_CHN 0x00000330
@ -1767,6 +1787,8 @@
#define STM32_SPI1_TX_DMA_CHN 0x00003300 #define STM32_SPI1_TX_DMA_CHN 0x00003300
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX FALSE
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ #define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
STM32_DMA_STREAM_ID_MSK(1, 6)) STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_SPI2_RX_DMA_CHN 0x00303000 #define STM32_SPI2_RX_DMA_CHN 0x00303000

20
os/hal/ports/STM32/STM32F1xx/stm32_registry.h
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@ -148,10 +148,12 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
@ -339,6 +341,7 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
@ -509,10 +512,12 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
@ -708,14 +713,19 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
@ -940,14 +950,19 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
@ -1174,14 +1189,19 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)

12
os/hal/ports/STM32/STM32F37x/stm32_registry.h
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@ -146,14 +146,20 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
@ -383,14 +389,20 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)

30
os/hal/ports/STM32/STM32F3xx/stm32_registry.h
View File

@ -151,14 +151,19 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
@ -365,6 +370,7 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
@ -565,10 +571,14 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
@ -759,10 +769,14 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
@ -964,14 +978,19 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
@ -1173,10 +1192,14 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
@ -1365,6 +1388,7 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
@ -1572,14 +1596,19 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
@ -1780,6 +1809,7 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)

26
os/hal/ports/STM32/STM32F4xx/stm32_registry.h
View File

@ -214,6 +214,7 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 2)) STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@ -222,12 +223,16 @@
#define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_SPI1_TX_DMA_CHN 0x00303000
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI2_RX_DMA_CHN 0x00000000 #define STM32_SPI2_RX_DMA_CHN 0x00000000
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_SPI2_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
STM32_DMA_STREAM_ID_MSK(1, 2)) STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_SPI3_RX_DMA_CHN 0x00000000 #define STM32_SPI3_RX_DMA_CHN 0x00000000
@ -236,6 +241,7 @@
#define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_SPI3_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI4 TRUE #define STM32_HAS_SPI4 TRUE
#define STM32_SPI4_SUPPORTS_I2S FALSE
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 3)) STM32_DMA_STREAM_ID_MSK(2, 3))
#define STM32_SPI4_RX_DMA_CHN 0x00005004 #define STM32_SPI4_RX_DMA_CHN 0x00005004
@ -244,6 +250,7 @@
#define STM32_SPI4_TX_DMA_CHN 0x00050040 #define STM32_SPI4_TX_DMA_CHN 0x00050040
#define STM32_HAS_SPI5 TRUE #define STM32_HAS_SPI5 TRUE
#define STM32_SPI5_SUPPORTS_I2S FALSE
#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
STM32_DMA_STREAM_ID_MSK(2, 5)) STM32_DMA_STREAM_ID_MSK(2, 5))
#define STM32_SPI5_RX_DMA_CHN 0x00702000 #define STM32_SPI5_RX_DMA_CHN 0x00702000
@ -252,6 +259,7 @@
#define STM32_SPI5_TX_DMA_CHN 0x07020000 #define STM32_SPI5_TX_DMA_CHN 0x07020000
#define STM32_HAS_SPI6 TRUE #define STM32_HAS_SPI6 TRUE
#define STM32_SPI6_SUPPORTS_I2S FALSE
#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6)) #define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6))
#define STM32_SPI6_RX_DMA_CHN 0x01000000 #define STM32_SPI6_RX_DMA_CHN 0x01000000
#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
@ -572,6 +580,7 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 2)) STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@ -580,12 +589,16 @@
#define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_SPI1_TX_DMA_CHN 0x00303000
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI2_RX_DMA_CHN 0x00000000 #define STM32_SPI2_RX_DMA_CHN 0x00000000
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_SPI2_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
STM32_DMA_STREAM_ID_MSK(1, 2)) STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_SPI3_RX_DMA_CHN 0x00000000 #define STM32_SPI3_RX_DMA_CHN 0x00000000
@ -882,6 +895,7 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 2)) STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@ -890,12 +904,16 @@
#define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_SPI1_TX_DMA_CHN 0x00303000
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI2_RX_DMA_CHN 0x00000000 #define STM32_SPI2_RX_DMA_CHN 0x00000000
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_SPI2_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
STM32_DMA_STREAM_ID_MSK(1, 2)) STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_SPI3_RX_DMA_CHN 0x00000000 #define STM32_SPI3_RX_DMA_CHN 0x00000000
@ -904,6 +922,7 @@
#define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_SPI3_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI4 TRUE #define STM32_HAS_SPI4 TRUE
#define STM32_SPI4_SUPPORTS_I2S FALSE
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 3)) STM32_DMA_STREAM_ID_MSK(2, 3))
#define STM32_SPI4_RX_DMA_CHN 0x00005004 #define STM32_SPI4_RX_DMA_CHN 0x00005004
@ -1149,6 +1168,7 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 2)) STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@ -1157,12 +1177,16 @@
#define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_SPI1_TX_DMA_CHN 0x00303000
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI2_RX_DMA_CHN 0x00000000 #define STM32_SPI2_RX_DMA_CHN 0x00000000
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_SPI2_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
STM32_DMA_STREAM_ID_MSK(1, 2)) STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_SPI3_RX_DMA_CHN 0x00000000 #define STM32_SPI3_RX_DMA_CHN 0x00000000
@ -1171,6 +1195,7 @@
#define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_SPI3_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI4 TRUE #define STM32_HAS_SPI4 TRUE
#define STM32_SPI4_SUPPORTS_I2S FALSE
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 3)) STM32_DMA_STREAM_ID_MSK(2, 3))
#define STM32_SPI4_RX_DMA_CHN 0x00005004 #define STM32_SPI4_RX_DMA_CHN 0x00005004
@ -1179,6 +1204,7 @@
#define STM32_SPI4_TX_DMA_CHN 0x00050040 #define STM32_SPI4_TX_DMA_CHN 0x00050040
#define STM32_HAS_SPI5 TRUE #define STM32_HAS_SPI5 TRUE
#define STM32_SPI5_SUPPORTS_I2S FALSE
#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
STM32_DMA_STREAM_ID_MSK(2, 5)) STM32_DMA_STREAM_ID_MSK(2, 5))
#define STM32_SPI5_RX_DMA_CHN 0x00702000 #define STM32_SPI5_RX_DMA_CHN 0x00702000

6
os/hal/ports/STM32/STM32F7xx/stm32_registry.h
View File

@ -232,6 +232,8 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX TRUE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 2)) STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@ -240,12 +242,16 @@
#define STM32_SPI1_TX_DMA_CHN 0x00303000 #define STM32_SPI1_TX_DMA_CHN 0x00303000
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI2_RX_DMA_CHN 0x00000000 #define STM32_SPI2_RX_DMA_CHN 0x00000000
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_SPI2_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
STM32_DMA_STREAM_ID_MSK(1, 2)) STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_SPI3_RX_DMA_CHN 0x00000000 #define STM32_SPI3_RX_DMA_CHN 0x00000000

3
os/hal/ports/STM32/STM32L0xx/stm32_registry.h
View File

@ -163,12 +163,15 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000010 #define STM32_SPI1_RX_DMA_CHN 0x00000010
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) #define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
#define STM32_SPI1_TX_DMA_CHN 0x00000100 #define STM32_SPI1_TX_DMA_CHN 0x00000100
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX FALSE
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ #define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
STM32_DMA_STREAM_ID_MSK(1, 6)) STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_SPI2_RX_DMA_CHN 0x00202000 #define STM32_SPI2_RX_DMA_CHN 0x00202000

5
os/hal/ports/STM32/STM32L1xx/stm32_registry.h
View File

@ -200,10 +200,13 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
@ -212,6 +215,8 @@
#define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI3 FALSE
#else #else
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#endif #endif