git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5193 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
ee50edb9bd
commit
a77a8ed5ee
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file templates/hal_lld.c
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* @brief HAL Driver subsystem low level driver source template.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define SAM_PM_UNLOCK(addr) \
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PM->PM_UNLOCK = BPM_UNLOCK_KEY(0xAAu) | \
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BPM_UNLOCK_ADDR((uint32_t)(addr) - (uint32_t)PM)
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#define SAM_SCIF_UNLOCK(addr) \
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SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xAAu) | \
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SCIF_UNLOCK_ADDR((uint32_t)(addr) - (uint32_t)SCIF)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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void sam_set_optimal_flash_mode(void) {
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if (SAM_PMCON_PS == SAM_PMCON_PS0) {
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/* Scalability Level 0.*/
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if (SAM_CPU_CLK > SAM_FLASH0WS_MAX) {
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/* One wait state required.*/
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if (SAM_CPU_CLK <= SAM_FLASH1WS_MAX) {
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/* Fast read mode disabled.*/
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}
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else {
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/* Fast read mode enabled.*/
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}
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}
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else {
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/* No wait state required.*/
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}
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}
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else {
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/* Scalability Level 1.*/
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if (SAM_CPU_CLK > SAM_FLASH0WS_MAX) {
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}
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else {
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}
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Enables a module on one of the PBx buses.
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* @note PB bridges are assumed to be already enabled.
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*
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* @param[in] bus_id id of the bus
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* @param[in] module module address
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*/
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void sam_enable_module(uint32_t bus_id, uint32_t module) {
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uint32_t mask;
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mask = *(&PM->PM_CPUMASK + bus_id);
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mask |= 1U << module;
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SAM_PM_UNLOCK((uint32_t)&PM->PM_CPUMASK + (4 * bus_id));
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*(&PM->PM_CPUMASK + bus_id) |= mask;
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}
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/**
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* @brief Disables a module on one of the PBx buses.
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* @note PB bridges are assumed to be already enabled.
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*
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* @param[in] bus_id id of the bus
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* @param[in] module module index
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*/
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void sam_disable_module(uint32_t bus_id, uint32_t module) {
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uint32_t mask;
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mask = *(&PM->PM_CPUMASK + bus_id);
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mask &= ~(1U << module);
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SAM_PM_UNLOCK((uint32_t)&PM->PM_CPUMASK + (4 * bus_id));
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*(&PM->PM_CPUMASK + bus_id) = mask;
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}
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/**
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* @brief Clock initialization.
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*/
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void sam_clock_init(void) {
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#if SAM_NO_INIT
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/* Enables bridges.*/
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sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBA_BRIDGE);
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sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBB_BRIDGE);
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sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBC_BRIDGE);
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sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBD_BRIDGE);
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#if SAM_USE_PICOCACHE
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/* Enable the PicoCache.*/
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sam_enable_module(SAM_CLK_GRP_PBB, SAM_PBB_HRAMC1_DATA);
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sam_enable_module(SAM_CLK_GRP_PBB, SAM_PBB_HRAMC1_REGS);
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HCACHE->HCACHE_CTRL = HCACHE_CTRL_CEN_YES;
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while ((HCACHE->HCACHE_SR & HCACHE_SR_CSTS_EN) == 0)
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;
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#endif
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/* Setting up prescalers.*/
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SAM_PM_UNLOCK(&PM->PM_CPUSEL);
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PM->PM_CPUSEL = SAM_CPUSEL;
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SAM_PM_UNLOCK(&PM->PM_PBASEL);
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PM->PM_PBASEL = SAM_PBASEL;
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SAM_PM_UNLOCK(&PM->PM_PBBSEL);
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PM->PM_PBBSEL = SAM_PBBSEL;
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SAM_PM_UNLOCK(&PM->PM_PBCSEL);
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PM->PM_PBCSEL = SAM_PBCSEL;
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SAM_PM_UNLOCK(&PM->PM_PBDSEL);
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PM->PM_PBDSEL = SAM_PBDSEL;
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/* Switching to the selected clock source, enabling it if necessary.*/
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_RCSYS
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/* Nothing to do, already running from SYSIRC.*/
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#endif
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_OSC0
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SAM_SCIF_UNLOCK(&SCIF->SCIF_OSCCTRL0);
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SCIF->SCIF_OSCCTRL0 = SAM_OSCCTRL_GAIN | SAM_OSCCTRL_MODE |
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SAM_OSCCTRL_STARTUP | SAM_OSCCTRL_OSCEN;
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while (!(SCIF->SCIF_PCLKSR & SCIF_PCLKSR_OSC0RDY))
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;
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sam_set_optimal_flash_mode();
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#endif /* SAM_MCCTRL_MCSEL == SAM_MCSEL_RCSYS */
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_PLL
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#endif /* SAM_MCCTRL_MCSEL == SAM_MCSEL_PLL */
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_DFLL
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#endif /* SAM_MCCTRL_MCSEL == SAM_MCSEL_DFLL */
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_RC80M
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#endif /* SAM_MCCTRL_MCSEL == SAM_MCSEL_RC80M */
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_RCFAST
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#endif /* SAM_MCCTRL_MCSEL == SAM_MCSEL_RCFAST */
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_RC1M
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#endif /* SAM_MCCTRL_MCSEL == SAM_MCSEL_RC1M */
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#endif /* SAM_NO_INIT */
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}
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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}
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/** @} */
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@ -1,611 +0,0 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
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||||
|
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ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file templates/hal_lld.h
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* @brief HAL subsystem low level driver header template.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - SAM_OSC32K_CLK.
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* - SAM_OSC32K_MODE_EXT (optional)
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* - SAM_OSC0_CLK.
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* - SAM_OSCCTRL_MODE
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "sam4l.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS TRUE
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/**
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* @brief Platform name
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*/
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#define PLATFORM_NAME "SAM4L Series"
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/**
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* @name Internal clock sources
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* @{
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*/
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#define SAM_RC32K_CLK 32768
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#define SAM_RCSYS_CLK 115000
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#define SAM_RC1M_CLK 1000000
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#define SAM_RCFAST0_CLK 4000000
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#define SAM_RCFAST1_CLK 8000000
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#define SAM_RCFAST2_CLK 12000000
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#define SAM_RC80M_CLK 80000000
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/** @} */
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/**
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* @name BUS IDs
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* @{
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*/
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#define SAM_CLK_GRP_CPU 0
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#define SAM_CLK_GRP_HSB 1
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#define SAM_CLK_GRP_PBA 2
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#define SAM_CLK_GRP_PBB 3
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#define SAM_CLK_GRP_PBC 4
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#define SAM_CLK_GRP_PBD 5
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/** @} */
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/**
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* @name Clocks derived from the HSB clock
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* @{
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*/
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#define SAM_HSB_PDCA_HSB 0
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#define SAM_HSB_HFLASHC_DATA 1
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#define SAM_HSB_HRAMC1_DATA 2
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#define SAM_HSB_USBC_DATA 3
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#define SAM_HSB_CRCCU_DATA 4
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#define SAM_HSB_PBA_BRIDGE 5
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#define SAM_HSB_PBB_BRIDGE 6
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#define SAM_HSB_PBC_BRIDGE 7
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#define SAM_HSB_PBD_BRIDGE 8
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#define SAM_HSB_AESA_HSB 9
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/** @} */
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/**
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* @name Clocks derived from the PBA clock
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* @{
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*/
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#define SAM_PBA_IISC 0
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#define SAM_PBA_SPI 1
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#define SAM_PBA_TC0 2
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#define SAM_PBA_TC1 3
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#define SAM_PBA_TWIM0 4
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#define SAM_PBA_TWIS0 5
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#define SAM_PBA_TWIM1 6
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#define SAM_PBA_TWIS1 7
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#define SAM_PBA_USART0 8
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#define SAM_PBA_USART1 9
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#define SAM_PBA_USART2 10
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#define SAM_PBA_USART3 11
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#define SAM_PBA_ADCIFE 12
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#define SAM_PBA_DACC 13
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#define SAM_PBA_ACIFC 14
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#define SAM_PBA_GLOC 15
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#define SAM_PBA_ABDACB 16
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#define SAM_PBA_TRNG 17
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#define SAM_PBA_PARC 18
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#define SAM_PBA_CATB 19
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#define SAM_PBA_TWIM2 21
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#define SAM_PBA_TWIM3 22
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#define SAM_PBA_LCDCA 23
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/** @} */
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/**
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* @name Clocks derived from the PBB clock
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* @{
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*/
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#define SAM_PBB_HFLASHC_REGS 0
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#define SAM_PBB_HRAMC1_REGS 1
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#define SAM_PBB_HMATRIX 2
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#define SAM_PBB_PDCA_PB 3
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#define SAM_PBB_CRCCU_REGS 4
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#define SAM_PBB_USBC_REGS 5
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#define SAM_PBB_PEVC 6
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/** @} */
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/**
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* @name Clocks derived from the PBC clock
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* @{
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*/
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#define SAM_PBC_PM 0
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#define SAM_PBC_CHIPID 1
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#define SAM_PBC_SCIF 2
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#define SAM_PBC_FREQM 3
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#define SAM_PBC_GPIO 4
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/* @} */
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/**
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* @name Clocks derived from the PBD clock
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* @{
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*/
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#define SAM_PBD_BPM 0
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#define SAM_PBD_BSCIF 1
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#define SAM_PBD_AST 2
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#define SAM_PBD_WDT 3
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#define SAM_PBD_EIC 4
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#define SAM_PBD_PICOUART 5
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/** @} */
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/**
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* @name MCCTRL register bits definitions
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* @{
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*/
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#define SAM_MCSEL_MASK (7 << 0) /**< MCSEL bits mask. */
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#define SAM_MCSEL_RCSYS (0 << 0) /**< System RC oscillator. */
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#define SAM_MCSEL_OSC0 (1 << 0) /**< Oscillator 0. */
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#define SAM_MCSEL_PLL (2 << 0) /**< PLL. */
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#define SAM_MCSEL_DFLL (3 << 0) /**< DFLL. */
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#define SAM_MCSEL_RC80M (4 << 0) /**< 80 MHz RC oscillator. */
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#define SAM_MCSEL_RCFAST (5 << 0) /**< 4/8/12 MHz RC oscillator. */
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#define SAM_MCSEL_RC1M (6 << 0) /**< 1 MHz RC oscillator. */
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/** @} */
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/**
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* @name CPUSEL register bits definitions
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* @{
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*/
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#define SAM_CPUSEL_MASK (7 << 0) /**< CPUSEL bits mask. */
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#define SAM_CPUSEL_DIV1 0
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#define SAM_CPUSEL_DIV2 (SAM_CPUDIV | 0)
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#define SAM_CPUSEL_DIV4 (SAM_CPUDIV | 1)
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#define SAM_CPUSEL_DIV8 (SAM_CPUDIV | 2)
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#define SAM_CPUSEL_DIV16 (SAM_CPUDIV | 3)
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#define SAM_CPUSEL_DIV32 (SAM_CPUDIV | 4)
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#define SAM_CPUSEL_DIV64 (SAM_CPUDIV | 5)
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#define SAM_CPUSEL_DIV128 (SAM_CPUDIV | 6)
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#define SAM_CPUSEL_DIV256 (SAM_CPUDIV | 7)
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#define SAM_CPUDIV (1 << 7) /**< CPUDIV bit. */
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/**
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* @name PBx registers bits definitions
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* @{
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*/
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#define SAM_PBSEL_MASK (7 << 0) /**< PBSEL bits mask. */
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#define SAM_PBSEL_DIV1 0
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#define SAM_PBSEL_DIV2 (SAM_CPUDIV | 0)
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#define SAM_PBSEL_DIV4 (SAM_CPUDIV | 1)
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#define SAM_PBSEL_DIV8 (SAM_CPUDIV | 2)
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#define SAM_PBSEL_DIV16 (SAM_CPUDIV | 3)
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#define SAM_PBSEL_DIV32 (SAM_CPUDIV | 4)
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#define SAM_PBSEL_DIV64 (SAM_CPUDIV | 5)
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#define SAM_PBSEL_DIV128 (SAM_CPUDIV | 6)
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#define SAM_PBSEL_DIV256 (SAM_CPUDIV | 7)
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#define SAM_PBDIV (1 << 7) /**< PBDIV bit. */
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/** @} */
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/**
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* @name RCFASTCFG registers bits definitions
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* @{
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*/
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#define SAM_RCFASTCFG_FRANGE_4M 0x00000000
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#define SAM_RCFASTCFG_FRANGE_8M 0x00000100
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#define SAM_RCFASTCFG_FRANGE_12M 0x00000200
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/** @} */
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/**
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* @name PMCON registers bits definitions
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* @{
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*/
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#define SAM_PMCON_PS0 (0 << 0)
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#define SAM_PMCON_PS1 (1 << 0)
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/** @} */
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/**
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* @name OSCCTRL0 registers bits definitions
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* @{
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*/
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#define SAM_OSCCTRL_MODE_EXT (0 << 0)
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#define SAM_OSCCTRL_MODE_XTAL (1 << 0)
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#define SAM_OSCCTRL_GAIN_0 (0 << 1)
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#define SAM_OSCCTRL_GAIN_1 (1 << 1)
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#define SAM_OSCCTRL_GAIN_2 (2 << 1)
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#define SAM_OSCCTRL_GAIN_3 (3 << 1)
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#define SAM_OSCCTRL_OSCEN (1 << 16)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief Disables the clock initialization in the HAL.
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*/
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#if !defined(SAM_NO_INIT) || defined(__DOXYGEN__)
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#define SAM_NO_INIT FALSE
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#endif
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/**
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* @brief Power Scalability mode.
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*/
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#if !defined(SAM_PMCON_PS) || defined(__DOXYGEN__)
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#define SAM_PMCON_PS SAM_PMCON_PS0
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#endif
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/**
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* @brief MCCTRL register settings.
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*/
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#if !defined(SAM_MCCTRL_MCSEL) || defined(__DOXYGEN__)
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#define SAM_MCCTRL_MCSEL SAM_MCSEL_PLL
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#endif
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/**
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* @brief CPUSEL register settings.
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*/
|
||||
#if !defined(SAM_CPUSEL) || defined(__DOXYGEN__)
|
||||
#define SAM_CPUSEL SAM_CPUSEL_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PBASEL register settings.
|
||||
*/
|
||||
#if !defined(SAM_PBASEL) || defined(__DOXYGEN__)
|
||||
#define SAM_PBASEL SAM_PBSEL_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PBBSEL register settings.
|
||||
*/
|
||||
#if !defined(SAM_PBBSEL) || defined(__DOXYGEN__)
|
||||
#define SAM_PBBSEL SAM_PBSEL_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PBCSEL register settings.
|
||||
*/
|
||||
#if !defined(SAM_PBCSEL) || defined(__DOXYGEN__)
|
||||
#define SAM_PBCSEL SAM_PBSEL_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PBDSEL register settings.
|
||||
*/
|
||||
#if !defined(SAM_PBDSEL) || defined(__DOXYGEN__)
|
||||
#define SAM_PBDSEL SAM_PBSEL_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PBDSEL register settings.
|
||||
*/
|
||||
#if !defined(SAM_PBDSEL) || defined(__DOXYGEN__)
|
||||
#define SAM_RCFAST_FRANGE SAM_RCFASTCFG_FRANGE_4M
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Clock limits depending on power scaling mode
|
||||
* @{
|
||||
*/
|
||||
#if (SAM_PMCON_PS == SAM_PMCON_PS0)|| defined(__DOXYGEN__)
|
||||
#define SAM_CPUCLK_MAX 50000000
|
||||
#define SAM_PBACLK_MAX 50000000
|
||||
#define SAM_PBBCLK_MAX 50000000
|
||||
#define SAM_PBCCLK_MAX 50000000
|
||||
#define SAM_PBDCLK_MAX 50000000
|
||||
#define SAM_FLASH0WS_MAX 18000000
|
||||
#define SAM_FLASH1WS_MAX 36000000
|
||||
#define SAM_FLASH1WS_FWU_MAX 12000000
|
||||
|
||||
#elif SAM_PMCON_PS == SAM_PMCON_PS1
|
||||
#define SAM_CPUCLK_MAX 12000000
|
||||
#define SAM_PBACLK_MAX 12000000
|
||||
#define SAM_PBBCLK_MAX 12000000
|
||||
#define SAM_PBCCLK_MAX 12000000
|
||||
#define SAM_PBDCLK_MAX 12000000
|
||||
#define SAM_FLASH0WS_MAX 8000000
|
||||
#define SAM_FLASH1WS_MAX 12000000
|
||||
#define SAM_FLASH1WS_FWU_MAX 0
|
||||
|
||||
#else
|
||||
#error "invalid SAM_PMCON_PS value specified"
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/* OSC0 mode check.*/
|
||||
#if (SAM_OSCCTRL_MODE != SAM_OSCCTRL_MODE_EXT) && \
|
||||
(SAM_OSCCTRL_MODE != SAM_OSCCTRL_MODE_XTAL)
|
||||
#error "invalid SAM_OSCCTRL_MODE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief OSC0 gain setting.
|
||||
*/
|
||||
#if SAM_OSCCTRL_MODE == SAM_OSCCTRL_MODE_EXT
|
||||
#define SAM_OSCCTRL_GAIN 0
|
||||
#else
|
||||
#if SAM_OSC0_CLK < 12000000
|
||||
#define SAM_OSCCTRL_GAIN SAM_OSCCTRL_GAIN_0
|
||||
#elif SAM_OSC0_CLK < 16000000
|
||||
#define SAM_OSCCTRL_GAIN SAM_OSCCTRL_GAIN_1
|
||||
#else
|
||||
#define SAM_OSCCTRL_GAIN SAM_OSCCTRL_GAIN_2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief OSC0 startup setting.
|
||||
*/
|
||||
#define SAM_OSCCTRL_STARTUP SCIF_OSCCTRL0_STARTUP(2)
|
||||
|
||||
/**
|
||||
* @brief Selected RCFAST clock frequency.
|
||||
*/
|
||||
#if (SAM_RCFAST_FRANGE == SAM_RCFASTCFG_FRANGE_4M)|| defined(__DOXYGEN__)
|
||||
#define SAM_RCFAST_CLK SAM_RCFAST0_CLK
|
||||
#elif SAM_RCFAST_FRANGE == SAM_RCFASTCFG_FRANGE_8M
|
||||
#define SAM_RCFAST_CLK SAM_RCFAST1_CLK
|
||||
#elif SAM_RCFAST_FRANGE == SAM_RCFASTCFG_FRANGE_12M
|
||||
#define SAM_RCFAST_CLK SAM_RCFAST2_CLK
|
||||
#else
|
||||
#error "invalid SAM_RCFAST_FRANGE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Selected main clock frequency.
|
||||
*/
|
||||
#if (SAM_MCCTRL_MCSEL == SAM_MCSEL_RCSYS) || defined(__DOXYGEN__)
|
||||
#define SAM_MAIN_CLK SAM_RCSYS_CLK
|
||||
#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_OSC0
|
||||
#define SAM_MAIN_CLK SAM_OSC0_CLK
|
||||
#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_PLL
|
||||
#define SAM_MAIN_CLK 0
|
||||
#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_DFLL
|
||||
#define SAM_MAIN_CLK 0
|
||||
#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_RC80M
|
||||
#define SAM_MAIN_CLK SAM_RC80M_CLK
|
||||
#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_RCFAST
|
||||
#define SAM_MAIN_CLK SAM_RCFAST_CLK
|
||||
#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_RC1M
|
||||
#define SAM_MAIN_CLK SAM_RC1M_CLK
|
||||
#else
|
||||
#error "invalid SAM_MCCTRL_MCSEL value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief CPU clock.
|
||||
*/
|
||||
#if (SAM_CPUSEL == SAM_CPUSEL_DIV1) || defined(__DOXYGEN__)
|
||||
#define SAM_CPU_CLK (SAM_MAIN_CLK / 1)
|
||||
#elif SAM_CPUSEL == SAM_CPUSEL_DIV2
|
||||
#define SAM_CPU_CLK (SAM_MAIN_CLK / 2)
|
||||
#elif SAM_CPUSEL == SAM_CPUSEL_DIV4
|
||||
#define SAM_CPU_CLK (SAM_MAIN_CLK / 4)
|
||||
#elif SAM_CPUSEL == SAM_CPUSEL_DIV8
|
||||
#define SAM_CPU_CLK (SAM_MAIN_CLK / 8)
|
||||
#elif SAM_CPUSEL == SAM_CPUSEL_DIV16
|
||||
#define SAM_CPU_CLK (SAM_MAIN_CLK / 16)
|
||||
#elif SAM_CPUSEL == SAM_CPUSEL_DIV32
|
||||
#define SAM_CPU_CLK (SAM_MAIN_CLK / 32)
|
||||
#elif SAM_CPUSEL == SAM_CPUSEL_DIV64
|
||||
#define SAM_CPU_CLK (SAM_MAIN_CLK / 64)
|
||||
#elif SAM_CPUSEL == SAM_CPUSEL_DIV128
|
||||
#define SAM_CPU_CLK (SAM_MAIN_CLK / 128)
|
||||
#elif SAM_CPUSEL == SAM_CPUSEL_DIV256
|
||||
#define SAM_CPU_CLK (SAM_MAIN_CLK / 256)
|
||||
#else
|
||||
#error "invalid SAM_CPUSEL value specified"
|
||||
#endif
|
||||
|
||||
/* CPU clock check.*/
|
||||
#if SAM_CPU_CLK > SAM_CPUCLK_MAX
|
||||
#error "SAM_CPU_CLK above maximum rated frequency (SAM_CPUCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PBA clock.
|
||||
*/
|
||||
#if (SAM_PBASEL == SAM_PBASEL_DIV1) || defined(__DOXYGEN__)
|
||||
#define SAM_PBA_CLK (SAM_MAIN_CLK / 1)
|
||||
#elif SAM_PBASEL == SAM_PBASEL_DIV2
|
||||
#define SAM_PBA_CLK (SAM_MAIN_CLK / 2)
|
||||
#elif SAM_PBASEL == SAM_PBASEL_DIV4
|
||||
#define SAM_PBA_CLK (SAM_MAIN_CLK / 4)
|
||||
#elif SAM_PBASEL == SAM_PBASEL_DIV8
|
||||
#define SAM_PBA_CLK (SAM_MAIN_CLK / 8)
|
||||
#elif SAM_PBASEL == SAM_PBASEL_DIV16
|
||||
#define SAM_PBA_CLK (SAM_MAIN_CLK / 16)
|
||||
#elif SAM_PBASEL == SAM_PBASEL_DIV32
|
||||
#define SAM_PBA_CLK (SAM_MAIN_CLK / 32)
|
||||
#elif SAM_PBASEL == SAM_PBASEL_DIV64
|
||||
#define SAM_PBA_CLK (SAM_MAIN_CLK / 64)
|
||||
#elif SAM_PBASEL == SAM_PBASEL_DIV128
|
||||
#define SAM_PBA_CLK (SAM_MAIN_CLK / 128)
|
||||
#elif SAM_PBASEL == SAM_PBASEL_DIV256
|
||||
#define SAM_PBA_CLK (SAM_MAIN_CLK / 256)
|
||||
#else
|
||||
#error "invalid SAM_PBASEL value specified"
|
||||
#endif
|
||||
|
||||
/* PBA clock check.*/
|
||||
#if SAM_PBA_CLK > SAM_PBACLK_MAX
|
||||
#error "SAM_PBA_CLK above maximum rated frequency (SAM_PBACLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PBB clock.
|
||||
*/
|
||||
#if (SAM_PBBSEL == SAM_PBBSEL_DIV1) || defined(__DOXYGEN__)
|
||||
#define SAM_PBB_CLK (SAM_MAIN_CLK / 1)
|
||||
#elif SAM_PBBSEL == SAM_PBBSEL_DIV2
|
||||
#define SAM_PBB_CLK (SAM_MAIN_CLK / 2)
|
||||
#elif SAM_PBBSEL == SAM_PBBSEL_DIV4
|
||||
#define SAM_PBB_CLK (SAM_MAIN_CLK / 4)
|
||||
#elif SAM_PBBSEL == SAM_PBBSEL_DIV8
|
||||
#define SAM_PBB_CLK (SAM_MAIN_CLK / 8)
|
||||
#elif SAM_PBBSEL == SAM_PBBSEL_DIV16
|
||||
#define SAM_PBB_CLK (SAM_MAIN_CLK / 16)
|
||||
#elif SAM_PBBSEL == SAM_PBBSEL_DIV32
|
||||
#define SAM_PBB_CLK (SAM_MAIN_CLK / 32)
|
||||
#elif SAM_PBBSEL == SAM_PBBSEL_DIV64
|
||||
#define SAM_PBB_CLK (SAM_MAIN_CLK / 64)
|
||||
#elif SAM_PBBSEL == SAM_PBBSEL_DIV128
|
||||
#define SAM_PBB_CLK (SAM_MAIN_CLK / 128)
|
||||
#elif SAM_PBBSEL == SAM_PBBSEL_DIV256
|
||||
#define SAM_PBB_CLK (SAM_MAIN_CLK / 256)
|
||||
#else
|
||||
#error "invalid SAM_PBBSEL value specified"
|
||||
#endif
|
||||
|
||||
/* PBB clock check.*/
|
||||
#if SAM_PBB_CLK > SAM_PBBCLK_MAX
|
||||
#error "SAM_PBB_CLK above maximum rated frequency (SAM_PBBCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PBC clock.
|
||||
*/
|
||||
#if (SAM_PBCSEL == SAM_PBCSEL_DIV1) || defined(__DOXYGEN__)
|
||||
#define SAM_PBC_CLK (SAM_MAIN_CLK / 1)
|
||||
#elif SAM_PBCSEL == SAM_PBCSEL_DIV2
|
||||
#define SAM_PBC_CLK (SAM_MAIN_CLK / 2)
|
||||
#elif SAM_PBCSEL == SAM_PBCSEL_DIV4
|
||||
#define SAM_PBC_CLK (SAM_MAIN_CLK / 4)
|
||||
#elif SAM_PBCSEL == SAM_PBCSEL_DIV8
|
||||
#define SAM_PBC_CLK (SAM_MAIN_CLK / 8)
|
||||
#elif SAM_PBCSEL == SAM_PBCSEL_DIV16
|
||||
#define SAM_PBC_CLK (SAM_MAIN_CLK / 16)
|
||||
#elif SAM_PBCSEL == SAM_PBCSEL_DIV32
|
||||
#define SAM_PBC_CLK (SAM_MAIN_CLK / 32)
|
||||
#elif SAM_PBCSEL == SAM_PBCSEL_DIV64
|
||||
#define SAM_PBC_CLK (SAM_MAIN_CLK / 64)
|
||||
#elif SAM_PBCSEL == SAM_PBCSEL_DIV128
|
||||
#define SAM_PBC_CLK (SAM_MAIN_CLK / 128)
|
||||
#elif SAM_PBCSEL == SAM_PBCSEL_DIV256
|
||||
#define SAM_PBC_CLK (SAM_MAIN_CLK / 256)
|
||||
#else
|
||||
#error "invalid SAM_PBCSEL value specified"
|
||||
#endif
|
||||
|
||||
/* PBC clock check.*/
|
||||
#if SAM_PBC_CLK > SAM_PBCCLK_MAX
|
||||
#error "SAM_PBC_CLK above maximum rated frequency (SAM_PBCCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PBD clock.
|
||||
*/
|
||||
#if (SAM_PBDSEL == SAM_PBDSEL_DIV1) || defined(__DOXYGEN__)
|
||||
#define SAM_PBD_CLK (SAM_MAIN_CLK / 1)
|
||||
#elif SAM_PBDSEL == SAM_PBDSEL_DIV2
|
||||
#define SAM_PBD_CLK (SAM_MAIN_CLK / 2)
|
||||
#elif SAM_PBDSEL == SAM_PBDSEL_DIV4
|
||||
#define SAM_PBD_CLK (SAM_MAIN_CLK / 4)
|
||||
#elif SAM_PBDSEL == SAM_PBDSEL_DIV8
|
||||
#define SAM_PBD_CLK (SAM_MAIN_CLK / 8)
|
||||
#elif SAM_PBDSEL == SAM_PBDSEL_DIV16
|
||||
#define SAM_PBD_CLK (SAM_MAIN_CLK / 16)
|
||||
#elif SAM_PBDSEL == SAM_PBDSEL_DIV32
|
||||
#define SAM_PBD_CLK (SAM_MAIN_CLK / 32)
|
||||
#elif SAM_PBDSEL == SAM_PBDSEL_DIV64
|
||||
#define SAM_PBD_CLK (SAM_MAIN_CLK / 64)
|
||||
#elif SAM_PBDSEL == SAM_PBDSEL_DIV128
|
||||
#define SAM_PBD_CLK (SAM_MAIN_CLK / 128)
|
||||
#elif SAM_PBDSEL == SAM_PBDSEL_DIV256
|
||||
#define SAM_PBD_CLK (SAM_MAIN_CLK / 256)
|
||||
#else
|
||||
#error "invalid SAM_PBDSEL value specified"
|
||||
#endif
|
||||
|
||||
/* PBD clock check.*/
|
||||
#if SAM_PBD_CLK > SAM_PBDCLK_MAX
|
||||
#error "SAM_PBD_CLK above maximum rated frequency (SAM_PBDCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Type representing a system clock frequency.
|
||||
*/
|
||||
typedef uint32_t halclock_t;
|
||||
|
||||
/**
|
||||
* @brief Type of the realtime free counter value.
|
||||
*/
|
||||
typedef uint32_t halrtcnt_t;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Returns the current value of the system free running counter.
|
||||
* @note This service is implemented by returning the content of the
|
||||
* DWT_CYCCNT register.
|
||||
*
|
||||
* @return The value of the system free running counter of
|
||||
* type halrtcnt_t.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define hal_lld_get_counter_value() DWT_CYCCNT
|
||||
|
||||
/**
|
||||
* @brief Realtime counter frequency.
|
||||
* @note The DWT_CYCCNT register is incremented directly by the system
|
||||
* clock so this function returns STM32_HCLK.
|
||||
*
|
||||
* @return The realtime counter frequency of type halclock_t.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define hal_lld_get_counter_frequency() STM32_HCLK
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void sam_enable_module(uint32_t bus_id, uint32_t module);
|
||||
void sam_disable_module(uint32_t bus_id, uint32_t module);
|
||||
void sam_clock_init(void);
|
||||
void hal_lld_init(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
# List of all the STM32F3xx platform files.
|
||||
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SAM4L/hal_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/SAM4L/asf/flashcalw.c
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SAM4L \
|
||||
${CHIBIOS}/os/hal/platforms/SAM4L/asf
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,101 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief ASF Patch Header file definitions for SAM4L.
|
||||
*
|
||||
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SAM4L_PATCH_ASF_H_INCLUDED
|
||||
#define SAM4L_PATCH_ASF_H_INCLUDED
|
||||
|
||||
// These defines are used for sam/drivers/flashcalw implementation.
|
||||
#define FLASHCALW_FCMD_CMD_HSEN (0x10u << 0)
|
||||
#define FLASHCALW_FCMD_CMD_HSDIS (0x11u << 0)
|
||||
|
||||
// These defines are used to keep compatibility with existing
|
||||
// sam/drivers/usart implementation from SAM3/4 products with SAM4L product.
|
||||
#define US_MR_USART_MODE_HW_HANDSHAKING US_MR_USART_MODE_HARDWARE
|
||||
#define US_MR_USART_MODE_IS07816_T_0 US_MR_USART_MODE_ISO7816_T0
|
||||
#define US_MR_USART_MODE_IS07816_T_1 US_MR_USART_MODE_ISO7816_T1
|
||||
#define US_MR_NBSTOP_2_BIT US_MR_NBSTOP_2
|
||||
#define US_MR_NBSTOP_1_BIT US_MR_NBSTOP_1
|
||||
#define US_MR_CHRL_8_BIT US_MR_CHRL_8
|
||||
#define US_MR_PAR_NO US_MR_PAR_NONE
|
||||
#define US_MR_PAR_MULTIDROP US_MR_PAR_MULTI
|
||||
#define US_IF US_IFR
|
||||
#define US_WPSR_WPVS US_WPSR_WPV_1
|
||||
|
||||
#if (!defined SCIF_RCOSC_FREQUENCY)
|
||||
# define SCIF_RCOSC_FREQUENCY 115200
|
||||
#endif
|
||||
|
||||
// These defines for homogeneity with other SAM header files.
|
||||
#define CHIP_FREQ_FWS_0 (18000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
|
||||
#define CHIP_FREQ_FWS_1 (36000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
|
||||
// WARNING NOTE: these are preliminary values.
|
||||
#define CHIP_FREQ_FLASH_HSEN_FWS_0 (18000000UL) /**< \brief Maximum operating frequency when FWS is 0 and the FLASH HS mode is enabled */
|
||||
#define CHIP_FREQ_FLASH_HSEN_FWS_1 (36000000UL) /**< \brief Maximum operating frequency when FWS is 1 and the FLASH HS mode is enabled */
|
||||
|
||||
// Size of HRAMC1 with 32-bit access
|
||||
#undef HRAMC1_SIZE
|
||||
#define HRAMC1_SIZE (0x800UL)
|
||||
|
||||
// USBC related offsets
|
||||
#define USBC_UHINT_P0INT_Pos 8
|
||||
#define USBC_UHINTE_P0INTE_Pos 8
|
||||
#define USBC_UPCFG0_PBK_Pos 2
|
||||
#define USBC_UPCFG0_PBK_Msk (0x1u << USBC_UPCFG0_PBK_Pos)
|
||||
|
||||
// These defines are used to keep compatibility with existing
|
||||
// sam/drivers/tc implementation from SAM3/4 products with SAM4L product.
|
||||
#define TC_SMMR TC_SMC
|
||||
#define TC_CMR_LDRA_RISING TC_CMR_LDRA_POS_EDGE_TIOA
|
||||
#define TC_CMR_LDRB_FALLING TC_CMR_LDRB_NEG_EDGE_TIOA
|
||||
#define TC_CMR_ETRGEDG_FALLING TC_CMR_ETRGEDG_NEG_EDGE
|
||||
|
||||
// These defines are used to keep compatibility with existing
|
||||
// sam/drivers/spi implementation from SAM3/4 products with SAM4L product.
|
||||
#define SPI_CSR_BITS_8_BIT SPI_CSR_BITS_8_BPT
|
||||
|
||||
#define SPI_WPSR_WPVS_Pos SPI_WPSR_SPIWPVS_Pos
|
||||
#define SPI_WPSR_WPVS_Msk SPI_WPSR_SPIWPVS_Msk
|
||||
#define SPI_WPSR_WPVSRC_Pos SPI_WPSR_SPIWPVSRC_Pos
|
||||
#define SPI_WPSR_WPVSRC_Msk SPI_WPSR_SPIWPVSRC_Msk
|
||||
|
||||
#endif // SAM4L_PATCH_ASF_H_INCLUDED
|
||||
|
|
@ -109,6 +109,8 @@
|
|||
(backported to 2.4.3).
|
||||
- FIX: Fixed wrong SPI path in platform_f105_f107.mk (bug 3598151).
|
||||
- FIX: Fixed PHY powerdown issues not fixed (bug 3596911).
|
||||
- NEW: Added kernel support for the SAM4L, an Atmel Studio 6 demo for the
|
||||
SAM4L-EK board has been added.
|
||||
- NEW: Added support for SPC56ELxx, SPC560BCxx, SPC560Pxx and SPC560Mxx
|
||||
platforms.
|
||||
- NEW: Added an abstract file system interface written in C++, no
|
||||
|
|
|
|||
Loading…
Reference in New Issue