diff --git a/docs/reports/LPC1114-48-GCC.txt b/docs/reports/LPC1114-48-GCC.txt index 260d994a4..32ea4154e 100644 --- a/docs/reports/LPC1114-48-GCC.txt +++ b/docs/reports/LPC1114-48-GCC.txt @@ -5,7 +5,7 @@ Settings: CLK=48, (2 wait states) *** ChibiOS/RT test suite *** -*** Kernel: 2.1.7unstable +*** Kernel: 2.3.0unstable *** GCC Version: 4.3.3 *** Architecture: ARMv6-M *** Core Variant: Cortex-M0 @@ -98,51 +98,51 @@ Settings: CLK=48, (2 wait states) --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.1 (Benchmark, messages #1) ---- Score : 124135 msgs/S, 248270 ctxswc/S +--- Score : 126834 msgs/S, 253668 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.2 (Benchmark, messages #2) ---- Score : 99992 msgs/S, 199984 ctxswc/S +--- Score : 100879 msgs/S, 201758 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.3 (Benchmark, messages #3) ---- Score : 99992 msgs/S, 199984 ctxswc/S +--- Score : 100879 msgs/S, 201758 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.4 (Benchmark, context switch) ---- Score : 380432 ctxswc/S +--- Score : 380632 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 78349 threads/S +--- Score : 78390 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 110375 threads/S +--- Score : 110433 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 31034 reschedules/S, 186204 ctxswc/S +--- Score : 31050 reschedules/S, 186300 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 253200 ctxswc/S +--- Score : 253332 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 298992 bytes/S +--- Score : 296368 bytes/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 350196 timers/S +--- Score : 350378 timers/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 591948 wait+signal/S +--- Score : 592280 wait+signal/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 334860 lock+unlock/S +--- Score : 335036 lock+unlock/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.13 (Benchmark, RAM footprint) diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.c b/os/ports/GCC/ARMCMx/chcore_v6m.c index 790761876..4e49e6256 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.c +++ b/os/ports/GCC/ARMCMx/chcore_v6m.c @@ -32,11 +32,6 @@ */ regarm_t _port_saved_pc; -/** - * @brief IRQ nesting counter. - */ -unsigned _port_irq_nesting; - /** * @brief System Timer vector. * @details This interrupt is used as system tick. diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h index 1bd2f777e..4b4ef04f6 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.h +++ b/os/ports/GCC/ARMCMx/chcore_v6m.h @@ -118,11 +118,9 @@ struct intctx { * @details This macro must be inserted at the start of all IRQ handlers * enabled to invoke system APIs. */ -#define PORT_IRQ_PROLOGUE() { \ - port_lock_from_isr(); \ - _port_irq_nesting++; \ - port_unlock_from_isr(); \ -} +#define PORT_IRQ_PROLOGUE() \ + regarm_t _saved_lr; \ + asm volatile ("mov %0, lr" : "=r" (_saved_lr) : : "memory") /** * @brief IRQ epilogue code. @@ -131,7 +129,7 @@ struct intctx { */ #define PORT_IRQ_EPILOGUE() { \ port_lock_from_isr(); \ - if ((--_port_irq_nesting == 0) && chSchIsRescRequiredExI()) { \ + if ((_saved_lr != (regarm_t)0xFFFFFFF1) && chSchIsRescRequiredExI()) { \ register struct cmxctx *ctxp; \ \ asm volatile ("mrs %0, PSP" : "=r" (ctxp) : ); \ @@ -160,7 +158,6 @@ struct intctx { * @brief Port-related initialization code. */ #define port_init() { \ - _port_irq_nesting = 0; \ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ @@ -229,7 +226,6 @@ struct intctx { #if !defined(__DOXYGEN__) extern regarm_t _port_saved_pc; -extern unsigned _port_irq_nesting; #endif #ifdef __cplusplus diff --git a/readme.txt b/readme.txt index 8516b1c41..6c5174cfa 100644 --- a/readme.txt +++ b/readme.txt @@ -69,6 +69,7 @@ ***************************************************************************** *** 2.3.0 *** +- FIX: Fixed race condition in CM0 ports (bug 3193062)(backported to 2.2.2). - FIX: Fixed Cortex-Mx linker scripts alignment of __heap_base__, the correct alignment is now enforced at runtime into core_init() in order to make the OS integration easier (bug 3191112)(backported to 2.2.2).