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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6099 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-08-07 14:07:06 +00:00
parent 68ea680d84
commit 9faa84cac8
11 changed files with 46 additions and 75 deletions
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18
os/halnew/platforms/STM32/USARTv2/serial_lld.c
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@ -422,43 +422,37 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
#if STM32_SERIAL_USE_USART1
if (&SD1 == sdp) {
rccEnableUSART1(FALSE);
nvicEnableVector(STM32_USART1_NUMBER,
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));
nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_USART2
if (&SD2 == sdp) {
rccEnableUSART2(FALSE);
nvicEnableVector(STM32_USART2_NUMBER,
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));
nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_USART3
if (&SD3 == sdp) {
rccEnableUSART3(FALSE);
nvicEnableVector(STM32_USART3_NUMBER,
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY));
nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_UART4
if (&SD4 == sdp) {
rccEnableUART4(FALSE);
nvicEnableVector(STM32_UART4_NUMBER,
CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY));
nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_UART5
if (&SD5 == sdp) {
rccEnableUART5(FALSE);
nvicEnableVector(STM32_UART5_NUMBER,
CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY));
nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_USART6
if (&SD6 == sdp) {
rccEnableUSART6(FALSE);
nvicEnableVector(STM32_USART6_NUMBER,
CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY));
nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY);
}
#endif
}

24
os/halnew/platforms/STM32/can_lld.c
View File

@ -394,14 +394,10 @@ void can_lld_start(CANDriver *canp) {
/* Clock activation.*/
#if STM32_CAN_USE_CAN1
if (&CAND1 == canp) {
nvicEnableVector(STM32_CAN1_TX_NUMBER,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
nvicEnableVector(STM32_CAN1_RX0_NUMBER,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
nvicEnableVector(STM32_CAN1_RX1_NUMBER,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
nvicEnableVector(STM32_CAN1_SCE_NUMBER,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
nvicEnableVector(STM32_CAN1_TX_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN1_RX0_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN1_RX1_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN1_SCE_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
rccEnableCAN1(FALSE);
}
#endif
@ -411,14 +407,10 @@ void can_lld_start(CANDriver *canp) {
osalDbgAssert(CAND1.state != CAN_STOP,
"can_lld_start(), #1", "CAN1 must be started");
nvicEnableVector(STM32_CAN2_TX_NUMBER,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
nvicEnableVector(STM32_CAN2_RX0_NUMBER,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
nvicEnableVector(STM32_CAN2_RX1_NUMBER,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
nvicEnableVector(STM32_CAN2_SCE_NUMBER,
CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
nvicEnableVector(STM32_CAN2_TX_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN2_RX0_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN2_RX1_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN2_SCE_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
rccEnableCAN2(FALSE);
}
#endif

27
os/halnew/platforms/STM32/icu_lld.c
View File

@ -400,10 +400,8 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD1 == icup) {
rccEnableTIM1(FALSE);
rccResetTIM1();
nvicEnableVector(STM32_TIM1_UP_NUMBER,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM1_CC_NUMBER,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_ICU_TIM1_IRQ_PRIORITY);
nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_ICU_TIM1_IRQ_PRIORITY);
icup->clock = STM32_TIMCLK2;
}
#endif
@ -411,8 +409,7 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD2 == icup) {
rccEnableTIM2(FALSE);
rccResetTIM2();
nvicEnableVector(STM32_TIM2_NUMBER,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM2_NUMBER, STM32_ICU_TIM2_IRQ_PRIORITY);
icup->clock = STM32_TIMCLK1;
}
#endif
@ -420,8 +417,7 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD3 == icup) {
rccEnableTIM3(FALSE);
rccResetTIM3();
nvicEnableVector(STM32_TIM3_NUMBER,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM3_NUMBER, STM32_ICU_TIM3_IRQ_PRIORITY);
icup->clock = STM32_TIMCLK1;
}
#endif
@ -429,8 +425,7 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD4 == icup) {
rccEnableTIM4(FALSE);
rccResetTIM4();
nvicEnableVector(STM32_TIM4_NUMBER,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM4_NUMBER, STM32_ICU_TIM4_IRQ_PRIORITY);
icup->clock = STM32_TIMCLK1;
}
#endif
@ -438,8 +433,7 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD5 == icup) {
rccEnableTIM5(FALSE);
rccResetTIM5();
nvicEnableVector(STM32_TIM5_NUMBER,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM5_NUMBER, STM32_ICU_TIM5_IRQ_PRIORITY);
icup->clock = STM32_TIMCLK1;
}
#endif
@ -447,10 +441,8 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD8 == icup) {
rccEnableTIM8(FALSE);
rccResetTIM8();
nvicEnableVector(STM32_TIM8_UP_NUMBER,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM8_CC_NUMBER,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_ICU_TIM8_IRQ_PRIORITY);
nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_ICU_TIM8_IRQ_PRIORITY);
icup->clock = STM32_TIMCLK2;
}
#endif
@ -458,8 +450,7 @@ void icu_lld_start(ICUDriver *icup) {
if (&ICUD9 == icup) {
rccEnableTIM9(FALSE);
rccResetTIM9();
nvicEnableVector(STM32_TIM9_NUMBER,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM9_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM9_NUMBER, STM32_ICU_TIM9_IRQ_PRIORITY);
icup->clock = STM32_TIMCLK1;
}
#endif

27
os/halnew/platforms/STM32/pwm_lld.c
View File

@ -407,10 +407,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD1 == pwmp) {
rccEnableTIM1(FALSE);
rccResetTIM1();
nvicEnableVector(STM32_TIM1_UP_NUMBER,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM1_CC_NUMBER,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_PWM_TIM1_IRQ_PRIORITY);
nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_PWM_TIM1_IRQ_PRIORITY);
pwmp->clock = STM32_TIMCLK2;
}
#endif
@ -418,8 +416,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD2 == pwmp) {
rccEnableTIM2(FALSE);
rccResetTIM2();
nvicEnableVector(STM32_TIM2_NUMBER,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM2_NUMBER, STM32_PWM_TIM2_IRQ_PRIORITY);
pwmp->clock = STM32_TIMCLK1;
}
#endif
@ -427,8 +424,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD3 == pwmp) {
rccEnableTIM3(FALSE);
rccResetTIM3();
nvicEnableVector(STM32_TIM3_NUMBER,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM3_NUMBER, STM32_PWM_TIM3_IRQ_PRIORITY);
pwmp->clock = STM32_TIMCLK1;
}
#endif
@ -436,8 +432,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD4 == pwmp) {
rccEnableTIM4(FALSE);
rccResetTIM4();
nvicEnableVector(STM32_TIM4_NUMBER,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM4_NUMBER, STM32_PWM_TIM4_IRQ_PRIORITY);
pwmp->clock = STM32_TIMCLK1;
}
#endif
@ -446,8 +441,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD5 == pwmp) {
rccEnableTIM5(FALSE);
rccResetTIM5();
nvicEnableVector(STM32_TIM5_NUMBER,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM5_NUMBER, STM32_PWM_TIM5_IRQ_PRIORITY);
pwmp->clock = STM32_TIMCLK1;
}
#endif
@ -455,10 +449,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD8 == pwmp) {
rccEnableTIM8(FALSE);
rccResetTIM8();
nvicEnableVector(STM32_TIM8_UP_NUMBER,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM8_CC_NUMBER,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_PWM_TIM8_IRQ_PRIORITY);
nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_PWM_TIM8_IRQ_PRIORITY);
pwmp->clock = STM32_TIMCLK2;
}
#endif
@ -466,8 +458,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
if (&PWMD9 == pwmp) {
rccEnableTIM9(FALSE);
rccResetTIM9();
nvicEnableVector(STM32_TIM9_NUMBER,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM9_IRQ_PRIORITY));
nvicEnableVector(STM32_TIM9_NUMBER, STM32_PWM_TIM9_IRQ_PRIORITY);
pwmp->clock = STM32_TIMCLK1;
}
#endif

9
os/halnew/platforms/STM32F30x/adc_lld.c
View File

@ -335,8 +335,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(ADC1_2_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_ADC12_IRQ_PRIORITY));
nvicEnableVector(ADC1_2_IRQn, STM32_ADC_ADC12_IRQ_PRIORITY);
#endif /* STM32_ADC_USE_ADC1 */
#if STM32_ADC_USE_ADC3
@ -353,11 +352,9 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(ADC3_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY));
nvicEnableVector(ADC3_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
#if STM32_ADC_DUAL_MODE
nvicEnableVector(ADC4_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY));
nvicEnableVector(ADC4_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
#endif
#endif /* STM32_ADC_USE_ADC3 */
}

3
os/halnew/platforms/STM32F30x/hal_lld.h
View File

@ -1085,7 +1085,8 @@
/* External declarations. */
/*===========================================================================*/
/* STM32 ISR, DMA and RCC helpers.*/
/* Various helpers.*/
#include "nvic.h"
#include "stm32_isr.h"
#include "stm32_dma.h"
#include "stm32_rcc.h"

2
os/halnew/platforms/STM32F30x/stm32_dma.c
View File

@ -403,7 +403,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
/* Enables the associated IRQ vector if a callback is defined.*/
if (func != NULL)
nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
nvicEnableVector(dmastp->vector, priority);
return FALSE;
}

2
os/halnew/platforms/common/ARMCMx/nvic.c
View File

@ -37,7 +37,7 @@
*/
void nvicEnableVector(uint32_t n, uint32_t prio) {
NVIC->IP[n] = prio << (8 - __NVIC_PRIO_BITS);
NVIC->IP[n] = NVIC_PRIORITY_MASK(prio);
NVIC->ICPR[n >> 5] = 1 << (n & 0x1F);
NVIC->ISER[n >> 5] = 1 << (n & 0x1F);
}

5
os/halnew/platforms/common/ARMCMx/nvic.h
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@ -29,6 +29,11 @@
#ifndef _NVIC_H_
#define _NVIC_H_
/**
* @brief Priority level to priority mask conversion macro.
*/
#define NVIC_PRIORITY_MASK(prio) ((prio) << (8 - __NVIC_PRIO_BITS))
#ifdef __cplusplus
extern "C" {
#endif

2
os/kernel/ports/ARMCMx/chcore.h
View File

@ -166,7 +166,7 @@ struct intctx {};
/**
* @brief Priority level to priority mask conversion macro.
*/
#define CORTEX_PRIORITY_MASK(n) \
#define CORTEX_PRIO_MASK(n) \
((n) << (8 - CORTEX_PRIORITY_BITS))
/*===========================================================================*/

2
os/kernel/ports/ARMCMx/chcore_v7m.h
View File

@ -197,7 +197,7 @@
* @note In compact kernel mode this constant value is enforced to zero.
*/
#define CORTEX_BASEPRI_KERNEL \
CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY)
CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
#else
#define CORTEX_MAX_KERNEL_PRIORITY 1