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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6160 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-08-15 15:31:06 +00:00
parent 44fe821ab4
commit 9dcb2a31c0
2 changed files with 7 additions and 7 deletions
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12
os/hal/platforms/STM32/TIMv1/stm32_tim.h
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@ -180,7 +180,7 @@
#define STM32_TIM_CCMR1_OC1PE (1U << 3) #define STM32_TIM_CCMR1_OC1PE (1U << 3)
#define STM32_TIM_CCMR1_OC1M_MASK ((7U << 4) | (1U << 16)) #define STM32_TIM_CCMR1_OC1M_MASK ((7U << 4) | (1U << 16))
#define STM32_TIM_CCMR1_OC1M(n) ((((n) & 3) << 4) | \ #define STM32_TIM_CCMR1_OC1M(n) ((((n) & 7) << 4) | \
(((n) >> 2) << 16)) (((n) >> 2) << 16))
#define STM32_TIM_CCMR1_OC1CE (1U << 7) #define STM32_TIM_CCMR1_OC1CE (1U << 7)
@ -192,7 +192,7 @@
#define STM32_TIM_CCMR1_OC2PE (1U << 11) #define STM32_TIM_CCMR1_OC2PE (1U << 11)
#define STM32_TIM_CCMR1_OC2M_MASK ((7U << 12) | (1U << 24)) #define STM32_TIM_CCMR1_OC2M_MASK ((7U << 12) | (1U << 24))
#define STM32_TIM_CCMR1_OC2M(n) ((((n) & 3) << 12) | \ #define STM32_TIM_CCMR1_OC2M(n) ((((n) & 7) << 12) | \
(((n) >> 2) << 24)) (((n) >> 2) << 24))
#define STM32_TIM_CCMR1_OC2CE (1U << 15) #define STM32_TIM_CCMR1_OC2CE (1U << 15)
@ -226,7 +226,7 @@
#define STM32_TIM_CCMR2_OC3PE (1U << 3) #define STM32_TIM_CCMR2_OC3PE (1U << 3)
#define STM32_TIM_CCMR2_OC3M_MASK ((7U << 4) | (1U << 16)) #define STM32_TIM_CCMR2_OC3M_MASK ((7U << 4) | (1U << 16))
#define STM32_TIM_CCMR2_OC3M(n) ((((n) & 3) << 4) | \ #define STM32_TIM_CCMR2_OC3M(n) ((((n) & 7) << 4) | \
(((n) >> 2) << 16)) (((n) >> 2) << 16))
#define STM32_TIM_CCMR2_OC3CE (1U << 7) #define STM32_TIM_CCMR2_OC3CE (1U << 7)
@ -238,7 +238,7 @@
#define STM32_TIM_CCMR2_OC4PE (1U << 11) #define STM32_TIM_CCMR2_OC4PE (1U << 11)
#define STM32_TIM_CCMR2_OC4M_MASK ((7U << 12) | (1U << 24)) #define STM32_TIM_CCMR2_OC4M_MASK ((7U << 12) | (1U << 24))
#define STM32_TIM_CCMR2_OC4M(n) ((((n) & 3) << 12) | \ #define STM32_TIM_CCMR2_OC4M(n) ((((n) & 7) << 12) | \
(((n) >> 2) << 24)) (((n) >> 2) << 24))
#define STM32_TIM_CCMR2_OC4CE (1U << 15) #define STM32_TIM_CCMR2_OC4CE (1U << 15)
@ -354,7 +354,7 @@
#define STM32_TIM_CCMR3_OC5PE (1U << 3) #define STM32_TIM_CCMR3_OC5PE (1U << 3)
#define STM32_TIM_CCMR3_OC5M_MASK ((7U << 4) | (1U << 16)) #define STM32_TIM_CCMR3_OC5M_MASK ((7U << 4) | (1U << 16))
#define STM32_TIM_CCMR3_OC5M(n) ((((n) & 3) << 4) | \ #define STM32_TIM_CCMR3_OC5M(n) ((((n) & 7) << 4) | \
(((n) >> 2) << 16)) (((n) >> 2) << 16))
#define STM32_TIM_CCMR3_OC5CE (1U << 7) #define STM32_TIM_CCMR3_OC5CE (1U << 7)
@ -363,7 +363,7 @@
#define STM32_TIM_CCMR3_OC6PE (1U << 11) #define STM32_TIM_CCMR3_OC6PE (1U << 11)
#define STM32_TIM_CCMR3_OC6M_MASK ((7U << 12) | (1U << 24)) #define STM32_TIM_CCMR3_OC6M_MASK ((7U << 12) | (1U << 24))
#define STM32_TIM_CCMR3_OC6M(n) ((((n) & 3) << 12) | \ #define STM32_TIM_CCMR3_OC6M(n) ((((n) & 7) << 12) | \
(((n) >> 2) << 24)) (((n) >> 2) << 24))
#define STM32_TIM_CCMR3_OC6CE (1U << 15) #define STM32_TIM_CCMR3_OC6CE (1U << 15)