STM32 SPI driver divided in two distinct implementations.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4877 35acf78f-673a-0410-8e92-d51de3d6d3f4master
gdisirio
parent
c8f3291765
commit
9d3e7a8fbc
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@ -19,7 +19,7 @@
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*/
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*/
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/**
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/**
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* @file STM32/spi_lld.c
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* @file STM32/SPIv1/spi_lld.c
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* @brief STM32 SPI subsystem low level driver source.
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* @brief STM32 SPI subsystem low level driver source.
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*
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*
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* @addtogroup SPI
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* @addtogroup SPI
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@ -273,12 +273,7 @@ void spi_lld_start(SPIDriver *spip) {
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}
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}
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/* Configuration-specific DMA setup.*/
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/* Configuration-specific DMA setup.*/
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#if defined(STM32F0XX) || defined(STM32F30X)
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if ((spip->config->cr1 & SPI_CR2_DS) <
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(SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)) {
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#else /* !defined(STM32F0XX) */
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if ((spip->config->cr1 & SPI_CR1_DFF) == 0) {
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if ((spip->config->cr1 & SPI_CR1_DFF) == 0) {
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#endif /* !defined(STM32F0XX) */
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/* Frame width is 8 bits or smaller.*/
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/* Frame width is 8 bits or smaller.*/
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spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
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spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
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STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
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STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
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@ -314,6 +309,7 @@ void spi_lld_stop(SPIDriver *spip) {
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/* SPI disable.*/
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/* SPI disable.*/
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spip->spi->CR1 = 0;
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spip->spi->CR1 = 0;
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spip->spi->CR2 = 0;
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dmaStreamRelease(spip->dmarx);
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dmaStreamRelease(spip->dmarx);
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dmaStreamRelease(spip->dmatx);
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dmaStreamRelease(spip->dmatx);
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@ -0,0 +1,415 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/SPIv1/spi_lld.h
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* @brief STM32 SPI subsystem low level driver header.
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*
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* @addtogroup SPI
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* @{
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*/
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#ifndef _SPI_LLD_H_
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#define _SPI_LLD_H_
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#if HAL_USE_SPI || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief SPI1 driver enable switch.
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* @details If set to @p TRUE the support for SPI1 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI1 FALSE
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#endif
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/**
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* @brief SPI2 driver enable switch.
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* @details If set to @p TRUE the support for SPI2 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI2 FALSE
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#endif
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/**
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* @brief SPI3 driver enable switch.
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* @details If set to @p TRUE the support for SPI3 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI3 FALSE
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#endif
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/**
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* @brief SPI1 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI2 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI3 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI1 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI2 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI3 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI DMA error hook.
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*/
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#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
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#endif
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#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
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/**
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* @brief DMA stream used for SPI1 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
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#endif
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/**
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* @brief DMA stream used for SPI1 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#endif
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/**
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* @brief DMA stream used for SPI2 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#endif
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/**
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* @brief DMA stream used for SPI2 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#endif
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/**
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* @brief DMA stream used for SPI3 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#endif
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/**
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* @brief DMA stream used for SPI3 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#endif
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#else /* !STM32_ADVANCED_DMA */
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/* Fixed streams for platforms using the old DMA peripheral, the values are
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valid for both STM32F1xx and STM32L1xx.*/
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#endif /* !STM32_ADVANCED_DMA*/
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1
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#error "SPI1 not present in the selected device"
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#endif
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#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2
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#error "SPI2 not present in the selected device"
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#endif
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#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3
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#error "SPI3 not present in the selected device"
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#endif
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#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3
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#error "SPI driver activated but no SPI peripheral assigned"
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#endif
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#if STM32_SPI_USE_SPI1 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI1"
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#endif
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#if STM32_SPI_USE_SPI2 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI2"
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#endif
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#if STM32_SPI_USE_SPI3 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI3"
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#endif
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#if STM32_SPI_USE_SPI1 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to SPI1"
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#endif
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#if STM32_SPI_USE_SPI2 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to SPI2"
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#endif
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#if STM32_SPI_USE_SPI3 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to SPI3"
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#endif
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#if STM32_SPI_USE_SPI1 && \
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!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
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#error "invalid DMA stream associated to SPI1 RX"
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#endif
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#if STM32_SPI_USE_SPI1 && \
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!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
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#error "invalid DMA stream associated to SPI1 TX"
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#endif
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#if STM32_SPI_USE_SPI2 && \
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!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
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#error "invalid DMA stream associated to SPI2 RX"
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#endif
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#if STM32_SPI_USE_SPI2 && \
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!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
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#error "invalid DMA stream associated to SPI2 TX"
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#endif
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#if STM32_SPI_USE_SPI3 && \
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!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
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#error "invalid DMA stream associated to SPI3 RX"
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#endif
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#if STM32_SPI_USE_SPI3 && \
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!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
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#error "invalid DMA stream associated to SPI3 TX"
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#endif
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type of a structure representing an SPI driver.
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*/
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typedef struct SPIDriver SPIDriver;
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/**
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* @brief SPI notification callback type.
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*
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* @param[in] spip pointer to the @p SPIDriver object triggering the
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* callback
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*/
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typedef void (*spicallback_t)(SPIDriver *spip);
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/**
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* @brief Driver configuration structure.
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*/
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typedef struct {
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/**
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* @brief Operation complete callback or @p NULL.
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*/
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spicallback_t end_cb;
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/* End of the mandatory fields.*/
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/**
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* @brief The chip select line port.
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*/
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ioportid_t ssport;
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/**
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* @brief The chip select line pad number.
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*/
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uint16_t sspad;
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/**
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* @brief SPI initialization data.
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*/
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uint16_t cr1;
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} SPIConfig;
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/**
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* @brief Structure representing a SPI driver.
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*/
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struct SPIDriver{
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/**
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* @brief Driver state.
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*/
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spistate_t state;
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/**
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* @brief Current configuration data.
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*/
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const SPIConfig *config;
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#if SPI_USE_WAIT || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief Waiting thread.
|
||||||
|
*/
|
||||||
|
Thread *thread;
|
||||||
|
#endif /* SPI_USE_WAIT */
|
||||||
|
#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
||||||
|
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief Mutex protecting the bus.
|
||||||
|
*/
|
||||||
|
Mutex mutex;
|
||||||
|
#elif CH_USE_SEMAPHORES
|
||||||
|
Semaphore semaphore;
|
||||||
|
#endif
|
||||||
|
#endif /* SPI_USE_MUTUAL_EXCLUSION */
|
||||||
|
#if defined(SPI_DRIVER_EXT_FIELDS)
|
||||||
|
SPI_DRIVER_EXT_FIELDS
|
||||||
|
#endif
|
||||||
|
/* End of the mandatory fields.*/
|
||||||
|
/**
|
||||||
|
* @brief Pointer to the SPIx registers block.
|
||||||
|
*/
|
||||||
|
SPI_TypeDef *spi;
|
||||||
|
/**
|
||||||
|
* @brief Receive DMA stream.
|
||||||
|
*/
|
||||||
|
const stm32_dma_stream_t *dmarx;
|
||||||
|
/**
|
||||||
|
* @brief Transmit DMA stream.
|
||||||
|
*/
|
||||||
|
const stm32_dma_stream_t *dmatx;
|
||||||
|
/**
|
||||||
|
* @brief RX DMA mode bit mask.
|
||||||
|
*/
|
||||||
|
uint32_t rxdmamode;
|
||||||
|
/**
|
||||||
|
* @brief TX DMA mode bit mask.
|
||||||
|
*/
|
||||||
|
uint32_t txdmamode;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver macros. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* External declarations. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
|
||||||
|
extern SPIDriver SPID1;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
|
||||||
|
extern SPIDriver SPID2;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
|
||||||
|
extern SPIDriver SPID3;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
void spi_lld_init(void);
|
||||||
|
void spi_lld_start(SPIDriver *spip);
|
||||||
|
void spi_lld_stop(SPIDriver *spip);
|
||||||
|
void spi_lld_select(SPIDriver *spip);
|
||||||
|
void spi_lld_unselect(SPIDriver *spip);
|
||||||
|
void spi_lld_ignore(SPIDriver *spip, size_t n);
|
||||||
|
void spi_lld_exchange(SPIDriver *spip, size_t n,
|
||||||
|
const void *txbuf, void *rxbuf);
|
||||||
|
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
|
||||||
|
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
|
||||||
|
uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* HAL_USE_SPI */
|
||||||
|
|
||||||
|
#endif /* _SPI_LLD_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -0,0 +1,490 @@
|
||||||
|
/*
|
||||||
|
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||||
|
2011,2012 Giovanni Di Sirio.
|
||||||
|
|
||||||
|
This file is part of ChibiOS/RT.
|
||||||
|
|
||||||
|
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file STM32/SPIv2/spi_lld.c
|
||||||
|
* @brief STM32 SPI subsystem low level driver source.
|
||||||
|
*
|
||||||
|
* @addtogroup SPI
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ch.h"
|
||||||
|
#include "hal.h"
|
||||||
|
|
||||||
|
#if HAL_USE_SPI || defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver local definitions. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#define SPI1_RX_DMA_CHANNEL \
|
||||||
|
STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \
|
||||||
|
STM32_SPI1_RX_DMA_CHN)
|
||||||
|
|
||||||
|
#define SPI1_TX_DMA_CHANNEL \
|
||||||
|
STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \
|
||||||
|
STM32_SPI1_TX_DMA_CHN)
|
||||||
|
|
||||||
|
#define SPI2_RX_DMA_CHANNEL \
|
||||||
|
STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \
|
||||||
|
STM32_SPI2_RX_DMA_CHN)
|
||||||
|
|
||||||
|
#define SPI2_TX_DMA_CHANNEL \
|
||||||
|
STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \
|
||||||
|
STM32_SPI2_TX_DMA_CHN)
|
||||||
|
|
||||||
|
#define SPI3_RX_DMA_CHANNEL \
|
||||||
|
STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \
|
||||||
|
STM32_SPI3_RX_DMA_CHN)
|
||||||
|
|
||||||
|
#define SPI3_TX_DMA_CHANNEL \
|
||||||
|
STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \
|
||||||
|
STM32_SPI3_TX_DMA_CHN)
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver exported variables. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/** @brief SPI1 driver identifier.*/
|
||||||
|
#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
|
||||||
|
SPIDriver SPID1;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @brief SPI2 driver identifier.*/
|
||||||
|
#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)
|
||||||
|
SPIDriver SPID2;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @brief SPI3 driver identifier.*/
|
||||||
|
#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)
|
||||||
|
SPIDriver SPID3;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver local variables. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
static uint16_t dummytx;
|
||||||
|
static uint16_t dummyrx;
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver local functions. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Shared end-of-rx service routine.
|
||||||
|
*
|
||||||
|
* @param[in] spip pointer to the @p SPIDriver object
|
||||||
|
* @param[in] flags pre-shifted content of the ISR register
|
||||||
|
*/
|
||||||
|
static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
|
||||||
|
|
||||||
|
/* DMA errors handling.*/
|
||||||
|
#if defined(STM32_SPI_DMA_ERROR_HOOK)
|
||||||
|
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
|
||||||
|
STM32_SPI_DMA_ERROR_HOOK(spip);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
(void)flags;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Stop everything.*/
|
||||||
|
dmaStreamDisable(spip->dmatx);
|
||||||
|
dmaStreamDisable(spip->dmarx);
|
||||||
|
|
||||||
|
/* Portable SPI ISR code defined in the high level driver, note, it is
|
||||||
|
a macro.*/
|
||||||
|
_spi_isr_code(spip);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Shared end-of-tx service routine.
|
||||||
|
*
|
||||||
|
* @param[in] spip pointer to the @p SPIDriver object
|
||||||
|
* @param[in] flags pre-shifted content of the ISR register
|
||||||
|
*/
|
||||||
|
static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
|
||||||
|
|
||||||
|
/* DMA errors handling.*/
|
||||||
|
#if defined(STM32_SPI_DMA_ERROR_HOOK)
|
||||||
|
(void)spip;
|
||||||
|
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
|
||||||
|
STM32_SPI_DMA_ERROR_HOOK(spip);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
(void)spip;
|
||||||
|
(void)flags;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver interrupt handlers. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver exported functions. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Low level SPI driver initialization.
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void spi_lld_init(void) {
|
||||||
|
|
||||||
|
dummytx = 0xFFFF;
|
||||||
|
|
||||||
|
#if STM32_SPI_USE_SPI1
|
||||||
|
spiObjectInit(&SPID1);
|
||||||
|
SPID1.spi = SPI1;
|
||||||
|
SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
|
||||||
|
SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
|
||||||
|
SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
|
||||||
|
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
|
||||||
|
STM32_DMA_CR_DIR_P2M |
|
||||||
|
STM32_DMA_CR_TCIE |
|
||||||
|
STM32_DMA_CR_DMEIE |
|
||||||
|
STM32_DMA_CR_TEIE;
|
||||||
|
SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
|
||||||
|
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
|
||||||
|
STM32_DMA_CR_DIR_M2P |
|
||||||
|
STM32_DMA_CR_DMEIE |
|
||||||
|
STM32_DMA_CR_TEIE;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_SPI_USE_SPI2
|
||||||
|
spiObjectInit(&SPID2);
|
||||||
|
SPID2.spi = SPI2;
|
||||||
|
SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
|
||||||
|
SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
|
||||||
|
SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
|
||||||
|
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
|
||||||
|
STM32_DMA_CR_DIR_P2M |
|
||||||
|
STM32_DMA_CR_TCIE |
|
||||||
|
STM32_DMA_CR_DMEIE |
|
||||||
|
STM32_DMA_CR_TEIE;
|
||||||
|
SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
|
||||||
|
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
|
||||||
|
STM32_DMA_CR_DIR_M2P |
|
||||||
|
STM32_DMA_CR_DMEIE |
|
||||||
|
STM32_DMA_CR_TEIE;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_SPI_USE_SPI3
|
||||||
|
spiObjectInit(&SPID3);
|
||||||
|
SPID3.spi = SPI3;
|
||||||
|
SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
|
||||||
|
SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
|
||||||
|
SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
|
||||||
|
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
|
||||||
|
STM32_DMA_CR_DIR_P2M |
|
||||||
|
STM32_DMA_CR_TCIE |
|
||||||
|
STM32_DMA_CR_DMEIE |
|
||||||
|
STM32_DMA_CR_TEIE;
|
||||||
|
SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
|
||||||
|
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
|
||||||
|
STM32_DMA_CR_DIR_M2P |
|
||||||
|
STM32_DMA_CR_DMEIE |
|
||||||
|
STM32_DMA_CR_TEIE;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures and activates the SPI peripheral.
|
||||||
|
*
|
||||||
|
* @param[in] spip pointer to the @p SPIDriver object
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void spi_lld_start(SPIDriver *spip) {
|
||||||
|
uint32_t ds;
|
||||||
|
|
||||||
|
/* If in stopped state then enables the SPI and DMA clocks.*/
|
||||||
|
if (spip->state == SPI_STOP) {
|
||||||
|
#if STM32_SPI_USE_SPI1
|
||||||
|
if (&SPID1 == spip) {
|
||||||
|
bool_t b;
|
||||||
|
b = dmaStreamAllocate(spip->dmarx,
|
||||||
|
STM32_SPI_SPI1_IRQ_PRIORITY,
|
||||||
|
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
|
||||||
|
(void *)spip);
|
||||||
|
chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated");
|
||||||
|
b = dmaStreamAllocate(spip->dmatx,
|
||||||
|
STM32_SPI_SPI1_IRQ_PRIORITY,
|
||||||
|
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
|
||||||
|
(void *)spip);
|
||||||
|
chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated");
|
||||||
|
rccEnableSPI1(FALSE);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#if STM32_SPI_USE_SPI2
|
||||||
|
if (&SPID2 == spip) {
|
||||||
|
bool_t b;
|
||||||
|
b = dmaStreamAllocate(spip->dmarx,
|
||||||
|
STM32_SPI_SPI2_IRQ_PRIORITY,
|
||||||
|
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
|
||||||
|
(void *)spip);
|
||||||
|
chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated");
|
||||||
|
b = dmaStreamAllocate(spip->dmatx,
|
||||||
|
STM32_SPI_SPI2_IRQ_PRIORITY,
|
||||||
|
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
|
||||||
|
(void *)spip);
|
||||||
|
chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated");
|
||||||
|
rccEnableSPI2(FALSE);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#if STM32_SPI_USE_SPI3
|
||||||
|
if (&SPID3 == spip) {
|
||||||
|
bool_t b;
|
||||||
|
b = dmaStreamAllocate(spip->dmarx,
|
||||||
|
STM32_SPI_SPI3_IRQ_PRIORITY,
|
||||||
|
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
|
||||||
|
(void *)spip);
|
||||||
|
chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated");
|
||||||
|
b = dmaStreamAllocate(spip->dmatx,
|
||||||
|
STM32_SPI_SPI3_IRQ_PRIORITY,
|
||||||
|
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
|
||||||
|
(void *)spip);
|
||||||
|
chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated");
|
||||||
|
rccEnableSPI3(FALSE);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* DMA setup.*/
|
||||||
|
dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR);
|
||||||
|
dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Configuration-specific DMA setup.*/
|
||||||
|
ds = spip->config->cr2 & SPI_CR2_DS;
|
||||||
|
if (!ds || (ds <= (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0))) {
|
||||||
|
/* Frame width is 8 bits or smaller.*/
|
||||||
|
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
|
||||||
|
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
|
||||||
|
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
|
||||||
|
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
/* Frame width is larger than 8 bits.*/
|
||||||
|
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
|
||||||
|
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
|
||||||
|
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
|
||||||
|
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
|
||||||
|
}
|
||||||
|
/* SPI setup and enable.*/
|
||||||
|
spip->spi->CR1 = 0;
|
||||||
|
spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM |
|
||||||
|
SPI_CR1_SSI;
|
||||||
|
spip->spi->CR2 = spip->config->cr2 | SPI_CR2_SSOE |
|
||||||
|
SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
|
||||||
|
spip->spi->CR1 |= SPI_CR1_SPE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deactivates the SPI peripheral.
|
||||||
|
*
|
||||||
|
* @param[in] spip pointer to the @p SPIDriver object
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void spi_lld_stop(SPIDriver *spip) {
|
||||||
|
|
||||||
|
/* If in ready state then disables the SPI clock.*/
|
||||||
|
if (spip->state == SPI_READY) {
|
||||||
|
|
||||||
|
/* SPI disable.*/
|
||||||
|
spip->spi->CR1 = 0;
|
||||||
|
spip->spi->CR2 = 0;
|
||||||
|
dmaStreamRelease(spip->dmarx);
|
||||||
|
dmaStreamRelease(spip->dmatx);
|
||||||
|
|
||||||
|
#if STM32_SPI_USE_SPI1
|
||||||
|
if (&SPID1 == spip)
|
||||||
|
rccDisableSPI1(FALSE);
|
||||||
|
#endif
|
||||||
|
#if STM32_SPI_USE_SPI2
|
||||||
|
if (&SPID2 == spip)
|
||||||
|
rccDisableSPI2(FALSE);
|
||||||
|
#endif
|
||||||
|
#if STM32_SPI_USE_SPI3
|
||||||
|
if (&SPID3 == spip)
|
||||||
|
rccDisableSPI3(FALSE);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Asserts the slave select signal and prepares for transfers.
|
||||||
|
*
|
||||||
|
* @param[in] spip pointer to the @p SPIDriver object
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void spi_lld_select(SPIDriver *spip) {
|
||||||
|
|
||||||
|
palClearPad(spip->config->ssport, spip->config->sspad);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deasserts the slave select signal.
|
||||||
|
* @details The previously selected peripheral is unselected.
|
||||||
|
*
|
||||||
|
* @param[in] spip pointer to the @p SPIDriver object
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void spi_lld_unselect(SPIDriver *spip) {
|
||||||
|
|
||||||
|
palSetPad(spip->config->ssport, spip->config->sspad);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Ignores data on the SPI bus.
|
||||||
|
* @details This asynchronous function starts the transmission of a series of
|
||||||
|
* idle words on the SPI bus and ignores the received data.
|
||||||
|
* @post At the end of the operation the configured callback is invoked.
|
||||||
|
*
|
||||||
|
* @param[in] spip pointer to the @p SPIDriver object
|
||||||
|
* @param[in] n number of words to be ignored
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void spi_lld_ignore(SPIDriver *spip, size_t n) {
|
||||||
|
|
||||||
|
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
|
||||||
|
dmaStreamSetTransactionSize(spip->dmarx, n);
|
||||||
|
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
|
||||||
|
|
||||||
|
dmaStreamSetMemory0(spip->dmatx, &dummytx);
|
||||||
|
dmaStreamSetTransactionSize(spip->dmatx, n);
|
||||||
|
dmaStreamSetMode(spip->dmatx, spip->txdmamode);
|
||||||
|
|
||||||
|
dmaStreamEnable(spip->dmarx);
|
||||||
|
dmaStreamEnable(spip->dmatx);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Exchanges data on the SPI bus.
|
||||||
|
* @details This asynchronous function starts a simultaneous transmit/receive
|
||||||
|
* operation.
|
||||||
|
* @post At the end of the operation the configured callback is invoked.
|
||||||
|
* @note The buffers are organized as uint8_t arrays for data sizes below or
|
||||||
|
* equal to 8 bits else it is organized as uint16_t arrays.
|
||||||
|
*
|
||||||
|
* @param[in] spip pointer to the @p SPIDriver object
|
||||||
|
* @param[in] n number of words to be exchanged
|
||||||
|
* @param[in] txbuf the pointer to the transmit buffer
|
||||||
|
* @param[out] rxbuf the pointer to the receive buffer
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void spi_lld_exchange(SPIDriver *spip, size_t n,
|
||||||
|
const void *txbuf, void *rxbuf) {
|
||||||
|
|
||||||
|
dmaStreamSetMemory0(spip->dmarx, rxbuf);
|
||||||
|
dmaStreamSetTransactionSize(spip->dmarx, n);
|
||||||
|
dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC);
|
||||||
|
|
||||||
|
dmaStreamSetMemory0(spip->dmatx, txbuf);
|
||||||
|
dmaStreamSetTransactionSize(spip->dmatx, n);
|
||||||
|
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
|
||||||
|
|
||||||
|
dmaStreamEnable(spip->dmarx);
|
||||||
|
dmaStreamEnable(spip->dmatx);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sends data over the SPI bus.
|
||||||
|
* @details This asynchronous function starts a transmit operation.
|
||||||
|
* @post At the end of the operation the configured callback is invoked.
|
||||||
|
* @note The buffers are organized as uint8_t arrays for data sizes below or
|
||||||
|
* equal to 8 bits else it is organized as uint16_t arrays.
|
||||||
|
*
|
||||||
|
* @param[in] spip pointer to the @p SPIDriver object
|
||||||
|
* @param[in] n number of words to send
|
||||||
|
* @param[in] txbuf the pointer to the transmit buffer
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
|
||||||
|
|
||||||
|
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
|
||||||
|
dmaStreamSetTransactionSize(spip->dmarx, n);
|
||||||
|
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
|
||||||
|
|
||||||
|
dmaStreamSetMemory0(spip->dmatx, txbuf);
|
||||||
|
dmaStreamSetTransactionSize(spip->dmatx, n);
|
||||||
|
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
|
||||||
|
|
||||||
|
dmaStreamEnable(spip->dmarx);
|
||||||
|
dmaStreamEnable(spip->dmatx);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Receives data from the SPI bus.
|
||||||
|
* @details This asynchronous function starts a receive operation.
|
||||||
|
* @post At the end of the operation the configured callback is invoked.
|
||||||
|
* @note The buffers are organized as uint8_t arrays for data sizes below or
|
||||||
|
* equal to 8 bits else it is organized as uint16_t arrays.
|
||||||
|
*
|
||||||
|
* @param[in] spip pointer to the @p SPIDriver object
|
||||||
|
* @param[in] n number of words to receive
|
||||||
|
* @param[out] rxbuf the pointer to the receive buffer
|
||||||
|
*
|
||||||
|
* @notapi
|
||||||
|
*/
|
||||||
|
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
|
||||||
|
|
||||||
|
dmaStreamSetMemory0(spip->dmarx, rxbuf);
|
||||||
|
dmaStreamSetTransactionSize(spip->dmarx, n);
|
||||||
|
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
|
||||||
|
|
||||||
|
dmaStreamSetMemory0(spip->dmatx, &dummytx);
|
||||||
|
dmaStreamSetTransactionSize(spip->dmatx, n);
|
||||||
|
dmaStreamSetMode(spip->dmatx, spip->txdmamode);
|
||||||
|
|
||||||
|
dmaStreamEnable(spip->dmarx);
|
||||||
|
dmaStreamEnable(spip->dmatx);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Exchanges one frame using a polled wait.
|
||||||
|
* @details This synchronous function exchanges one frame using a polled
|
||||||
|
* synchronization method. This function is useful when exchanging
|
||||||
|
* small amount of data on high speed channels, usually in this
|
||||||
|
* situation is much more efficient just wait for completion using
|
||||||
|
* polling than suspending the thread waiting for an interrupt.
|
||||||
|
*
|
||||||
|
* @param[in] spip pointer to the @p SPIDriver object
|
||||||
|
* @param[in] frame the data frame to send over the SPI bus
|
||||||
|
* @return The received data frame from the SPI bus.
|
||||||
|
*/
|
||||||
|
uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
|
||||||
|
|
||||||
|
spip->spi->DR = frame;
|
||||||
|
while ((spip->spi->SR & SPI_SR_RXNE) == 0)
|
||||||
|
;
|
||||||
|
return spip->spi->DR;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* HAL_USE_SPI */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -19,7 +19,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @file STM32/spi_lld.h
|
* @file STM32/SPIv2/spi_lld.h
|
||||||
* @brief STM32 SPI subsystem low level driver header.
|
* @brief STM32 SPI subsystem low level driver header.
|
||||||
*
|
*
|
||||||
* @addtogroup SPI
|
* @addtogroup SPI
|
||||||
|
|
@ -189,7 +189,7 @@
|
||||||
|
|
||||||
#else /* !defined(STM32F0XX) */
|
#else /* !defined(STM32F0XX) */
|
||||||
/* Fixed streams for platforms using the old DMA peripheral, the values are
|
/* Fixed streams for platforms using the old DMA peripheral, the values are
|
||||||
valid for both STM32F1xx, STM32L1xx and STM32F3xx.*/
|
valid for STM32F3xx.*/
|
||||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
|
@ -320,9 +320,13 @@ typedef struct {
|
||||||
*/
|
*/
|
||||||
uint16_t sspad;
|
uint16_t sspad;
|
||||||
/**
|
/**
|
||||||
* @brief SPI initialization data.
|
* @brief SPI CR1 register initialization data.
|
||||||
*/
|
*/
|
||||||
uint16_t cr1;
|
uint16_t cr1;
|
||||||
|
/**
|
||||||
|
* @brief SPI CR2 register initialization data.
|
||||||
|
*/
|
||||||
|
uint16_t cr2;
|
||||||
} SPIConfig;
|
} SPIConfig;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -7,8 +7,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
|
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
|
||||||
|
${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
|
||||||
|
|
||||||
|
|
@ -16,4 +16,5 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
|
||||||
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
|
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32 \
|
${CHIBIOS}/os/hal/platforms/STM32 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
|
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
|
||||||
|
${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv2
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv2
|
||||||
|
|
|
||||||
|
|
@ -10,10 +10,10 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
|
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \
|
||||||
|
${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
|
${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
|
||||||
|
|
@ -24,6 +24,7 @@ PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \
|
${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
|
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \
|
${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \
|
||||||
|
${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USBv1
|
${CHIBIOS}/os/hal/platforms/STM32/USBv1
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -2,11 +2,12 @@
|
||||||
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F3xx/stm32_dma.c \
|
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F3xx/stm32_dma.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32F3xx/hal_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32F3xx/hal_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c
|
||||||
|
|
||||||
# Required include directories
|
# Required include directories
|
||||||
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F3xx \
|
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F3xx \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32 \
|
${CHIBIOS}/os/hal/platforms/STM32 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
|
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
|
||||||
|
${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv2
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv2
|
||||||
|
|
|
||||||
|
|
@ -10,11 +10,11 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
|
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \
|
||||||
|
${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c
|
||||||
|
|
||||||
|
|
@ -25,4 +25,5 @@ PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F4xx \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
|
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/OTGv1 \
|
${CHIBIOS}/os/hal/platforms/STM32/OTGv1 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
|
${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
|
||||||
|
${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv1
|
||||||
|
|
|
||||||
|
|
@ -7,9 +7,9 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
|
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
|
||||||
|
${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
|
${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
|
||||||
|
|
@ -19,5 +19,6 @@ PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32L1xx \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32 \
|
${CHIBIOS}/os/hal/platforms/STM32 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
|
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
|
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
|
||||||
|
${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
|
${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
|
||||||
${CHIBIOS}/os/hal/platforms/STM32/USBv1
|
${CHIBIOS}/os/hal/platforms/STM32/USBv1
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue