git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5257 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
3b951cfb37
commit
9c15492e2d
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@ -6,7 +6,7 @@ Settings: SYSCLK=64
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*** ChibiOS/RT test suite
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***
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*** Kernel: 2.5.2unstable
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*** Compiled: Feb 15 2013 - 12:24:06
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*** Compiled: Feb 19 2013 - 11:15:43
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*** Compiler: GCC 4.6.3 build on 2013-01-07
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*** Architecture: Power Architecture
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*** Core Variant: e200z0
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@ -100,7 +100,7 @@ Settings: SYSCLK=64
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.1 (Benchmark, messages #1)
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--- Score : 200707 msgs/S, 401414 ctxswc/S
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--- Score : 200701 msgs/S, 401402 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.2 (Benchmark, messages #2)
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@ -108,23 +108,23 @@ Settings: SYSCLK=64
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.3 (Benchmark, messages #3)
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--- Score : 167515 msgs/S, 335030 ctxswc/S
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--- Score : 167519 msgs/S, 335038 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.4 (Benchmark, context switch)
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--- Score : 590272 ctxswc/S
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--- Score : 590288 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.5 (Benchmark, threads, full cycle)
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--- Score : 132964 threads/S
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--- Score : 132967 threads/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.6 (Benchmark, threads, create only)
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--- Score : 189949 threads/S
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--- Score : 189947 threads/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
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--- Score : 51973 reschedules/S, 311838 ctxswc/S
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--- Score : 51972 reschedules/S, 311832 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.8 (Benchmark, round robin context switching)
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@ -132,19 +132,19 @@ Settings: SYSCLK=64
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.9 (Benchmark, I/O Queues throughput)
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--- Score : 619272 bytes/S
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--- Score : 619280 bytes/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.10 (Benchmark, virtual timers set/reset)
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--- Score : 802792 timers/S
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--- Score : 802802 timers/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.11 (Benchmark, semaphores wait/signal)
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--- Score : 818236 wait+signal/S
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--- Score : 818244 wait+signal/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
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--- Score : 643052 lock+unlock/S
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--- Score : 643028 lock+unlock/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.13 (Benchmark, RAM footprint)
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@ -144,6 +144,11 @@ void spc_clock_init(void) {
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CGM.OSC_CTL.B.OSCBYP = TRUE;
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#endif /* SPC5_OSC_BYPASS */
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/* Setting the various dividers and source selectors.*/
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CGM.SC_DC[0].R = SPC5_CGM_SC_DC0;
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CGM.SC_DC[1].R = SPC5_CGM_SC_DC1;
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CGM.SC_DC[2].R = SPC5_CGM_SC_DC2;
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/* Initialization of the FMPLLs settings.*/
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CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
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((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
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@ -283,6 +283,30 @@
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#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
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#endif
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/**
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* @brief Peripherals Set 1 clock divider value.
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* @note Zero means disabled clock.
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*/
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#if !defined(SPC5_PHERIPERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
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#define SPC5_PHERIPERAL1_CLK_DIV_VALUE 2
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#endif
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/**
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* @brief Peripherals Set 2 clock divider value.
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* @note Zero means disabled clock.
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*/
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#if !defined(SPC5_PHERIPERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
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#define SPC5_PHERIPERAL2_CLK_DIV_VALUE 2
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#endif
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/**
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* @brief Peripherals Set 3 clock divider value.
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* @note Zero means disabled clock.
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*/
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#if !defined(SPC5_PHERIPERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
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#define SPC5_PHERIPERAL3_CLK_DIV_VALUE 2
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#endif
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/**
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* @brief Active run modes in ME_ME register.
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* @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
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@ -678,6 +702,36 @@
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#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
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#endif
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/* Check on the peripherals set 1 clock divider settings.*/
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#if SPC5_PHERIPERAL1_CLK_DIV_VALUE == 0
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#define SPC5_CGM_SC_DC0 0
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#elif (SPC5_PHERIPERAL1_CLK_DIV_VALUE >= 1) && \
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(SPC5_PHERIPERAL1_CLK_DIV_VALUE <= 16)
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#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PHERIPERAL1_CLK_DIV_VALUE - 1))
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#else
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#error "invalid SPC5_PHERIPERAL1_CLK_DIV_VALUE value specified"
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#endif
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/* Check on the peripherals set 2 clock divider settings.*/
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#if SPC5_PHERIPERAL2_CLK_DIV_VALUE == 0
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#define SPC5_CGM_SC_DC1 0
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#elif (SPC5_PHERIPERAL2_CLK_DIV_VALUE >= 1) && \
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(SPC5_PHERIPERAL2_CLK_DIV_VALUE <= 16)
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#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PHERIPERAL2_CLK_DIV_VALUE - 1))
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#else
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#error "invalid SPC5_PHERIPERAL2_CLK_DIV_VALUE value specified"
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#endif
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/* Check on the peripherals set 3 clock divider settings.*/
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#if SPC5_PHERIPERAL3_CLK_DIV_VALUE == 0
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#define SPC5_CGM_SC_DC2 0
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#elif (SPC5_PHERIPERAL3_CLK_DIV_VALUE >= 1) && \
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(SPC5_PHERIPERAL3_CLK_DIV_VALUE <= 16)
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#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PHERIPERAL3_CLK_DIV_VALUE - 1))
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#else
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#error "invalid SPC5_PHERIPERAL3_CLK_DIV_VALUE value specified"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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@ -40,6 +40,8 @@
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#define SPC5_LINFLEX0_RXI_NUMBER 79
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#define SPC5_LINFLEX0_TXI_NUMBER 80
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#define SPC5_LINFLEX0_ERR_NUMBER 81
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#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \
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SPC5_PHERIPERAL1_CLK_DIV_VALUE)
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#define SPC5_HAS_LINFLEX1 TRUE
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#define SPC5_LINFLEX1_PCTL 49
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@ -49,6 +51,8 @@
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#define SPC5_LINFLEX1_RXI_NUMBER 99
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#define SPC5_LINFLEX1_TXI_NUMBER 100
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#define SPC5_LINFLEX1_ERR_NUMBER 101
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#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \
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SPC5_PHERIPERAL1_CLK_DIV_VALUE)
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#define SPC5_HAS_LINFLEX2 TRUE
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#define SPC5_LINFLEX2_PCTL 50
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