From 9bbb4ac554e3a32d5d9ffad9b4901e2e8ddb99ed Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 29 Apr 2013 09:17:13 +0000 Subject: [PATCH] Added wait states to the RAM accesses as specified on the DS. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5643 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/reports/SPC564A64-150.txt | 26 +++++++++++++------------- os/hal/platforms/SPC564Axx/hal_lld.c | 13 +++++++------ os/hal/platforms/SPC564Axx/hal_lld.h | 9 +++++++++ os/ports/GCC/PPC/SPC564Axx/core.s | 2 +- 4 files changed, 30 insertions(+), 20 deletions(-) diff --git a/docs/reports/SPC564A64-150.txt b/docs/reports/SPC564A64-150.txt index c84a520ad..ad2d80d84 100644 --- a/docs/reports/SPC564A64-150.txt +++ b/docs/reports/SPC564A64-150.txt @@ -6,7 +6,7 @@ Settings: SYSCLK=150 *** ChibiOS/RT test suite *** *** Kernel: 2.5.2unstable -*** Compiled: Apr 29 2013 - 10:23:56 +*** Compiled: Apr 29 2013 - 11:08:09 *** Compiler: GCC 4.6.3 build on 2013-01-07 *** Architecture: Power Architecture *** Core Variant: e200z4 @@ -100,51 +100,51 @@ Settings: SYSCLK=150 --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.1 (Benchmark, messages #1) ---- Score : 660320 msgs/S, 1320640 ctxswc/S +--- Score : 543008 msgs/S, 1086016 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.2 (Benchmark, messages #2) ---- Score : 545062 msgs/S, 1090124 ctxswc/S +--- Score : 448711 msgs/S, 897422 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.3 (Benchmark, messages #3) ---- Score : 545061 msgs/S, 1090122 ctxswc/S +--- Score : 448712 msgs/S, 897424 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.4 (Benchmark, context switch) ---- Score : 1927888 ctxswc/S +--- Score : 1547056 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 423422 threads/S +--- Score : 358539 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 614312 threads/S +--- Score : 518581 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 168227 reschedules/S, 1009362 ctxswc/S +--- Score : 137368 reschedules/S, 824208 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 1153440 ctxswc/S +--- Score : 915500 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 1898864 bytes/S +--- Score : 1624592 bytes/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 2238006 timers/S +--- Score : 1897166 timers/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 2968164 wait+signal/S +--- Score : 2688244 wait+signal/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 2172344 lock+unlock/S +--- Score : 1855960 lock+unlock/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.13 (Benchmark, RAM footprint) diff --git a/os/hal/platforms/SPC564Axx/hal_lld.c b/os/hal/platforms/SPC564Axx/hal_lld.c index 2115116c4..c6c67ba31 100644 --- a/os/hal/platforms/SPC564Axx/hal_lld.c +++ b/os/hal/platforms/SPC564Axx/hal_lld.c @@ -53,12 +53,6 @@ void hal_lld_init(void) { uint32_t n; - /* FLASH wait states and prefetching setup.*/ - FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS; - FLASH_A.BIUCR2.R = 0; - FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS; - FLASH_B.BIUCR2.R = 0; - /* The SRAM is parked on the load/store port, for some unknown reason it is defaulted on the instructions port and this kills performance.*/ XBAR.SGPCR2.B.PARK = 1; /* RAM slave on load/store port.*/ @@ -110,6 +104,13 @@ void hal_lld_init(void) { */ void spc_clock_init(void) { + /* Setting up RAM/Flash wait states and the prefetching bits.*/ + ECSM.MUDCR.R = SPC5_RAM_WS; + FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS; + FLASH_A.BIUCR2.R = 0; + FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS; + FLASH_B.BIUCR2.R = 0; + #if !SPC5_NO_INIT /* PLL activation.*/ FMPLL.ESYNCR1.B.EMODE = 1; /* Enhanced mode on. */ diff --git a/os/hal/platforms/SPC564Axx/hal_lld.h b/os/hal/platforms/SPC564Axx/hal_lld.h index d2ee43f55..5612c3954 100644 --- a/os/hal/platforms/SPC564Axx/hal_lld.h +++ b/os/hal/platforms/SPC564Axx/hal_lld.h @@ -241,6 +241,15 @@ #define SPC5_FLASH_WS (BIUCR_APC_4 | BIUCR_RWSC_4 | BIUCR_WWSC_3) #endif +/** + * @brief RAM wait states are a function of the system clock. + */ +#if (SPC5_SYSCLK <= 98000000) || defined(__DOXYGEN__) +#define SPC5_RAM_WS 0 +#else +#define SPC5_RAM_WS 0x40000000 +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/ports/GCC/PPC/SPC564Axx/core.s b/os/ports/GCC/PPC/SPC564Axx/core.s index eb07085ae..da14e7236 100644 --- a/os/ports/GCC/PPC/SPC564Axx/core.s +++ b/os/ports/GCC/PPC/SPC564Axx/core.s @@ -111,7 +111,7 @@ */ #define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0)) #define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K) -#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE | MAS2_I) +#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE) #define TLB0_MAS3 (MAS3_RPN(0x40000000) | \ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ MAS3_UR | MAS3_SR)