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MISRA fixes on NIL. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7751 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
Giovanni Di Sirio 2015-03-10 15:53:36 +00:00
parent 69c791b542
commit 99f5f9e434
6 changed files with 207 additions and 184 deletions
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90
os/nil/include/nil.h
View File

@ -30,6 +30,10 @@
#ifndef _NIL_H_
#define _NIL_H_
/**
* @brief Type of a structure representing a thread.
* @note It is required as an early definition.
*/
typedef struct nil_thread thread_t;
#include "nilconf.h"
@ -44,7 +48,7 @@ typedef struct nil_thread thread_t;
* @name Nil RTOS identification
* @{
*/
#define _NIL_ /**< @brief Nil RTOS identification.*/
#define _NIL_
#define CH_KERNEL_VERSION "1.0.0dev"
@ -57,11 +61,11 @@ typedef struct nil_thread thread_t;
* @name Wakeup messages
* @{
*/
#define MSG_OK 0 /**< @brief Normal wakeup message. */
#define MSG_TIMEOUT -1 /**< @brief Wake-up caused by a timeout
condition. */
#define MSG_RESET -2 /**< @brief Wake-up caused by a reset
condition. */
#define MSG_OK (msg_t)0 /**< @brief OK wakeup message. */
#define MSG_TIMEOUT (msg_t)-1 /**< @brief Wake-up caused by
a timeout condition. */
#define MSG_RESET (msg_t)-2 /**< @brief Wake-up caused by
a reset condition. */
/** @} */
/**
@ -87,11 +91,12 @@ typedef struct nil_thread thread_t;
* @name Thread state related macros
* @{
*/
#define NIL_STATE_READY 0 /**< @brief Thread ready or executing. */
#define NIL_STATE_SLEEPING 1 /**< @brief Thread sleeping. */
#define NIL_STATE_SUSP 2 /**< @brief Thread suspended. */
#define NIL_STATE_WTSEM 3 /**< @brief Thread waiting on semaphore.*/
#define NIL_STATE_WTOREVT 4 /**< @brief Thread waiting for events. */
#define NIL_STATE_READY (tstate_t)0 /**< @brief Thread ready or
executing. */
#define NIL_STATE_SLEEPING (tstate_t)1 /**< @brief Thread sleeping. */
#define NIL_STATE_SUSP (tstate_t)2 /**< @brief Thread suspended. */
#define NIL_STATE_WTSEM (tstate_t)3 /**< @brief On semaphore. */
#define NIL_STATE_WTOREVT (tstate_t)4 /**< @brief Waiting for events. */
#define NIL_THD_IS_READY(tr) ((tr)->state == NIL_STATE_READY)
#define NIL_THD_IS_SLEEPING(tr) ((tr)->state == NIL_STATE_SLEEPING)
#define NIL_THD_IS_SUSP(tr) ((tr)->state == NIL_STATE_SUSP)
@ -256,7 +261,7 @@ typedef struct nil_thread thread_t;
"be zero or greater than one"
#endif
#if NIL_CFG_ENABLE_ASSERTS || NIL_CFG_ENABLE_STACK_CHECK
#if (NIL_CFG_ENABLE_ASSERTS == TRUE) || (NIL_CFG_ENABLE_STACK_CHECK == TRUE)
#define NIL_DBG_ENABLED TRUE
#else
#define NIL_DBG_ENABLED FALSE
@ -264,7 +269,7 @@ typedef struct nil_thread thread_t;
/** Boundaries of the idle thread boundaries, only required if stack checking
is enabled.*/
#if NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
#if (NIL_CFG_ENABLE_STACK_CHECK == TRUE) || defined(__DOXYGEN__)
extern stkalign_t __main_thread_stack_base__, __main_thread_stack_end__;
#define THD_IDLE_BASE (&__main_thread_stack_base__)
@ -298,7 +303,7 @@ struct nil_semaphore {
/**
* @brief Thread function.
*/
typedef void (*tfunc_t)(void *);
typedef void (*tfunc_t)(void *p);
/**
* @brief Type of a structure representing a thread static configuration.
@ -316,11 +321,6 @@ struct nil_thread_cfg {
void *arg; /**< @brief Thread function argument. */
};
/**
* @brief Type of a structure representing a thread.
*/
typedef struct nil_thread thread_t;
/**
* @brief Type of a thread reference.
*/
@ -339,16 +339,16 @@ struct nil_thread {
void *p; /**< @brief Generic pointer. */
thread_reference_t *trp; /**< @brief Pointer to thread reference. */
semaphore_t *semp; /**< @brief Pointer to semaphore. */
#if NIL_CFG_USE_EVENTS || defined(__DOXYGEN__)
#if (NIL_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__)
eventmask_t ewmask; /**< @brief Enabled events mask. */
#endif
} u1;
volatile systime_t timeout;/**< @brief Timeout counter, zero
if disabled. */
#if NIL_CFG_USE_EVENTS || defined(__DOXYGEN__)
#if (NIL_CFG_USE_EVENTS == TRUE) || defined(__DOXYGEN__)
eventmask_t epmask; /**< @brief Pending events mask. */
#endif
#if NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
#if (NIL_CFG_ENABLE_STACK_CHECK == TRUE) || defined(__DOXYGEN__)
stkalign_t *stklim;/**< @brief Thread stack boundary. */
#endif
/* Optional extra fields.*/
@ -376,13 +376,13 @@ struct nil_system {
* or to an higher priority thread if a switch is required.
*/
thread_t *next;
#if NIL_CFG_ST_TIMEDELTA == 0 || defined(__DOXYGEN__)
#if (NIL_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__)
/**
* @brief System time.
*/
systime_t systime;
#endif
#if NIL_CFG_ST_TIMEDELTA > 0 || defined(__DOXYGEN__)
#if (NIL_CFG_ST_TIMEDELTA > 0) || defined(__DOXYGEN__)
/**
* @brief System time of the last tick event.
*/
@ -396,7 +396,7 @@ struct nil_system {
* @brief Thread structures for all the defined threads.
*/
thread_t threads[NIL_CFG_NUM_THREADS + 1];
#if NIL_DBG_ENABLED || defined(__DOXYGEN__)
#if (NIL_DBG_ENABLED == TRUE) || defined(__DOXYGEN__)
/**
* @brief Panic message.
* @note This field is only present if some debug options have been
@ -433,7 +433,7 @@ struct nil_system {
* @brief End of user threads table.
*/
#define THD_TABLE_END \
{THD_IDLE_BASE, THD_IDLE_END, "idle", 0, NULL} \
{THD_IDLE_BASE, THD_IDLE_END, "idle", NULL, NULL} \
};
/** @} */
@ -450,7 +450,7 @@ struct nil_system {
* @api
*/
#define THD_ALIGN_STACK_SIZE(n) \
((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
((((n) - 1U) | (sizeof(stkalign_t) - 1U)) + 1U)
/**
* @brief Calculates the total Working Area size.
@ -547,7 +547,7 @@ struct nil_system {
* @api
*/
#define S2ST(sec) \
((systime_t)((sec) * NIL_CFG_ST_FREQUENCY))
((systime_t)((uint32_t)(sec) * (uint32_t)NIL_CFG_ST_FREQUENCY))
/**
* @brief Milliseconds to system ticks.
@ -560,8 +560,8 @@ struct nil_system {
* @api
*/
#define MS2ST(msec) \
((systime_t)(((((uint32_t)(msec)) * \
((uint32_t)NIL_CFG_ST_FREQUENCY) - 1UL) / 1000UL) + 1UL))
((systime_t)((((((uint32_t)(msec)) * \
((uint32_t)NIL_CFG_ST_FREQUENCY)) - 1UL) / 1000UL) + 1UL))
/**
* @brief Microseconds to system ticks.
@ -574,8 +574,8 @@ struct nil_system {
* @api
*/
#define US2ST(usec) \
((systime_t)(((((uint32_t)(usec)) * \
((uint32_t)NIL_CFG_ST_FREQUENCY) - 1UL) / 1000000UL) + 1UL))
((systime_t)((((((uint32_t)(usec)) * \
((uint32_t)NIL_CFG_ST_FREQUENCY)) - 1UL) / 1000000UL) + 1UL))
/** @} */
/**
@ -708,12 +708,13 @@ struct nil_system {
* @brief Suspends the invoking thread until the system time arrives to the
* specified value.
*
* @param[in] time absolute system time
* @param[in] abstime absolute system time
*
* @sclass
*/
#define chThdSleepUntilS(time) \
chSchGoSleepTimeoutS(NIL_STATE_SLEEPING, (time) - chVTGetSystemTimeX())
#define chThdSleepUntilS(abstime) \
(void) chSchGoSleepTimeoutS(NIL_STATE_SLEEPING, (abstime) - \
chVTGetSystemTimeX())
/**
* @brief Initializes a semaphore with the specified counter value.
@ -774,7 +775,7 @@ struct nil_system {
*
* @xclass
*/
#if NIL_CFG_ST_TIMEDELTA == 0 || defined(__DOXYGEN__)
#if (NIL_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__)
#define chVTGetSystemTimeX() (nil.systime)
#else
#define chVTGetSystemTimeX() port_timer_get_time()
@ -824,9 +825,14 @@ struct nil_system {
*/
#if !defined(chDbgAssert)
#define chDbgAssert(c, r) do { \
if (NIL_CFG_ENABLE_ASSERTS && !(c)) \
/*lint -save -e506 -e774 [2.1, 14.3] Can be a constant by design.*/ \
if (NIL_CFG_ENABLE_ASSERTS != FALSE) { \
if (!(c)) { \
/*lint -restore*/ \
chSysHalt(__func__); \
} while (0)
} \
} \
} while (false)
#endif /* !defined(chDbgAssert) */
/** @} */
@ -854,10 +860,10 @@ extern "C" {
msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t timeout);
msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout);
void chThdResumeI(thread_reference_t *trp, msg_t msg);
void chThdSleep(systime_t time);
void chThdSleepUntil(systime_t time);
msg_t chSemWaitTimeout(semaphore_t *sp, systime_t time);
msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t time);
void chThdSleep(systime_t timeout);
void chThdSleepUntil(systime_t abstime);
msg_t chSemWaitTimeout(semaphore_t *sp, systime_t timeout);
msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t timeout);
void chSemSignal(semaphore_t *sp);
void chSemSignalI(semaphore_t *sp);
void chSemReset(semaphore_t *sp, cnt_t n);

2
os/nil/ports/ARMCMx/compilers/GCC/niltypes.h
View File

@ -46,7 +46,7 @@
* @brief Generic 'true' boolean constant.
*/
#if !defined(TRUE) || defined(__DOXYGEN__)
#define TRUE (!FALSE)
#define TRUE 1
#endif
/** @} */

14
os/nil/ports/ARMCMx/nilcore.h
View File

@ -155,7 +155,7 @@ struct port_extctx {};
/**
* @brief System saved context.
* @details This structure represents the inner stack frame during a context
* switching.
* switch.
*/
struct port_intctx {};
#endif /* defined(__DOXYGEN__) */
@ -169,7 +169,7 @@ struct port_intctx {};
/**
* @brief Total priority levels.
*/
#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
#define CORTEX_PRIORITY_LEVELS (1U << CORTEX_PRIORITY_BITS)
/**
* @brief Minimum priority level.
@ -182,7 +182,7 @@ struct port_intctx {};
* @brief Maximum priority level.
* @details The maximum allowed priority level is always zero.
*/
#define CORTEX_MAXIMUM_PRIORITY 0
#define CORTEX_MAXIMUM_PRIORITY 0U
/**
* @brief Priority level verification macro.
@ -200,7 +200,7 @@ struct port_intctx {};
* @brief Priority level to priority mask conversion macro.
*/
#define CORTEX_PRIO_MASK(n) \
((n) << (8 - CORTEX_PRIORITY_BITS))
((n) << (8U - (unsigned)CORTEX_PRIORITY_BITS))
/*===========================================================================*/
/* External declarations. */
@ -221,11 +221,11 @@ struct port_intctx {};
#if !defined(_FROM_ASM_)
#if NIL_CFG_ST_TIMEDELTA > 0
#if !PORT_USE_ALT_TIMER
#if PORT_USE_ALT_TIMER == FALSE
#include "nilcore_timer.h"
#else /* PORT_USE_ALT_TIMER */
#else /* PORT_USE_ALT_TIMER != FALSE */
#include "nilcore_timer_alt.h"
#endif /* PORT_USE_ALT_TIMER */
#endif /* PORT_USE_ALT_TIMER != FALSE */
#endif /* NIL_CFG_ST_TIMEDELTA > 0 */
#endif /* !defined(_FROM_ASM_) */

20
os/nil/ports/ARMCMx/nilcore_v7m.c
View File

@ -51,17 +51,19 @@
/* Module interrupt handlers. */
/*===========================================================================*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
/**
* @brief SVC vector.
* @details The SVC vector is used for exception mode re-entering after a
* context switch.
* @note The PendSV vector is only used in advanced kernel mode.
*/
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
void SVC_Handler(void) {
/*lint -restore*/
struct port_extctx *ctxp;
#if CORTEX_USE_FPU
#if CORTEX_USE_FPU == TRUE
/* Enforcing unstacking of the FP part of the context.*/
SCB_FPCCR &= ~FPCCR_LSPACT;
#endif
@ -79,19 +81,21 @@ void SVC_Handler(void) {
/* Restoring the normal interrupts status.*/
port_unlock_from_isr();
}
#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
#endif /* CORTEX_SIMPLIFIED_PRIORITY == FALSE */
#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#if (CORTEX_SIMPLIFIED_PRIORITY == TRUE) || defined(__DOXYGEN__)
/**
* @brief PendSV vector.
* @details The PendSV vector is used for exception mode re-entering after a
* context switch.
* @note The PendSV vector is only used in compact kernel mode.
*/
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
void PendSV_Handler(void) {
/*lint -restore*/
struct port_extctx *ctxp;
#if CORTEX_USE_FPU
#if CORTEX_USE_FPU == TRUE
/* Enforcing unstacking of the FP part of the context.*/
SCB_FPCCR &= ~FPCCR_LSPACT;
#endif
@ -106,7 +110,7 @@ void PendSV_Handler(void) {
/* Writing back the modified PSP value.*/
__set_PSP((uint32_t)ctxp);
}
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
#endif /* CORTEX_SIMPLIFIED_PRIORITY == TRUE */
/*===========================================================================*/
/* Module exported functions. */
@ -118,10 +122,10 @@ void PendSV_Handler(void) {
void _port_irq_epilogue(void) {
port_lock_from_isr();
if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0) {
if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0U) {
struct port_extctx *ctxp;
#if CORTEX_USE_FPU
#if CORTEX_USE_FPU == TRUE
/* Enforcing a lazy FPU state save by accessing the FPCSR register.*/
(void) __get_FPSCR();
#endif

143
os/nil/ports/ARMCMx/nilcore_v7m.h
View File

@ -25,53 +25,13 @@
* @{
*/
#ifndef _CHCORE_V7M_H_
#define _CHCORE_V7M_H_
#ifndef _NILCORE_V7M_H_
#define _NILCORE_V7M_H_
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
/**
* @name Architecture and Compiler
* @{
*/
#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
/**
* @brief Macro defining the specific ARM architecture.
*/
#define PORT_ARCHITECTURE_ARM_v7M
/**
* @brief Name of the implemented architecture.
*/
#define PORT_ARCHITECTURE_NAME "ARMv7-M"
/**
* @brief Name of the architecture variant.
*/
#define PORT_CORE_VARIANT_NAME "Cortex-M3"
#elif (CORTEX_MODEL == CORTEX_M4)
#define PORT_ARCHITECTURE_ARM_v7ME
#define PORT_ARCHITECTURE_NAME "ARMv7-ME"
#if CORTEX_USE_FPU
#define PORT_CORE_VARIANT_NAME "Cortex-M4F"
#else
#define PORT_CORE_VARIANT_NAME "Cortex-M4"
#endif
#endif
/**
* @brief Port-specific information string.
*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define PORT_INFO "Advanced kernel mode"
#else
#define PORT_INFO "Compact kernel mode"
#endif
/** @} */
/**
* @brief This port supports a realtime counter.
*/
@ -80,7 +40,7 @@
/**
* @brief Disabled value for BASEPRI register.
*/
#define CORTEX_BASEPRI_DISABLED 0
#define CORTEX_BASEPRI_DISABLED 0U
/*===========================================================================*/
/* Module pre-compile time settings. */
@ -125,7 +85,7 @@
*/
#if !defined(CORTEX_USE_FPU)
#define CORTEX_USE_FPU CORTEX_HAS_FPU
#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
#elif (CORTEX_USE_FPU == TRUE) && (CORTEX_HAS_FPU == FALSE)
/* This setting requires an FPU presence check in case it is externally
redefined.*/
#error "the selected core does not have an FPU"
@ -149,7 +109,7 @@
* priority level.
*/
#if !defined(CORTEX_PRIORITY_SVCALL)
#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1U)
#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
/* If it is externally redefined then better perform a validity check on it.*/
#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
@ -159,7 +119,7 @@
* @brief NVIC VTOR initialization expression.
*/
#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
#define CORTEX_VTOR_INIT 0x00000000
#define CORTEX_VTOR_INIT 0x00000000U
#endif
/**
@ -175,11 +135,51 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
/**
* @name Architecture and Compiler
* @{
*/
#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
/**
* @brief Macro defining the specific ARM architecture.
*/
#define PORT_ARCHITECTURE_ARM_v7M
/**
* @brief Name of the implemented architecture.
*/
#define PORT_ARCHITECTURE_NAME "ARMv7-M"
/**
* @brief Name of the architecture variant.
*/
#define PORT_CORE_VARIANT_NAME "Cortex-M3"
#elif (CORTEX_MODEL == CORTEX_M4)
#define PORT_ARCHITECTURE_ARM_v7ME
#define PORT_ARCHITECTURE_NAME "ARMv7-ME"
#if CORTEX_USE_FPU
#define PORT_CORE_VARIANT_NAME "Cortex-M4F"
#else
#define PORT_CORE_VARIANT_NAME "Cortex-M4"
#endif
#endif
/**
* @brief Port-specific information string.
*/
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
#define PORT_INFO "Advanced kernel mode"
#else
#define PORT_INFO "Compact kernel mode"
#endif
/** @} */
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
/**
* @brief Maximum usable priority for normal ISRs.
*/
#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1U)
/**
* @brief BASEPRI level within kernel lock.
@ -188,7 +188,7 @@
CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
#else
#define CORTEX_MAX_KERNEL_PRIORITY 0
#define CORTEX_MAX_KERNEL_PRIORITY 0U
#endif
/**
@ -277,16 +277,18 @@ struct port_intctx {
/*===========================================================================*/
/**
* @brief Platform dependent thread stack setup.
* @brief Platform dependent part of the @p chThdCreateI() API.
* @details This code usually setup the context switching frame represented
* by an @p port_intctx structure.
*/
#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) { \
(tp)->ctxp = (struct port_intctx *)(((uint8_t *)(wend)) - \
/*lint -save -e611 -e9074 -e9087 [11.1, 11.3] Casts are planned here.*/ \
(tp)->ctxp = (struct port_intctx *)((uint8_t *)(wend) - \
sizeof(struct port_intctx)); \
(tp)->ctxp->r4 = (regarm_t)(pf); \
(tp)->ctxp->r5 = (regarm_t)(arg); \
(tp)->ctxp->lr = (regarm_t)(_port_thread_start); \
/*lint -restore*/ \
}
/**
@ -295,7 +297,7 @@ struct port_intctx {
*/
#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \
sizeof(struct port_extctx) + \
(n) + (PORT_INT_REQUIRED_STACK))
((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK)))
/**
* @brief IRQ prologue code.
@ -335,13 +337,14 @@ struct port_intctx {
* @param[in] ntp the thread to be switched in
* @param[in] otp the thread to be switched out
*/
#if !NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
#if (NIL_CFG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__)
#define port_switch(ntp, otp) _port_switch(ntp, otp)
#else
#define port_switch(ntp, otp) { \
struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \
if ((stkalign_t *)(r13 - 1) < (otp)->stklim) \
if ((stkalign_t *)(r13 - 1) < (otp)->stklim) { \
chSysHalt("stack overflow"); \
} \
_port_switch(ntp, otp); \
}
#endif
@ -382,7 +385,7 @@ static inline void port_init(void) {
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
/* Initialization of the system vectors used by the port.*/
#if !CORTEX_SIMPLIFIED_PRIORITY
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL);
#endif
NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
@ -394,12 +397,12 @@ static inline void port_init(void) {
* @return The interrupts status.
*/
static inline syssts_t port_get_irq_status(void) {
register uint32_t sts;
syssts_t sts;
#if !CORTEX_SIMPLIFIED_PRIORITY
sts = __get_BASEPRI();
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
sts = (syssts_t)__get_BASEPRI();
#else /* CORTEX_SIMPLIFIED_PRIORITY */
sts = __get_PRIMASK();
sts = (syssts_t)__get_PRIMASK();
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
return sts;
}
@ -415,10 +418,10 @@ static inline syssts_t port_get_irq_status(void) {
*/
static inline bool port_irq_enabled(syssts_t sts) {
#if !CORTEX_SIMPLIFIED_PRIORITY
return sts == CORTEX_BASEPRI_DISABLED;
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
return sts == (syssts_t)CORTEX_BASEPRI_DISABLED;
#else /* CORTEX_SIMPLIFIED_PRIORITY */
return (sts & 1) == 0;
return (sts & (syssts_t)1) == (syssts_t)0;
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
}
@ -431,7 +434,7 @@ static inline bool port_irq_enabled(syssts_t sts) {
*/
static inline bool port_is_isr_context(void) {
return (bool)((__get_IPSR() & 0x1FF) != 0);
return (bool)((__get_IPSR() & 0x1FFU) != 0U);
}
/**
@ -441,7 +444,7 @@ static inline bool port_is_isr_context(void) {
*/
static inline void port_lock(void) {
#if !CORTEX_SIMPLIFIED_PRIORITY
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
#else /* CORTEX_SIMPLIFIED_PRIORITY */
__disable_irq();
@ -455,7 +458,7 @@ static inline void port_lock(void) {
*/
static inline void port_unlock(void) {
#if !CORTEX_SIMPLIFIED_PRIORITY
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
#else /* CORTEX_SIMPLIFIED_PRIORITY */
__enable_irq();
@ -501,7 +504,7 @@ static inline void port_disable(void) {
*/
static inline void port_suspend(void) {
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
__enable_irq();
#else
@ -515,7 +518,7 @@ static inline void port_suspend(void) {
*/
static inline void port_enable(void) {
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
#endif
__enable_irq();
@ -531,8 +534,8 @@ static inline void port_enable(void) {
*/
static inline void port_wait_for_interrupt(void) {
#if CORTEX_ENABLE_WFI_IDLE
__WFI;
#if CORTEX_ENABLE_WFI_IDLE == TRUE
__WFI();
#endif
}
@ -548,6 +551,6 @@ static inline rtcnt_t port_rt_get_counter_value(void) {
#endif /* !defined(_FROM_ASM_) */
#endif /* _CHCORE_V7M_H_ */
#endif /* _NILCORE_V7M_H_ */
/** @} */

120
os/nil/src/nil.c
View File

@ -91,7 +91,8 @@ void chSysInit(void) {
/* Initialization hook.*/
NIL_CFG_THREAD_EXT_INIT_HOOK(tp);
tp++, tcp++;
tp++;
tcp++;
}
#if NIL_CFG_ENABLE_STACK_CHECK
@ -134,8 +135,8 @@ void chSysHalt(const char *reason) {
NIL_CFG_SYSTEM_HALT_HOOK(reason);
/* Harmless infinite loop.*/
while (true)
;
while (true) {
}
}
/**
@ -152,19 +153,23 @@ void chSysTimerHandlerI(void) {
nil.systime++;
do {
/* Is the thread in a wait state with timeout?.*/
if (tp->timeout > 0) {
if (tp->timeout > (systime_t)0) {
chDbgAssert(!NIL_THD_IS_READY(tp), "is ready");
/* Did the timer reach zero?*/
if (--tp->timeout == 0) {
if (--tp->timeout == (systime_t)0) {
/* Timeout on semaphores requires a special handling because the
semaphore counter must be incremented.*/
if (NIL_THD_IS_WTSEM(tp))
/*lint -save -e9013 [15.7] There is no else because it is not needed.*/
if (NIL_THD_IS_WTSEM(tp)) {
tp->u1.semp->cnt++;
else if (NIL_THD_IS_SUSP(tp))
}
else if (NIL_THD_IS_SUSP(tp)) {
*tp->u1.trp = NULL;
chSchReadyI(tp, MSG_TIMEOUT);
}
/*lint -restore*/
(void) chSchReadyI(tp, MSG_TIMEOUT);
}
}
/* Lock released in order to give a preemption chance on those
@ -175,32 +180,37 @@ void chSysTimerHandlerI(void) {
} while (tp < &nil.threads[NIL_CFG_NUM_THREADS]);
#else
thread_t *tp = &nil.threads[0];
systime_t next = 0;
systime_t next = (systime_t)0;
chDbgAssert(nil.nexttime == port_timer_get_alarm(), "time mismatch");
do {
/* Is the thread in a wait state with timeout?.*/
if (tp->timeout > 0) {
if (tp->timeout > (systime_t)0) {
chDbgAssert(!NIL_THD_IS_READY(tp), "is ready");
chDbgAssert(tp->timeout >= nil.nexttime - nil.lasttime, "skipped one");
tp->timeout -= nil.nexttime - nil.lasttime;
if (tp->timeout == 0) {
if (tp->timeout == (systime_t)0) {
/* Timeout on semaphores requires a special handling because the
semaphore counter must be incremented.*/
if (NIL_THD_IS_WTSEM(tp))
/*lint -save -e9013 [15.7] There is no else because it is not needed.*/
if (NIL_THD_IS_WTSEM(tp)) {
tp->u1.semp->cnt++;
else if (NIL_THD_IS_SUSP(tp))
}
else if (NIL_THD_IS_SUSP(tp)) {
*tp->u1.trp = NULL;
chSchReadyI(tp, MSG_TIMEOUT);
}
/*lint -restore*/
(void) chSchReadyI(tp, MSG_TIMEOUT);
}
else {
if (tp->timeout <= (systime_t)(next - 1))
if (tp->timeout <= (systime_t)(next - (systime_t)1)) {
next = tp->timeout;
}
}
}
/* Lock released in order to give a preemption chance on those
architectures supporting IRQ preemption.*/
chSysUnlockFromISR();
@ -208,7 +218,7 @@ void chSysTimerHandlerI(void) {
chSysLockFromISR();
} while (tp < &nil.threads[NIL_CFG_NUM_THREADS]);
nil.lasttime = nil.nexttime;
if (next > 0) {
if (next > (systime_t)0) {
nil.nexttime += next;
port_timer_set_alarm(nil.nexttime);
}
@ -228,9 +238,10 @@ void chSysTimerHandlerI(void) {
*/
void chSysUnconditionalLock(void) {
if (port_irq_enabled(port_get_irq_status()))
if (port_irq_enabled(port_get_irq_status())) {
chSysLock();
}
}
/**
* @brief Unconditionally leaves the kernel lock state.
@ -241,9 +252,10 @@ void chSysUnconditionalLock(void) {
*/
void chSysUnconditionalUnlock(void) {
if (!port_irq_enabled(port_get_irq_status()))
if (!port_irq_enabled(port_get_irq_status())) {
chSysUnlock();
}
}
/**
* @brief Returns the execution status and enters a critical zone.
@ -262,11 +274,13 @@ syssts_t chSysGetStatusAndLockX(void) {
syssts_t sts = port_get_irq_status();
if (port_irq_enabled(sts)) {
if (port_is_isr_context())
if (port_is_isr_context()) {
chSysLockFromISR();
else
}
else {
chSysLock();
}
}
return sts;
}
@ -282,8 +296,9 @@ syssts_t chSysGetStatusAndLockX(void) {
void chSysRestoreStatusX(syssts_t sts) {
if (port_irq_enabled(sts)) {
if (port_is_isr_context())
if (port_is_isr_context()) {
chSysUnlockFromISR();
}
else {
chSchRescheduleS();
chSysUnlock();
@ -309,9 +324,10 @@ thread_t *chSchReadyI(thread_t *tp, msg_t msg) {
tp->u1.msg = msg;
tp->state = NIL_STATE_READY;
tp->timeout = 0;
if (tp < nil.next)
tp->timeout = (systime_t)0;
if (tp < nil.next) {
nil.next = tp;
}
return tp;
}
@ -455,23 +471,21 @@ void chThdResumeI(thread_reference_t *trp, msg_t msg) {
chDbgAssert(NIL_THD_IS_SUSP(tr), "not suspended");
*trp = NULL;
chSchReadyI(tr, msg);
(void) chSchReadyI(tr, msg);
}
}
/**
* @brief Suspends the invoking thread for the specified time.
*
* @param[in] time the delay in system ticks
* @param[in] timeout the delay in system ticks
*
* @api
*/
void chThdSleep(systime_t time) {
void chThdSleep(systime_t timeout) {
chSysLock();
chThdSleepS(time);
(void) chThdSleepS(timeout);
chSysUnlock();
}
@ -479,16 +493,14 @@ void chThdSleep(systime_t time) {
* @brief Suspends the invoking thread until the system time arrives to the
* specified value.
*
* @param[in] time absolute system time
* @param[in] abstime absolute system time
*
* @api
*/
void chThdSleepUntil(systime_t time) {
void chThdSleepUntil(systime_t abstime) {
chSysLock();
chThdSleepUntilS(time);
chThdSleepUntilS(abstime);
chSysUnlock();
}
@ -515,10 +527,9 @@ msg_t chSemWaitTimeout(semaphore_t *sp, systime_t timeout) {
msg_t msg;
chSysLock();
msg = chSemWaitTimeoutS(sp, timeout);
chSysUnlock();
return msg;
}
@ -546,14 +557,15 @@ msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t timeout) {
/* Note, the semaphore counter is a volatile variable so accesses are
manually optimized.*/
cnt_t cnt = sp->cnt;
if (cnt <= 0) {
if (TIME_IMMEDIATE == timeout)
if (cnt <= (cnt_t)0) {
if (TIME_IMMEDIATE == timeout) {
return MSG_TIMEOUT;
sp->cnt = cnt - 1;
}
sp->cnt = cnt - (cnt_t)1;
nil.current->u1.semp = sp;
return chSchGoSleepTimeoutS(NIL_STATE_WTSEM, timeout);
}
sp->cnt = cnt - 1;
sp->cnt = cnt - (cnt_t)1;
return MSG_OK;
}
@ -571,10 +583,8 @@ msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t timeout) {
void chSemSignal(semaphore_t *sp) {
chSysLock();
chSemSignalI(sp);
chSchRescheduleS();
chSysUnlock();
}
@ -591,7 +601,7 @@ void chSemSignal(semaphore_t *sp) {
*/
void chSemSignalI(semaphore_t *sp) {
if (++sp->cnt <= 0) {
if (++sp->cnt <= (cnt_t)0) {
thread_reference_t tr = nil.threads;
while (true) {
/* Is this thread waiting on this semaphore?*/
@ -599,7 +609,7 @@ void chSemSignalI(semaphore_t *sp) {
chDbgAssert(NIL_THD_IS_WTSEM(tr), "not waiting");
chSchReadyI(tr, MSG_OK);
(void) chSchReadyI(tr, MSG_OK);
return;
}
tr++;
@ -629,10 +639,8 @@ void chSemSignalI(semaphore_t *sp) {
void chSemReset(semaphore_t *sp, cnt_t n) {
chSysLock();
chSemResetI(sp, n);
chSchRescheduleS();
chSysUnlock();
}
@ -659,14 +667,14 @@ void chSemResetI(semaphore_t *sp, cnt_t n) {
cnt = sp->cnt;
sp->cnt = n;
tp = nil.threads;
while (cnt < 0) {
while (cnt < (cnt_t)0) {
/* Is this thread waiting on this semaphore?*/
if (tp->u1.semp == sp) {
chDbgAssert(NIL_THD_IS_WTSEM(tp), "not waiting");
cnt++;
chSchReadyI(tp, MSG_RESET);
(void) chSchReadyI(tp, MSG_RESET);
}
tp++;
@ -686,10 +694,8 @@ void chSemResetI(semaphore_t *sp, cnt_t n) {
void chEvtSignal(thread_t *tp, eventmask_t mask) {
chSysLock();
chEvtSignalI(tp, mask);
chSchRescheduleS();
chSysUnlock();
}
@ -708,8 +714,10 @@ void chEvtSignal(thread_t *tp, eventmask_t mask) {
void chEvtSignalI(thread_t *tp, eventmask_t mask) {
tp->epmask |= mask;
if (NIL_THD_IS_WTOREVT(tp) && ((tp->epmask & tp->u1.ewmask) != 0))
chSchReadyI(tp, MSG_OK);
if (NIL_THD_IS_WTOREVT(tp) &&
((tp->epmask & tp->u1.ewmask) != (eventmask_t)0)) {
(void) chSchReadyI(tp, MSG_OK);
}
}
/**
@ -734,10 +742,9 @@ eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t timeout) {
eventmask_t m;
chSysLock();
m = chEvtWaitAnyTimeoutS(mask, timeout);
chSysUnlock();
return m;
}
@ -763,19 +770,22 @@ eventmask_t chEvtWaitAnyTimeoutS(eventmask_t mask, systime_t timeout) {
thread_t *ctp = nil.current;
eventmask_t m;
if ((m = (ctp->epmask & mask)) == 0) {
if ((m = (ctp->epmask & mask)) == (eventmask_t)0) {
if (TIME_IMMEDIATE == timeout) {
chSysUnlock();
return (eventmask_t)0;
}
ctp->u1.ewmask = mask;
if (chSchGoSleepTimeoutS(NIL_STATE_WTOREVT, timeout) < MSG_OK) {
chSysUnlock();
return (eventmask_t)0;
}
m = ctp->epmask & mask;
}
ctp->epmask &= ~m;
return m;
}