Add board and demos files for Nonstandard LPC4330 SBC.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6741 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
theshed 2014-03-01 21:30:20 +00:00
parent 5b02bc9fc4
commit 98da8365ea
16 changed files with 5237 additions and 0 deletions

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
LPC4330 SBC board config file - Copyright (C) 2013 Marcin Jokel
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
#if HAL_USE_PAL || defined(__DOXYGEN__)
const PALConfig pal_default_config = {
{VAL_GPIO0DATA, VAL_GPIO0DIR},
{VAL_GPIO1DATA, VAL_GPIO1DIR},
{VAL_GPIO2DATA, VAL_GPIO2DIR},
{VAL_GPIO3DATA, VAL_GPIO3DIR},
{VAL_GPIO4DATA, VAL_GPIO4DIR},
{VAL_GPIO5DATA, VAL_GPIO5DIR}
};
#endif
/*
* Board Ethernet pins configuration.
* ENET_REF_CLK pin must be set before macInit().
*/
static void board_eth_pin_config(void) {
/* Ethernet I/O config */
LPC_SCU->SFSP0_0 = (1 << 7) | (1 << 5) | (1 << 6) | (1 << 4) | 0x02; /* Set ENET RXD1 P0.0, disable pull-up resistor.*/
LPC_SCU->SFSP0_1 = (1 << 7) | (1 << 5) | (1 << 6) | (1 << 4) | 0x06; /* Set ENET TX EN P0.1, disable pull-up resistor.*/
LPC_SCU->SFSP1_15 = (1 << 7) | (1 << 5) | (1 << 6) | (1 << 4) | 0x03; /* Set ENET RXD0 P1.15, disable pull-up resistor.*/
LPC_SCU->SFSP1_16 = (1 << 7) | (1 << 5) | (1 << 6) | (1 << 4) | 0x07; /* Set ENET CRS P1.16, disable pull-up resistor.*/
LPC_SCU->SFSP1_17 = (1 << 7) | (1 << 5) | (1 << 6) | (1 << 4) | 0x03; /* Set ENET MDIO P1.17, disable pull-up resistor.*/
LPC_SCU->SFSP1_18 = (1 << 7) | (1 << 5) | (1 << 6) | (1 << 4) | 0x03; /* Set ENET TXD0 P1.18, disable pull-up resistor.*/
LPC_SCU->SFSP1_19 = (1 << 7) | (1 << 5) | (1 << 6) | (1 << 4) | 0x00; /* Set ENET REF CLK P1.19, disable pull-up resistor.*/
LPC_SCU->SFSP1_20 = (1 << 7) | (1 << 5) | (1 << 6) | (1 << 4) | 0x03; /* Set ENET TXD1 P1.20, disable pull-up resistor.*/
LPC_SCU->SFSP7_7 = (1 << 7) | (1 << 5) | (1 << 6) | (1 << 4) | 0x06; /* Set ENET MDC P7.7, disable pull-up resistor.*/
}
/*
* Early initialization code.
* This initialization must be performed just after stack setup and before
* any other initialization.
*/
void __early_init(void) {
#ifdef RESET_ON_RESTART_DEBUG
uint32_t i;
__disable_irq();
/* Reset peripherals. */
LPC_RGU->RESET_CTRL0 = 0x10DF1000;
LPC_RGU->RESET_CTRL1 = 0x01DFF7FF;
for (i = 0; i < 8; i++) {
NVIC->ICPR[i] = 0xFFFFFFFF; /* Clear pending interrupts in the NVIC. */
}
__enable_irq();
#endif
lpc_clock_init();
#if HAL_USE_MAC
board_eth_pin_config();
#endif
}
/*
* Board-specific initialization code.
*/
void boardInit(void) {
/*
* Extra, board-specific, initializations.
*/
/* UART3 I/O config */
LPC_SCU->SFSP2_3 = (1 << 4) | 0x02; /* Set UART3 TXD3 P2.3, disable pull-up resistor.*/
LPC_SCU->SFSP2_4 = (1 << 6) | (1 << 4) | 0x02; /* Set UART3 RXD3 P2.4, disable pull-up resistor.*/
/* SD card SSP1 I/O config */
LPC_SCU->SFSPF_4 = (1 << 4) | 0x00; /* Set SSP1 SCK PF.4, disable pull-up resistor.*/
LPC_SCU->SFSP1_3 = (1 << 6) | (1 << 4) | 0x05; /* Set SSP1 MISO P1.3, disable pull-up resistor.*/
LPC_SCU->SFSP1_4 = (1 << 4) | 0x05; /* Set SSP1 MOSI P1.4, disable pull-up resistor.*/
LPC_SCU->SFSP3_1 = (1 << 4) | 0x04; /* Set SSP1 CS GPIO P3.1, disable pull-up resistor.*/
/* I2C0 I/O config */
//LPC_SCU->SFSI2C0 = (1 << 11) | (1 << 3); /* Set I2C0 SDA and SCL, standard/fast mode, enable the input receiver.*/
/* I/O for switches config */
LPC_SCU->SFSP7_5 = (1 << 6) | (1 << 4); /* Set SW_1 P7.5, enable input buffer, disable pull-up resistor.*/
LPC_SCU->SFSP7_6 = (1 << 6) | (1 << 4); /* Set SW_2 P7.6, enable input buffer, disable pull-up resistor.*/
/* I2S0 I/O config */
//LPC_SCU->SFSP3_0 = (1 << 4) | 0x03; /* Set I2S0 TX MCLK P3.0, disable pull-up resistor.*/
//LPC_SCU->SFSP3_2 = (1 << 4) | 0x01; /* Set I2S0 RX SDA P3.2, disable pull-up resistor.*/
//LPC_SCU->SFSP4_7 = (1 << 4) | 0x07; /* Set I2S0 TX SCK P4.7, disable pull-up resistor.*/
//LPC_SCU->SFSP7_1 = (1 << 4) | 0x02; /* Set I2S0 TX WS P7.1, disable pull-up resistor.*/
//LPC_SCU->SFSP7_2 = (1 << 4) | 0x02; /* Set I2S0 TX SDA P7.2, disable pull-up resistor.*/
/* SDRAM I/O config */
/* Address lines */
//LPC_SCU->SFSP2_9 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC A0 P2.9, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP2_10 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC A1 P2.10, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP2_11 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC A2 P2.11, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP2_12 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC A3 P2.12, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP2_13 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC A4 P2.13, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP1_0 = (1 << 7) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC A5 P1.0, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP1_1 = (1 << 7) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC A6 P1.1, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP1_2 = (1 << 7) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC A7 P1.2, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP2_8 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC A8 P2.8, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP2_7 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC A9 P2.9, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP2_6 = (1 << 7) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC A10 P2.6, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP2_2 = (1 << 7) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC A11 P2.2, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP2_1 = (1 << 7) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC A12 P2.1, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP2_0 = (1 << 7) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC A13 P2.0, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP6_8 = (1 << 7) | (1 << 5) | (1 << 4) | 0x01; /* Set EMC A14 P2.13, disable glitch filter, fast mode, disable pull-up resistor.*/
/* Data lines */
//LPC_SCU->SFSP1_7 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC D0 P1.7, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP1_8 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC D1 P1.8, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP1_9 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC D2 P1.9, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP1_10 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC D3 P1.10, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP1_11 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC D4 P1.11, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP1_12 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC D5 P1.12, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP1_13 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC D6 P1.13, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP1_14 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC D7 P1.14, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP5_4 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC D8 P5.4, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP5_5 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC D9 P5.5, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP5_6 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC D10 P5.6, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP5_7 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC D11 P5.7, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP5_0 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC D12 P5.0, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP5_1 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC D13 P5.1, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP5_2 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC D14 P5.2, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP5_3 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x02; /* Set EMC D15 P5.3, disable glitch filter, fast mode, input buffer, disable pull-up resistor.*/
//LPC_SCU->SFSP1_6 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC WE P1.6, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSCLK_0 = (1 << 7) | (1 << 5) | (1 << 4) | 0x00; /* Set EMC CLK0, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSCLK_2 = (1 << 7) | (1 << 5) | (1 << 4) | 0x00; /* Set EMC CLK2, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->EMCDELAYCLK = 0; /* No clock delay.*/
//LPC_SCU->SFSP6_4 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC CAS P6.4, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP6_5 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC RAS P6.5, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP6_11 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC CKEOUT0 P6.11, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP6_12 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC DQMOUT0 P6.12, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP6_10 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC DQMOUT1 P6.10, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP6_9 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set EMC DYCS0 P6.9, disable glitch filter, fast mode, disable pull-up resistor.*/
/* SPIFI I/O config */
//LPC_SCU->SFSP3_3 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set SPIFI SCK P3.3, disable glitch filter, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP3_4 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set SPIFI SIO3 P3.4, disable glitch filter, input buffer, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP3_5 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set SPIFI SIO2 P3.5, disable glitch filter, input buffer, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP3_6 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set SPIFI SIO1 P3.6, disable glitch filter, input buffer, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP3_7 = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | 0x03; /* Set SPIFI SIO0 P3.7, disable glitch filter, input buffer, fast mode, disable pull-up resistor.*/
//LPC_SCU->SFSP3_8 = (1 << 7) | (1 << 5) | (1 << 4) | 0x03; /* Set SPIFI CS P3.8, disable glitch filter, fast mode, disable pull-up resistor.*/
/* DAC I/O config */
/* No need configuration. */
}

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
LPC4330 SBC board config file - Copyright (C) 2013 Marcin Jokel
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for non standard board LPC4330 SBC.
*/
/*
* Board identifiers.
*/
#define BOARD_NONSTANDARD_LPC4330_SBC
#define BOARD_NAME "LPC4330 SBC"
#define RESET_ON_RESTART_DEBUG /* Only for debug. */
/*
* Ethernet PHY type.
*/
#define MII_KSZ8031_ID 0x00221556
#define BOARD_PHY_ID MII_KSZ8031_ID
#define BOARD_PHY_RMII
/*
* Board frequencies.
*/
#define XTAL 12000000UL
#define RTC_XTAL 32768UL
#define ENET_RX_CLK 50000000UL
#define ENET_TX_CLK 50000000UL
/*
* GPIO 0 initial setup.
*/
#define VAL_GPIO0DIR 0x00000000
#define VAL_GPIO0DATA 0x00000000
/*
* GPIO 1 initial setup.
*/
#define VAL_GPIO1DIR 0x00000000
#define VAL_GPIO1DATA 0x00000000
/*
* GPIO 2 initial setup.
*/
#define VAL_GPIO2DIR PAL_PORT_BIT(GPIO2_LED)
#define VAL_GPIO2DATA PAL_PORT_BIT(GPIO2_LED)
/*
* GPIO 3 initial setup.
*/
#define VAL_GPIO3DIR 0x00000000
#define VAL_GPIO3DATA 0x00000000
/*
* GPIO 4 initial setup.
*/
#define LPC_HAS_GPIO4 TRUE
#define VAL_GPIO4DIR 0x00000000
#define VAL_GPIO4DATA 0x00000000
/*
* GPIO 5 initial setup.
*/
#define VAL_GPIO5DIR PAL_PORT_BIT(GPIO5_SD_CS)
#define VAL_GPIO5DATA PAL_PORT_BIT(GPIO5_SD_CS)
/*
* GPIO 6 initial setup.
*/
#define LPC_HAS_GPIO6 FALSE
/*
* GPIO 7 initial setup.
*/
#define LPC_HAS_GPIO7 FALSE
/*
* Pin definitions.
*/
#define GPIO2_LED 0
#define GPIO3_SW_USER1 13
#define GPIO3_SW_USER2 14
#define GPIO5_SD_CS 8
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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# List of all the board related files.
BOARDSRC = ${CHIBIOS}/boards/NONSTANDARD_LPC4330_SBC/board.c
# Required include directories
BOARDINC = ${CHIBIOS}/boards/NONSTANDARD_LPC4330_SBC

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##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Enables the use of FPU on Cortex-M4.
ifeq ($(USE_FPU),)
USE_FPU = no
endif
# Enables the use of Cortex-M4 by LPC43xx in LPC43xx.h.
ifeq ($(USE_CORE_M4),)
USE_CORE_M4 = yes
endif
# LPC43xx boot select: ram, spifi_flash_debug, flash.
ifeq ($(LPC_BOOT_SELECT),)
LPC_BOOT_SELECT = ram
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files and paths
CHIBIOS = ../..
include $(CHIBIOS)/boards/NONSTANDARD_LPC4330_SBC/board.mk
include $(CHIBIOS)/os/hal/platforms/LPC43xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC43xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk
include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/LPC4330_RAM_DEBUG.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(PORTSRC) \
$(KERNSRC) \
$(TESTSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
$(LWSRC) \
$(CHIBIOS)/os/various/evtimer.c \
web/web.c main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \
$(CHIBIOS)/os/various
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m4
#TRGT = arm-elf-
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
OD = $(TRGT)objdump
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
#
# Compiler settings
##############################################################################
##############################################################################
# Start of default section
#
# List all default C defines here, like -D_DEBUG=1
DDEFS = -D__NEWLIB__
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
ifeq ($(USE_FPU),yes)
USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
DDEFS += -DCORTEX_USE_FPU=TRUE
else
DDEFS += -DCORTEX_USE_FPU=FALSE
endif
ifeq ($(USE_CORE_M4),yes)
DDEFS += -DCORE_M4
endif
ifeq ($(LPC_BOOT_SELECT), ram)
DDEFS += -DCORTEX_VTOR_INIT=0x10000000
else
ifeq ($(LPC_BOOT_SELECT), spifi_flash_debug)
DDEFS += -DCORTEX_VTOR_INIT=0x14000000
else
DDEFS += -DCORTEX_VTOR_INIT=0x00000000
endif
endif
include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM TRUE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC TRUE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
#include "test.h"
#include "lwipthread.h"
#include "web/web.h"
/*
* Green LED blinker thread, times are in milliseconds.
*/
static WORKING_AREA(waThread1, 128);
static msg_t Thread1(void *arg) {
(void)arg;
chRegSetThreadName("blinker");
while (TRUE) {
palClearPad(GPIO2, GPIO2_LED);
chThdSleepMilliseconds(500);
palSetPad(GPIO2, GPIO2_LED);
chThdSleepMilliseconds(500);
}
}
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Activates the serial driver 6 using the driver default configuration.
*/
sdStart(&SD4, NULL);
/*
* Creates the blinker thread.
*/
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
/*
* Creates the LWIP threads (it changes priority internally).
*/
chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 1,
lwip_thread, NULL);
/*
* Creates the HTTP thread (it changes priority internally).
*/
chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1,
http_server, NULL);
/*
* Normal main() thread activity, in this demo it does nothing except
* sleeping in a loop and check the button state.
*/
while (TRUE) {
if (!palReadPad(GPIO3, GPIO3_SW_USER1)) {
TestThread(&SD4);
}
chThdSleepMilliseconds(500);
}
}

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* LPC43xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the driver
* is enabled in halconf.h.
*
* IRQ priorities:
* 7...0 Lowest...highest.
*
* LPC base clock sources:
* 0x00 32 kHz oscillator
* 0x01 IRC (default)
* 0x02 ENET_RX_CLK
* 0x03 ENET_TX_CLK
* 0x04 GP_CLKIN
* 0x06 Crystal oscillator
* 0x07 PLL0USB
* 0x08 PLL0AUDIO
* 0x09 PLL1
* 0x0C IDIVA
* 0x0D IDIVB
* 0x0E IDIVC
* 0x0F IDIVD
* 0x10 IDIVE
*/
/*
* HAL driver system settings.
*/
#define LPC_XTAL_ENABLE TRUE
#define LPC_PLL1_ENABLE TRUE
#define LPC_PLL1_MUL 17
#define LPC_PLL1_PREDIV 1
#define LPC_PLL1_POSTDIV_ENABLE TRUE
#define LPC_PLL1_POSTDIV 2
#define LPC_PLL0USB_ENABLE FALSE
#define LPC_PLL0AUDIO_ENABLE FALSE
#define LPC_HAS_FLASH FALSE
/* Clock dividers */
#define LPC_IDIVA_ENABLE FALSE
#define LPC_IDIVA_DIV 1
#define LPC_IDIVA_SRC 0x09
#define LPC_IDIVB_ENABLE TRUE
#define LPC_IDIVB_DIV 2
#define LPC_IDIVB_SRC 0x09
#define LPC_IDIVC_ENABLE TRUE
#define LPC_IDIVC_DIV 3
#define LPC_IDIVC_SRC 0x09
#define LPC_IDIVD_ENABLE FALSE
#define LPC_IDIVD_DIV 1
#define LPC_IDIVD_SRC 0x09
#define LPC_IDIVE_ENABLE FALSE
#define LPC_IDIVE_DIV 1
#define LPC_IDIVE_SRC 0x09
/* Base clocks */
#define LPC_BASE_USB0_CLK_ENABLE FALSE /* Base clock for USB0. */
#define LPC_BASE_PERIPH_CLK_ENABLE TRUE /* Base clock for Cortex-M0SUB subsystem, SGPIO. */
#define LPC_BASE_PERIPH_CLK_SRC 0x09
#define LPC_BASE_USB1_CLK_ENABLE TRUE /* Base clock for USB1. */
#define LPC_BASE_USB1_CLK_SRC 0x01
#define LPC_BASE_SPIFI_CLK_ENABLE TRUE /* Base clock for SPIFI. */
#define LPC_BASE_SPIFI_CLK_SRC 0x0D
#define LPC_BASE_SPI_CLK_ENABLE TRUE /* Base clock for SPI. */
#define LPC_BASE_SPI_CLK_SRC 0x01
#define LPC_BASE_PHY_RX_CLK_ENABLE TRUE /* Base clock for Ethernet PHY Receive clock. */
#define LPC_BASE_PHY_RX_CLK_SRC 0x0E
#define LPC_BASE_PHY_TX_CLK_ENABLE TRUE /* Base clock for Ethernet PHY Transmit clock. */
#define LPC_BASE_PHY_TX_CLK_SRC 0x0E
#define LPC_BASE_APB1_CLK_ENABLE TRUE /* Base clock for APB1: I2C0, I2S, CAN1. */
#define LPC_BASE_APB1_CLK_SRC 0x01
#define LPC_BASE_APB3_CLK_ENABLE TRUE /* Base clock for APB3: I2C1, DAC, ADC0, ADC1, CAN0. */
#define LPC_BASE_APB3_CLK_SRC 0x01
#define LPC_BASE_LCD_CLK_ENABLE FALSE /* Base clock for LCD. */
#define LPC_BASE_LCD_CLK_SRC 0x01
#define LPC_BASE_SDIO_CLK_ENABLE FALSE /* Base clock for SD/MMC. */
#define LPC_BASE_SDIO_CLK_SRC 0x01
#define LPC_BASE_SSP0_CLK_ENABLE TRUE /* Base clock for SSP0. */
#define LPC_BASE_SSP0_CLK_SRC 0x01
#define LPC_BASE_SSP1_CLK_ENABLE TRUE /* Base clock for SSP1. */
#define LPC_BASE_SSP1_CLK_SRC 0x01
#define LPC_BASE_UART0_CLK_ENABLE TRUE /* Base clock for UART0. */
#define LPC_BASE_UART0_CLK_SRC 0x01
#define LPC_BASE_UART1_CLK_ENABLE TRUE /* Base clock for UART1. */
#define LPC_BASE_UART1_CLK_SRC 0x01
#define LPC_BASE_UART2_CLK_ENABLE TRUE /* Base clock for UART2. */
#define LPC_BASE_UART2_CLK_SRC 0x01
#define LPC_BASE_UART3_CLK_ENABLE TRUE /* Base clock for UART3. */
#define LPC_BASE_UART3_CLK_SRC 0x01
#define LPC_BASE_OUT_CLK_ENABLE FALSE /* Base clock for UART0. */
#define LPC_BASE_OUT_CLK_SRC 0x01
#define LPC_BASE_APLL_CLK_ENABLE FALSE /* Base clock for audio system. */
#define LPC_BASE_APLL_CLK_SRC 0x01
#define LPC_BASE_CGU_OUT0_CLK_ENABLE FALSE /* Base clock for CGU_OUT0 clock output. */
#define LPC_BASE_CGU_OUT0_CLK_SRC 0x01
#define LPC_BASE_CGU_OUT1_CLK_ENABLE FALSE /* Base clock for CGU_OUT1 clock output. */
#define LPC_BASE_CGU_OUT1_CLK_SRC 0x01
/*
* GPT driver system settings.
*/
#define LPC_GPT_USE_TIM0 FALSE
#define LPC_GPT_USE_TIM1 FALSE
#define LPC_GPT_USE_TIM2 FALSE
#define LPC_GPT_USE_TIM3 FALSE
#define LPC_GPT_TIM0_IRQ_PRIORITY 2
#define LPC_GPT_TIM1_IRQ_PRIORITY 2
#define LPC_GPT_TIM2_IRQ_PRIORITY 2
#define LPC_GPT_TIM3_IRQ_PRIORITY 2
/*
* SERIAL driver system settings.
*/
#define LPC_SERIAL_USE_UART0 FALSE
#define LPC_SERIAL_USE_UART1 FALSE
#define LPC_SERIAL_USE_UART2 FALSE
#define LPC_SERIAL_USE_UART3 TRUE
#define LPC_SERIAL_FIFO_PRELOAD 16
#define LPC_SERIAL_UART0_IRQ_PRIORITY 3
#define LPC_SERIAL_UART1_IRQ_PRIORITY 3
#define LPC_SERIAL_UART2_IRQ_PRIORITY 3
#define LPC_SERIAL_UART3_IRQ_PRIORITY 3
/*
* I2C driver system settings.
*/
#define LPC_I2C_USE_I2C0 FALSE
#define LPC_I2C_USE_I2C1 FALSE
#define LPC_I2C_I2C0_IRQ_PRIORITY 3
#define LPC_I2C_I2C1_IRQ_PRIORITY 3
/*
* SPI driver system settings.
*/
#define LPC_SPI_USE_SSP0 FALSE
#define LPC_SPI_USE_SSP1 FALSE
#define LPC_SPI_SSP0_IRQ_PRIORITY 5
#define LPC_SPI_SSP1_IRQ_PRIORITY 5
/*
* RTC driver system settings.
*/
#define LPC_RTC_IS_CALENDAR TRUE
#define LPC_RTC_USE_ALARM TRUE
#define LPC_RTC_IRQ_PRIORITY 3
/*
* MAC driver system settings.
*/
#define LPC_MAC_TRANSMIT_BUFFERS 2
#define LPC_MAC_RECEIVE_BUFFERS 4
#define LPC_MAC_BUFFERS_SIZE 1522
#define LPC_MAC_PHY_TIMEOUT 100
#define LPC_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define LPC_MAC_ETH1_IRQ_PRIORITY 13

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file is a modified version of the lwIP web server demo. The original
* author is unknown because the file didn't contain any license information.
*/
/**
* @file web.c
* @brief HTTP server wrapper thread code.
* @addtogroup WEB_THREAD
* @{
*/
#include "ch.h"
#include "lwip/opt.h"
#include "lwip/arch.h"
#include "lwip/api.h"
#include "web.h"
#if LWIP_NETCONN
static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n";
static const char http_index_html[] = "<html><head><title>Congrats!</title></head><body><h1>Welcome to our lwIP HTTP server!</h1><p>This is a small test page.</body></html>";
static void http_server_serve(struct netconn *conn) {
struct netbuf *inbuf;
char *buf;
u16_t buflen;
err_t err;
/* Read the data from the port, blocking if nothing yet there.
We assume the request (the part we care about) is in one netbuf */
err = netconn_recv(conn, &inbuf);
if (err == ERR_OK) {
netbuf_data(inbuf, (void **)&buf, &buflen);
/* Is this an HTTP GET command? (only check the first 5 chars, since
there are other formats for GET, and we're keeping it very simple )*/
if (buflen>=5 &&
buf[0]=='G' &&
buf[1]=='E' &&
buf[2]=='T' &&
buf[3]==' ' &&
buf[4]=='/' ) {
/* Send the HTML header
* subtract 1 from the size, since we dont send the \0 in the string
* NETCONN_NOCOPY: our data is const static, so no need to copy it
*/
netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY);
/* Send our HTML page */
netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY);
}
}
/* Close the connection (server closes in HTTP) */
netconn_close(conn);
/* Delete the buffer (netconn_recv gives us ownership,
so we have to make sure to deallocate the buffer) */
netbuf_delete(inbuf);
}
/**
* Stack area for the http thread.
*/
WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
/**
* HTTP server thread.
*/
msg_t http_server(void *p) {
struct netconn *conn, *newconn;
err_t err;
(void)p;
/* Create a new TCP connection handle */
conn = netconn_new(NETCONN_TCP);
LWIP_ERROR("http_server: invalid conn", (conn != NULL), return RDY_RESET;);
/* Bind to port 80 (HTTP) with default IP address */
netconn_bind(conn, NULL, WEB_THREAD_PORT);
/* Put the connection into LISTEN state */
netconn_listen(conn);
/* Goes to the final priority after initialization.*/
chThdSetPriority(WEB_THREAD_PRIORITY);
while(1) {
err = netconn_accept(conn, &newconn);
if (err != ERR_OK)
continue;
http_server_serve(newconn);
netconn_delete(newconn);
}
return RDY_OK;
}
#endif /* LWIP_NETCONN */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file web.h
* @brief HTTP server wrapper thread macros and structures.
* @addtogroup WEB_THREAD
* @{
*/
#ifndef _WEB_H_
#define _WEB_H_
#ifndef WEB_THREAD_STACK_SIZE
#define WEB_THREAD_STACK_SIZE 1024
#endif
#ifndef WEB_THREAD_PORT
#define WEB_THREAD_PORT 80
#endif
#ifndef WEB_THREAD_PRIORITY
#define WEB_THREAD_PRIORITY (LOWPRIO + 2)
#endif
extern WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
#ifdef __cplusplus
extern "C" {
#endif
msg_t http_server(void *p);
#ifdef __cplusplus
}
#endif
#endif /* _WEB_H_ */
/** @} */

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##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Enables the use of FPU on Cortex-M4.
ifeq ($(USE_FPU),)
USE_FPU = no
endif
# Enables the use of Cortex-M4 by LPC43xx in LPC43xx.h.
ifeq ($(USE_CORE_M4),)
USE_CORE_M4 = yes
endif
# LPC43xx boot select: ram, spifi_flash_debug, flash.
ifeq ($(LPC_BOOT_SELECT),)
LPC_BOOT_SELECT = ram
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files
CHIBIOS = ../..
include $(CHIBIOS)/boards/NONSTANDARD_LPC4330_SBC/board.mk
include $(CHIBIOS)/os/hal/platforms/LPC43xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC43xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/LPC4330_RAM_DEBUG.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(PORTSRC) \
$(KERNSRC) \
$(TESTSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
$(CHIBIOS)/os/various/evtimer.c \
$(CHIBIOS)/os/various/syscalls.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m4
#TRGT = arm-elf-
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
OD = $(TRGT)objdump
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
#
# Compiler settings
##############################################################################
##############################################################################
# Start of default section
#
# List all default C defines here, like -D_DEBUG=1
DDEFS = -D__NEWLIB__
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
ifeq ($(USE_FPU),yes)
USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
DDEFS += -DCORTEX_USE_FPU=TRUE
else
DDEFS += -DCORTEX_USE_FPU=FALSE
endif
ifeq ($(USE_CORE_M4),yes)
DDEFS += -DCORE_M4
endif
ifeq ($(LPC_BOOT_SELECT), ram)
DDEFS += -DCORTEX_VTOR_INIT=0x10000000
else
ifeq ($(LPC_BOOT_SELECT), spifi_flash_debug)
DDEFS += -DCORTEX_VTOR_INIT=0x14000000
else
DDEFS += -DCORTEX_VTOR_INIT=0x00000000
endif
endif
include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
#include "test.h"
/*
* Red LED blinker thread, times are in milliseconds.
*/
static WORKING_AREA(waThread1, 128);
static msg_t Thread1(void *arg) {
(void)arg;
chRegSetThreadName("blinker1");
while (TRUE) {
palTogglePad(GPIO2, GPIO2_LED);
chThdSleepMilliseconds(500);
}
}
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Activates the SD1 and SPI1 drivers.
*/
sdStart(&SD4, NULL); /* Default: 38400,8,N,1. */
/*
* Creates the blinker threads.
*/
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
/*
* Normal main() thread activity.
*/
while (TRUE) {
if (!palReadPad(GPIO3, GPIO3_SW_USER1)) {
TestThread(&SD4);
}
chThdSleepMilliseconds(100);
}
}

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* LPC43xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the driver
* is enabled in halconf.h.
*
* IRQ priorities:
* 7...0 Lowest...highest.
*
* LPC base clock sources:
* 0x00 32 kHz oscillator
* 0x01 IRC (default)
* 0x02 ENET_RX_CLK
* 0x03 ENET_TX_CLK
* 0x04 GP_CLKIN
* 0x06 Crystal oscillator
* 0x07 PLL0USB
* 0x08 PLL0AUDIO
* 0x09 PLL1
* 0x0C IDIVA
* 0x0D IDIVB
* 0x0E IDIVC
* 0x0F IDIVD
* 0x10 IDIVE
*/
/*
* HAL driver system settings.
*/
#define LPC_XTAL_ENABLE TRUE
#define LPC_PLL1_ENABLE TRUE
#define LPC_PLL1_MUL 17
#define LPC_PLL1_PREDIV 1
#define LPC_PLL1_POSTDIV_ENABLE FALSE
#define LPC_PLL1_POSTDIV 2
#define LPC_PLL0USB_ENABLE FALSE
#define LPC_PLL0AUDIO_ENABLE FALSE
#define LPC_FLASHLESS TRUE
/* Clock dividers */
#define LPC_IDIVA_ENABLE FALSE
#define LPC_IDIVA_DIV 1
#define LPC_IDIVA_SRC 0x09
#define LPC_IDIVB_ENABLE FALSE
#define LPC_IDIVB_DIV 2
#define LPC_IDIVB_SRC 0x09
#define LPC_IDIVC_ENABLE FALSE
#define LPC_IDIVC_DIV 3
#define LPC_IDIVC_SRC 0x09
#define LPC_IDIVD_ENABLE FALSE
#define LPC_IDIVD_DIV 1
#define LPC_IDIVD_SRC 0x09
#define LPC_IDIVE_ENABLE FALSE
#define LPC_IDIVE_DIV 1
#define LPC_IDIVE_SRC 0x09
/* Base clocks */
#define LPC_BASE_USB0_CLK_ENABLE FALSE /* Base clock for USB0. */
#define LPC_BASE_PERIPH_CLK_ENABLE TRUE /* Base clock for Cortex-M0SUB subsystem, SGPIO. */
#define LPC_BASE_PERIPH_CLK_SRC 0x09
#define LPC_BASE_USB1_CLK_ENABLE TRUE /* Base clock for USB1. */
#define LPC_BASE_USB1_CLK_SRC 0x01
#define LPC_BASE_SPIFI_CLK_ENABLE FALSE /* Base clock for SPIFI. */
#define LPC_BASE_SPIFI_CLK_SRC 0x0D
#define LPC_BASE_SPI_CLK_ENABLE TRUE /* Base clock for SPI. */
#define LPC_BASE_SPI_CLK_SRC 0x01
#define LPC_BASE_PHY_RX_CLK_ENABLE FALSE /* Base clock for Ethernet PHY Receive clock. */
#define LPC_BASE_PHY_RX_CLK_SRC 0x0E
#define LPC_BASE_PHY_TX_CLK_ENABLE FALSE /* Base clock for Ethernet PHY Transmit clock. */
#define LPC_BASE_PHY_TX_CLK_SRC 0x0E
#define LPC_BASE_APB1_CLK_ENABLE TRUE /* Base clock for APB1: I2C0, I2S, CAN1. */
#define LPC_BASE_APB1_CLK_SRC 0x01
#define LPC_BASE_APB3_CLK_ENABLE TRUE /* Base clock for APB3: I2C1, DAC, ADC0, ADC1, CAN0. */
#define LPC_BASE_APB3_CLK_SRC 0x01
#define LPC_BASE_LCD_CLK_ENABLE FALSE /* Base clock for LCD. */
#define LPC_BASE_LCD_CLK_SRC 0x01
#define LPC_BASE_SDIO_CLK_ENABLE FALSE /* Base clock for SD/MMC. */
#define LPC_BASE_SDIO_CLK_SRC 0x01
#define LPC_BASE_SSP0_CLK_ENABLE TRUE /* Base clock for SSP0. */
#define LPC_BASE_SSP0_CLK_SRC 0x01
#define LPC_BASE_SSP1_CLK_ENABLE TRUE /* Base clock for SSP1. */
#define LPC_BASE_SSP1_CLK_SRC 0x01
#define LPC_BASE_UART0_CLK_ENABLE TRUE /* Base clock for UART0. */
#define LPC_BASE_UART0_CLK_SRC 0x01
#define LPC_BASE_UART1_CLK_ENABLE TRUE /* Base clock for UART1. */
#define LPC_BASE_UART1_CLK_SRC 0x01
#define LPC_BASE_UART2_CLK_ENABLE TRUE /* Base clock for UART2. */
#define LPC_BASE_UART2_CLK_SRC 0x01
#define LPC_BASE_UART3_CLK_ENABLE TRUE /* Base clock for UART3. */
#define LPC_BASE_UART3_CLK_SRC 0x01
#define LPC_BASE_OUT_CLK_ENABLE FALSE /* Base clock for UART0. */
#define LPC_BASE_OUT_CLK_SRC 0x01
#define LPC_BASE_APLL_CLK_ENABLE FALSE /* Base clock for audio system. */
#define LPC_BASE_APLL_CLK_SRC 0x01
#define LPC_BASE_CGU_OUT0_CLK_ENABLE FALSE /* Base clock for CGU_OUT0 clock output. */
#define LPC_BASE_CGU_OUT0_CLK_SRC 0x01
#define LPC_BASE_CGU_OUT1_CLK_ENABLE FALSE /* Base clock for CGU_OUT1 clock output. */
#define LPC_BASE_CGU_OUT1_CLK_SRC 0x01
/*
* GPT driver system settings.
*/
#define LPC_GPT_USE_TIM0 FALSE
#define LPC_GPT_USE_TIM1 FALSE
#define LPC_GPT_USE_TIM2 FALSE
#define LPC_GPT_USE_TIM3 FALSE
#define LPC_GPT_TIM0_IRQ_PRIORITY 2
#define LPC_GPT_TIM1_IRQ_PRIORITY 2
#define LPC_GPT_TIM2_IRQ_PRIORITY 2
#define LPC_GPT_TIM3_IRQ_PRIORITY 2
/*
* SERIAL driver system settings.
*/
#define LPC_SERIAL_USE_UART0 FALSE
#define LPC_SERIAL_USE_UART1 FALSE
#define LPC_SERIAL_USE_UART2 FALSE
#define LPC_SERIAL_USE_UART3 TRUE
#define LPC_SERIAL_FIFO_PRELOAD 16
#define LPC_SERIAL_UART0_IRQ_PRIORITY 3
#define LPC_SERIAL_UART1_IRQ_PRIORITY 3
#define LPC_SERIAL_UART2_IRQ_PRIORITY 3
#define LPC_SERIAL_UART3_IRQ_PRIORITY 3
/*
* I2C driver system settings.
*/
#define LPC_I2C_USE_I2C0 FALSE
#define LPC_I2C_USE_I2C1 FALSE
#define LPC_I2C_I2C0_IRQ_PRIORITY 3
#define LPC_I2C_I2C1_IRQ_PRIORITY 3
/*
* SPI driver system settings.
*/
#define LPC_SPI_USE_SSP0 FALSE
#define LPC_SPI_USE_SSP1 FALSE
#define LPC_SPI_SSP0_IRQ_PRIORITY 5
#define LPC_SPI_SSP1_IRQ_PRIORITY 5