Fixed bug 3567597. STM32F1x rtc_lld_init glitches rtc on hard reset
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4666 35acf78f-673a-0410-8e92-d51de3d6d3f4master
parent
954a365b01
commit
98c5ccf6b8
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@ -135,17 +135,26 @@ CH_IRQ_HANDLER(RTC_IRQHandler) {
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*
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*
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* @notapi
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* @notapi
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*/
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*/
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void rtc_lld_init(void){
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void rtc_lld_init(void){
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/* Required because access to PRL.*/
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/* Required because access to PRL.*/
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rtc_lld_apb1_sync();
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rtc_lld_apb1_sync();
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/* Writes preload register only if its value is not equal to desired value.*/
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/*
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if (STM32_RTCCLK != (((uint32_t)(RTC->PRLH)) << 16) +
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* Writes preload register only if its value is not equal to desired value.
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((uint32_t)RTC->PRLL) + 1) {
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*
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* Ref CD00171190: RM0008 Reference manual Cls 18.4.3 The RTC->PRL registers
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* are write only. We must store the value for the pre-scaler in BKP->DR1
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* and BKP->DR1 so we know it has been set.
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* The pre-scaler must not be set on every reset as RTC clock counts are
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* lost when it is set.
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*/
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if ((STM32_RTCCLK - 1) != ((((uint32_t)BKP->DR1) << 16) | BKP->DR2)){
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rtc_lld_acquire();
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rtc_lld_acquire();
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RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16);
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RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F;
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RTC->PRLL = (uint16_t)((STM32_RTCCLK - 1) & 0xFFFF);
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BKP->DR1 = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F;
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RTC->PRLL = (uint16_t)(((STM32_RTCCLK - 1)) & 0xFFFF);
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BKP->DR2 = (uint16_t)(((STM32_RTCCLK - 1)) & 0xFFFF);
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rtc_lld_release();
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rtc_lld_release();
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}
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}
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