STM32L0xx-related work.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8093 35acf78f-673a-0410-8e92-d51de3d6d3f4master
gdisirio
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96a249effd
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F0xx/hal_lld.c
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* @brief STM32F0xx HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief CMSIS system core clock variable.
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* @note It is declared in system_stm32f0xx.h.
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*/
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uint32_t SystemCoreClock = STM32_SYSCLK;
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Initializes the backup domain.
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* @note WARNING! Changing clock source impossible without resetting
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* of the whole BKP domain.
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*/
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static void hal_lld_backup_domain_init(void) {
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/* Backup domain access enabled and left open.*/
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PWR->CR |= PWR_CR_DBP;
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/* Reset BKP domain if different clock source selected.*/
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if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
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/* Backup domain reset.*/
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RCC->BDCR = RCC_BDCR_BDRST;
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RCC->BDCR = 0;
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}
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/* If enabled then the LSE is started.*/
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#if STM32_LSE_ENABLED
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#if defined(STM32_LSE_BYPASS)
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/* LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
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#else
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/* No LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
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#endif
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while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
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; /* Waits until LSE is stable. */
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#endif
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#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
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/* If the backup domain hasn't been initialized yet then proceed with
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initialization.*/
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if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
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/* Selects clock source.*/
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RCC->BDCR |= STM32_RTCSEL;
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/* RTC clock enabled.*/
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RCC->BDCR |= RCC_BDCR_RTCEN;
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}
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#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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/* Reset of all peripherals.*/
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rccResetAHB(0xFFFFFFFF);
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rccResetAPB1(0xFFFFFFFF);
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rccResetAPB2(~RCC_APB2RSTR_DBGMCURST);
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/* PWR clock enabled.*/
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rccEnablePWRInterface(FALSE);
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/* Initializes the backup domain.*/
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hal_lld_backup_domain_init();
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#if defined(STM32_DMA_REQUIRED)
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dmaInit();
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#endif
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/* Programmable voltage detector enable.*/
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#if STM32_PVD_ENABLE
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PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
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#endif /* STM32_PVD_ENABLE */
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}
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/**
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* @brief STM32 clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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* @note This function should be invoked just after the system reset.
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*
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* @special
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*/
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void stm32_clock_init(void) {
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#if !STM32_NO_INIT
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/* HSI setup, it enforces the reset situation in order to handle possible
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problems with JTAG probes and re-initializations.*/
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RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
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while (!(RCC->CR & RCC_CR_HSIRDY))
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; /* Wait until HSI is stable. */
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/* HSI is selected as new source without touching the other fields in
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CFGR. Clearing the register has to be postponed after HSI is the
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new source.*/
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RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
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RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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; /* Wait until HSI is selected. */
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/* Registers finally cleared to reset values.*/
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RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
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RCC->CFGR = 0; /* CFGR reset value. */
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#if STM32_HSE_ENABLED
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/* HSE activation.*/
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#if defined(STM32_HSE_BYPASS)
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/* HSE Bypass.*/
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RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
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#else
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/* No HSE Bypass.*/
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RCC->CR |= RCC_CR_HSEON;
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#endif
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while (!(RCC->CR & RCC_CR_HSERDY))
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; /* Waits until HSE is stable. */
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#endif
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#if STM32_HSI14_ENABLED
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/* HSI14 activation.*/
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RCC->CR2 |= RCC_CR2_HSI14ON;
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while (!(RCC->CR2 & RCC_CR2_HSI14RDY))
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; /* Waits until HSI14 is stable. */
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#endif
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#if STM32_HSI48_ENABLED
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/* HSI48 activation.*/
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RCC->CR2 |= RCC_CR2_HSI48ON;
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while (!(RCC->CR2 & RCC_CR2_HSI48RDY))
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; /* Waits until HSI48 is stable. */
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#endif
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#if STM32_LSI_ENABLED
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/* LSI activation.*/
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RCC->CSR |= RCC_CSR_LSION;
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while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
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; /* Waits until LSI is stable. */
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#endif
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/* Clock settings.*/
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RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |
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STM32_ADCPRE | STM32_PPRE | STM32_HPRE;
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RCC->CFGR2 = STM32_PREDIV;
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RCC->CFGR3 = STM32_ADCSW | STM32_USBSW | STM32_CECSW |
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STM32_I2C1SW | STM32_USART1SW;
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#if STM32_ACTIVATE_PLL
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/* PLL activation.*/
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL is stable. */
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#endif
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/* Flash setup and final clock selection. */
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FLASH->ACR = STM32_FLASHBITS;
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/* Switching to the configured clock source if it is different from HSI.*/
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#if (STM32_SW != STM32_SW_HSI)
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/* Switches clock source.*/
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RCC->CFGR |= STM32_SW;
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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; /* Waits selection complete. */
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#endif
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
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#endif /* !STM32_NO_INIT */
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}
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/** @} */
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@ -0,0 +1,979 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32L0xx/hal_lld.h
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* @brief STM32L0xx HAL subsystem low level driver header.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - STM32_LSECLK.
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* - STM32_LSEDRV.
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* - STM32_LSE_BYPASS (optionally).
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* - STM32_HSECLK.
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* - STM32_HSE_BYPASS (optionally).
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* .
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* One of the following macros must also be defined:
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* - STM32L051xx, STM32L052xx, STM32L053xx,
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* STM32L061xx, STM32L062xx, STM32L063xx for ultra-low-power MCUs.
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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/*
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* Registry definitions.
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*/
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#include "stm32_registry.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Platform identification macros
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* @{
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*/
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#if defined(STM32L051xx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32L051xx ultra-low-power MCU"
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#elif defined(STM32L052xx)
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#define PLATFORM_NAME "STM32L052xx ultra-low-power MCU"
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#elif defined(STM32L053xx)
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#define PLATFORM_NAME "STM32L053xx ultra-low-power MCU"
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#elif defined(STM32L061xx)
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#define PLATFORM_NAME "STM32L061xx ultra-low-power MCU"
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#elif defined(STM32L062xx)
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#define PLATFORM_NAME "STM32L062xx ultra-low-power MCU"
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#elif defined(STM32L063xx)
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#define PLATFORM_NAME "STM32L063xx ultra-low-power MCU"
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#else
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#error "STM32L0xx device not specified"
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#endif
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/** @} */
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/**
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* @name Absolute Maximum Ratings
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* @{
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*/
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/**
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* @brief Maximum system clock frequency.
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*/
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#define STM32_SYSCLK_MAX 32000000
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/**
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* @brief Maximum HSE clock frequency.
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*/
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#define STM32_HSECLK_MAX 24000000
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/**
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* @brief Minimum HSE clock frequency.
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*/
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#define STM32_HSECLK_MIN 2000000
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/**
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* @brief Maximum LSE clock frequency.
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*/
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#define STM32_LSECLK_MAX 1000000
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/**
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* @brief Minimum LSE clock frequency.
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*/
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#define STM32_LSECLK_MIN 1000
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/**
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* @brief Maximum PLLs input clock frequency.
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*/
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#define STM32_PLLIN_MAX 24000000
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/**
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* @brief Minimum PLLs input clock frequency.
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*/
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#define STM32_PLLIN_MIN 2000000
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/**
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* @brief Maximum PLL output clock frequency.
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*/
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#define STM32_PLLOUT_MAX 32000000
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/**
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* @brief Minimum PLL output clock frequency.
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*/
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#define STM32_PLLOUT_MIN 2000000
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/**
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* @brief Maximum APB clock frequency.
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*/
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#define STM32_PCLK1_MAX 32000000
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/**
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* @brief Maximum APB clock frequency.
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*/
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#define STM32_PCLK2_MAX 32000000
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/** @} */
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/**
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* @name Internal clock sources
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* @{
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*/
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#define STM32_HSI16CLK 16000000 /**< 16MHz internal clock. */
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#define STM32_HSI48CLK 48000000 /**< 48MHz internal clock. */
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#define STM32_LSICLK 38000 /**< Low speed internal clock. */
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/** @} */
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/**
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* @name PWR_CR register bits definitions
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* @{
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*/
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#define STM32_PLS_MASK (7 << 5) /**< PLS field mask. */
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#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
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#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
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#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
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#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
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#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
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#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
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#define STM32_PLS_EXT (7 << 5) /**< PVD level 7. */
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#define STM32_VOS_MASK (3 << 11) /**< VOS field mask. */
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#define STM32_VOS_RANGE1 (1 << 11) /**< VOS level 1.8 volts. */
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#define STM32_VOS_RANGE2 (2 << 11) /**< VOS level 1.5 volts. */
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#define STM32_VOS_RANGE3 (3 << 11) /**< VOS level 1.2 volts. */
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/** @} */
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/**
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* @name RCC_CR register bits definitions
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* @{
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*/
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#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */
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#define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */
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#define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */
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#define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */
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#define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */
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/** @} */
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/**
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* @name RCC_CFGR register bits definitions
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* @{
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*/
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#define STM32_SW_MASK (3 << 0) /**< SW field mask. */
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#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
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#define STM32_SW_HSI16 (1 << 0) /**< SYSCLK source is HSI16 */
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#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
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#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
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#define STM32_HPRE_MASK (15 << 4) /**< HPRE field mask. */
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#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
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#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
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#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
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#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
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#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
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#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
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#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
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#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
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#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
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#define STM32_PPRE1_MASK (7 << 8) /**< PPRE2 field mask. */
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#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
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#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
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#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
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#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
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#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
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#define STM32_PPRE2_MASK (7 << 12) /**< PPRE2 field mask. */
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#define STM32_PPRE2_DIV1 (0 << 12) /**< HCLK divided by 1. */
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#define STM32_PPRE2_DIV2 (4 << 12) /**< HCLK divided by 2. */
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#define STM32_PPRE2_DIV4 (5 << 12) /**< HCLK divided by 4. */
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#define STM32_PPRE2_DIV8 (6 << 12) /**< HCLK divided by 8. */
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#define STM32_PPRE2_DIV16 (7 << 12) /**< HCLK divided by 16. */
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#define STM32_STOPWUCK_MASK (1 << 15) /**< PLLDIV field mask. */
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#define STM32_STOPWUCK_MSI (0 << 15) /**< MSI is wakeup clock. */
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#define STM32_STOPWUCK_HSI16 (1 << 15) /**< HSI16 is wakeup clock. */
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#define STM32_PLLSRC_MASK (1 << 16) /**< PLLSRC field mask. */
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#define STM32_PLLSRC_HSI16 (0 << 16) /**< PLL clock source is HSI16. */
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#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
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#define STM32_PLLMUL_MASK (15 << 18) /**< PLLMUL field mask. */
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#define STM32_PLLMUL_MUL3 (0 << 18) /**< PLL multiplier is 3. */
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#define STM32_PLLMUL_MUL4 (1 << 18) /**< PLL multiplier is 4. */
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#define STM32_PLLMUL_MUL6 (2 << 18) /**< PLL multiplier is 6. */
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#define STM32_PLLMUL_MUL8 (3 << 18) /**< PLL multiplier is 8. */
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#define STM32_PLLMUL_MUL12 (4 << 18) /**< PLL multiplier is 12. */
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#define STM32_PLLMUL_MUL16 (5 << 18) /**< PLL multiplier is 16. */
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#define STM32_PLLMUL_MUL24 (6 << 18) /**< PLL multiplier is 24. */
|
||||
#define STM32_PLLMUL_MUL32 (7 << 18) /**< PLL multiplier is 32. */
|
||||
#define STM32_PLLMUL_MUL48 (8 << 18) /**< PLL multiplier is 48. */
|
||||
|
||||
#define STM32_PLLDIV_MASK (3 << 22) /**< PLLDIV field mask. */
|
||||
#define STM32_PLLDIV_DIV2 (1 << 22) /**< PLL divided by 2. */
|
||||
#define STM32_PLLDIV_DIV3 (2 << 22) /**< PLL divided by 3. */
|
||||
#define STM32_PLLDIV_DIV4 (3 << 22) /**< PLL divided by 4. */
|
||||
|
||||
#define STM32_MCOSEL_MASK (15 << 24) /**< MCOSEL field mask. */
|
||||
#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
|
||||
#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
|
||||
#define STM32_MCOSEL_HSI16 (2 << 24) /**< HSI16 clock on MCO pin. */
|
||||
#define STM32_MCOSEL_MSI (3 << 24) /**< MSI clock on MCO pin. */
|
||||
#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */
|
||||
#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
|
||||
#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
|
||||
#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
|
||||
#define STM32_MCOSEL_HSI48 (8 << 24) /**< HSI48 clock on MCO pin. */
|
||||
|
||||
#define STM32_MCOPRE_MASK (7 << 28) /**< MCOPRE field mask. */
|
||||
#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO is divided by 1. */
|
||||
#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO is divided by 1. */
|
||||
#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO is divided by 1. */
|
||||
#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO is divided by 1. */
|
||||
#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO is divided by 1. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RCC_ICSCR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */
|
||||
#define STM32_MSIRANGE_64K (0 << 13) /**< 64kHz nominal. */
|
||||
#define STM32_MSIRANGE_128K (1 << 13) /**< 128kHz nominal. */
|
||||
#define STM32_MSIRANGE_256K (2 << 13) /**< 256kHz nominal. */
|
||||
#define STM32_MSIRANGE_512K (3 << 13) /**< 512kHz nominal. */
|
||||
#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */
|
||||
#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */
|
||||
#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RCC_CSR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */
|
||||
#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */
|
||||
#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */
|
||||
#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */
|
||||
#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RCC_CCIPR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_USART1SEL_MASK (3 << 0) /**< USART1 clock source mask. */
|
||||
#define STM32_USART1SEL_APB (0 << 0) /**< USART1 clock is APB. */
|
||||
#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 clock is SYSCLK. */
|
||||
#define STM32_USART1SEL_HSI16 (2 << 0) /**< USART1 clock is HSI16. */
|
||||
#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 clock is LSE. */
|
||||
#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 clock source mask. */
|
||||
|
||||
#define STM32_USART2SEL_APB (0 << 2) /**< USART2 clock is APB. */
|
||||
#define STM32_USART2SEL_SYSCLK (1 << 2) /**< USART2 clock is SYSCLK. */
|
||||
#define STM32_USART2SEL_HSI16 (2 << 2) /**< USART2 clock is HSI16. */
|
||||
#define STM32_USART2SEL_LSE (3 << 2) /**< USART2 clock is LSE. */
|
||||
|
||||
#define STM32_LPUART1SEL_MASK (3 << 10) /**< LPUART1 clock source mask. */
|
||||
#define STM32_LPUART1SEL_APB (0 << 10) /**< LPUART1 clock is APB. */
|
||||
#define STM32_LPUART1SEL_SYSCLK (1 << 10) /**< LPUART1 clock is SYSCLK. */
|
||||
#define STM32_LPUART1SEL_HSI16 (2 << 10) /**< LPUART1 clock is HSI16. */
|
||||
#define STM32_LPUART1SEL_LSE (3 << 10) /**< LPUART1 clock is LSE. */
|
||||
|
||||
#define STM32_I2C1SEL_MASK (3 << 12) /**< I2C1 clock source mask. */
|
||||
#define STM32_I2C1SEL_APB (0 << 12) /**< I2C1 clock is APB. */
|
||||
#define STM32_I2C1SEL_SYSCLK (1 << 12) /**< I2C1 clock is SYSCLK. */
|
||||
#define STM32_I2C1SEL_HSI16 (2 << 12) /**< I2C1 clock is HSI16. */
|
||||
|
||||
#define STM32_I2C3SEL_MASK (3 << 16) /**< I2C3 clock source mask. */
|
||||
#define STM32_I2C3SEL_APB (0 << 16) /**< I2C3 clock is APB. */
|
||||
#define STM32_I2C3SEL_SYSCLK (1 << 16) /**< I2C3 clock is SYSCLK. */
|
||||
#define STM32_I2C3SEL_HSI16 (2 << 16) /**< I2C3 clock is HSI16. */
|
||||
|
||||
#define STM32_HSI48SEL_MASK (1 << 27) /**< HSI48SEL clock source mask.*/
|
||||
#define STM32_HSI48SEL_USBPLL (0 << 27) /**< HSI48 clock is USB PLL. */
|
||||
#define STM32_HSI48SEL_RC48 (1 << 27) /**< HSI48 clock is RC28. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Disables the PWR/RCC initialization in the HAL.
|
||||
*/
|
||||
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
|
||||
#define STM32_NO_INIT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Core voltage selection.
|
||||
* @note This setting affects all the performance and clock related
|
||||
* settings, the maximum performance is only obtainable selecting
|
||||
* the maximum voltage.
|
||||
*/
|
||||
#if !defined(STM32_VOS) || defined(__DOXYGEN__)
|
||||
#define STM32_VOS STM32_VOS_1P8
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the programmable voltage detector.
|
||||
*/
|
||||
#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
|
||||
#define STM32_PVD_ENABLE FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Sets voltage level for programmable voltage detector.
|
||||
*/
|
||||
#if !defined(STM32_PLS) || defined(__DOXYGEN__)
|
||||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the HSI clock source.
|
||||
*/
|
||||
#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the LSI clock source.
|
||||
*/
|
||||
#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the HSE clock source.
|
||||
*/
|
||||
#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_HSE_ENABLED FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the LSE clock source.
|
||||
*/
|
||||
#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC clock setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_CLOCK_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USB clock setting.
|
||||
*/
|
||||
#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_USB_CLOCK_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MSI frequency setting.
|
||||
*/
|
||||
#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
|
||||
#define STM32_MSIRANGE STM32_MSIRANGE_2M
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Main clock source selection.
|
||||
* @note If the selected clock source is not the PLL then the PLL is not
|
||||
* initialized and started.
|
||||
* @note The default value is calculated for a 32MHz system clock from
|
||||
* the internal 16MHz HSI clock.
|
||||
*/
|
||||
#if !defined(STM32_SW) || defined(__DOXYGEN__)
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clock source for the PLL.
|
||||
* @note This setting has only effect if the PLL is selected as the
|
||||
* system clock source.
|
||||
* @note The default value is calculated for a 32MHz system clock from
|
||||
* the internal 16MHz HSI clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSI
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL multiplier value.
|
||||
* @note The allowed values are 3, 4, 6, 8, 12, 16, 32, 48.
|
||||
* @note The default value is calculated for a 32MHz system clock from
|
||||
* the internal 16MHz HSI clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLMUL_VALUE 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL divider value.
|
||||
* @note The allowed values are 2, 3, 4.
|
||||
* @note The default value is calculated for a 32MHz system clock from
|
||||
* the internal 16MHz HSI clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLDIV_VALUE 3
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief AHB prescaler value.
|
||||
* @note The default value is calculated for a 32MHz system clock from
|
||||
* the internal 16MHz HSI clock.
|
||||
*/
|
||||
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB1 prescaler value.
|
||||
*/
|
||||
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB2 prescaler value.
|
||||
*/
|
||||
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCO clock source.
|
||||
*/
|
||||
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCO divider setting.
|
||||
*/
|
||||
#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_MCOPRE STM32_MCOPRE_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief RTC/LCD clock source.
|
||||
*/
|
||||
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief HSE divider toward RTC setting.
|
||||
*/
|
||||
#if !defined(STM32_RTCPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_RTCPRE STM32_RTCPRE_DIV2
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Configuration-related checks.
|
||||
*/
|
||||
#if !defined(STM32L0xx_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32L0xx_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
/* Voltage related limits.*/
|
||||
#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Maximum HSE clock frequency at current voltage setting.
|
||||
*/
|
||||
#define STM32_HSECLK_MAX 32000000
|
||||
|
||||
/**
|
||||
* @brief Maximum SYSCLK clock frequency at current voltage setting.
|
||||
*/
|
||||
#define STM32_SYSCLK_MAX 32000000
|
||||
|
||||
/**
|
||||
* @brief Maximum VCO clock frequency at current voltage setting.
|
||||
*/
|
||||
#define STM32_PLLVCO_MAX 96000000
|
||||
|
||||
/**
|
||||
* @brief Minimum VCO clock frequency at current voltage setting.
|
||||
*/
|
||||
#define STM32_PLLVCO_MIN 6000000
|
||||
|
||||
/**
|
||||
* @brief Maximum APB1 clock frequency.
|
||||
*/
|
||||
#define STM32_PCLK1_MAX 32000000
|
||||
|
||||
/**
|
||||
* @brief Maximum APB2 clock frequency.
|
||||
*/
|
||||
#define STM32_PCLK2_MAX 32000000
|
||||
|
||||
/**
|
||||
* @brief Maximum frequency not requiring a wait state for flash accesses.
|
||||
*/
|
||||
#define STM32_0WS_THRESHOLD 16000000
|
||||
|
||||
/**
|
||||
* @brief HSI availability at current voltage settings.
|
||||
*/
|
||||
#define STM32_HSI_AVAILABLE TRUE
|
||||
|
||||
#elif STM32_VOS == STM32_VOS_1P5
|
||||
#define STM32_HSECLK_MAX 16000000
|
||||
#define STM32_SYSCLK_MAX 16000000
|
||||
#define STM32_PLLVCO_MAX 48000000
|
||||
#define STM32_PLLVCO_MIN 6000000
|
||||
#define STM32_PCLK1_MAX 16000000
|
||||
#define STM32_PCLK2_MAX 16000000
|
||||
#define STM32_0WS_THRESHOLD 8000000
|
||||
#define STM32_HSI_AVAILABLE TRUE
|
||||
#elif STM32_VOS == STM32_VOS_1P2
|
||||
#define STM32_HSECLK_MAX 4000000
|
||||
#define STM32_SYSCLK_MAX 4000000
|
||||
#define STM32_PLLVCO_MAX 24000000
|
||||
#define STM32_PLLVCO_MIN 6000000
|
||||
#define STM32_PCLK1_MAX 4000000
|
||||
#define STM32_PCLK2_MAX 4000000
|
||||
#define STM32_0WS_THRESHOLD 2000000
|
||||
#define STM32_HSI_AVAILABLE FALSE
|
||||
#else
|
||||
#error "invalid STM32_VOS value specified"
|
||||
#endif
|
||||
|
||||
/* HSI related checks.*/
|
||||
#if STM32_HSI_ENABLED
|
||||
#if !STM32_HSI_AVAILABLE
|
||||
#error "impossible to activate HSI under the current voltage settings"
|
||||
#endif
|
||||
#else /* !STM32_HSI_ENABLED */
|
||||
#if STM32_ADC_CLOCK_ENABLED || \
|
||||
(STM32_SW == STM32_SW_HSI) || \
|
||||
((STM32_SW == STM32_SW_PLL) && \
|
||||
(STM32_PLLSRC == STM32_PLLSRC_HSI)) || \
|
||||
(STM32_MCOSEL == STM32_MCOSEL_HSI) || \
|
||||
((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
|
||||
(STM32_PLLSRC == STM32_PLLSRC_HSI))
|
||||
#error "required HSI clock is not enabled"
|
||||
#endif
|
||||
#endif /* !STM32_HSI_ENABLED */
|
||||
|
||||
/* HSE related checks.*/
|
||||
#if STM32_HSE_ENABLED
|
||||
#if STM32_HSECLK == 0
|
||||
#error "impossible to activate HSE"
|
||||
#endif
|
||||
#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX)
|
||||
#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)"
|
||||
#endif
|
||||
#else /* !STM32_HSE_ENABLED */
|
||||
#if (STM32_SW == STM32_SW_HSE) || \
|
||||
((STM32_SW == STM32_SW_PLL) && \
|
||||
(STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
|
||||
(STM32_MCOSEL == STM32_MCOSEL_HSE) || \
|
||||
((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
|
||||
(STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
|
||||
(STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
|
||||
#error "required HSE clock is not enabled"
|
||||
#endif
|
||||
#endif /* !STM32_HSE_ENABLED */
|
||||
|
||||
/* LSI related checks.*/
|
||||
#if STM32_LSI_ENABLED
|
||||
#else /* !STM32_LSI_ENABLED */
|
||||
|
||||
#if STM32_MCOSEL == STM32_MCOSEL_LSI
|
||||
#error "LSI not enabled, required by STM32_MCOSEL"
|
||||
#endif
|
||||
|
||||
#if STM32_RTCSEL == STM32_RTCSEL_LSI
|
||||
#error "LSI not enabled, required by STM32_RTCSEL"
|
||||
#endif
|
||||
|
||||
#endif /* !STM32_LSI_ENABLED */
|
||||
|
||||
/* LSE related checks.*/
|
||||
#if STM32_LSE_ENABLED
|
||||
#if (STM32_LSECLK == 0)
|
||||
#error "impossible to activate LSE"
|
||||
#endif
|
||||
#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)
|
||||
#error "STM32_LSECLK outside acceptable range (1...1000kHz)"
|
||||
#endif
|
||||
#else /* !STM32_LSE_ENABLED */
|
||||
|
||||
#if STM32_MCOSEL == STM32_MCOSEL_LSE
|
||||
#error "LSE not enabled, required by STM32_MCOSEL"
|
||||
#endif
|
||||
|
||||
#if STM32_RTCSEL == STM32_RTCSEL_LSE
|
||||
#error "LSE not enabled, required by STM32_RTCSEL"
|
||||
#endif
|
||||
|
||||
#endif /* !STM32_LSE_ENABLED */
|
||||
|
||||
/* PLL related checks.*/
|
||||
#if STM32_USB_CLOCK_ENABLED || \
|
||||
(STM32_SW == STM32_SW_PLL) || \
|
||||
(STM32_MCOSEL == STM32_MCOSEL_PLL) || \
|
||||
defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PLL activation flag.
|
||||
*/
|
||||
#define STM32_ACTIVATE_PLL TRUE
|
||||
#else
|
||||
#define STM32_ACTIVATE_PLL FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLMUL field.
|
||||
*/
|
||||
#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLMUL (0 << 18)
|
||||
#elif STM32_PLLMUL_VALUE == 4
|
||||
#define STM32_PLLMUL (1 << 18)
|
||||
#elif STM32_PLLMUL_VALUE == 6
|
||||
#define STM32_PLLMUL (2 << 18)
|
||||
#elif STM32_PLLMUL_VALUE == 8
|
||||
#define STM32_PLLMUL (3 << 18)
|
||||
#elif STM32_PLLMUL_VALUE == 12
|
||||
#define STM32_PLLMUL (4 << 18)
|
||||
#elif STM32_PLLMUL_VALUE == 16
|
||||
#define STM32_PLLMUL (5 << 18)
|
||||
#elif STM32_PLLMUL_VALUE == 24
|
||||
#define STM32_PLLMUL (6 << 18)
|
||||
#elif STM32_PLLMUL_VALUE == 32
|
||||
#define STM32_PLLMUL (7 << 18)
|
||||
#elif STM32_PLLMUL_VALUE == 48
|
||||
#define STM32_PLLMUL (8 << 18)
|
||||
#else
|
||||
#error "invalid STM32_PLLMUL_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLDIV field.
|
||||
*/
|
||||
#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLDIV (1 << 22)
|
||||
#elif STM32_PLLDIV_VALUE == 3
|
||||
#define STM32_PLLDIV (2 << 22)
|
||||
#elif STM32_PLLDIV_VALUE == 4
|
||||
#define STM32_PLLDIV (3 << 22)
|
||||
#else
|
||||
#error "invalid STM32_PLLDIV_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL input clock frequency.
|
||||
*/
|
||||
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLCLKIN STM32_HSECLK
|
||||
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
|
||||
#define STM32_PLLCLKIN STM32_HSICLK
|
||||
#else
|
||||
#error "invalid STM32_PLLSRC value specified"
|
||||
#endif
|
||||
|
||||
/* PLL input frequency range check.*/
|
||||
#if (STM32_PLLCLKIN < 2000000) || (STM32_PLLCLKIN > 24000000)
|
||||
#error "STM32_PLLCLKIN outside acceptable range (2...24MHz)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL VCO frequency.
|
||||
*/
|
||||
#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
|
||||
|
||||
/* PLL output frequency range check.*/
|
||||
#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
|
||||
#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL output clock frequency.
|
||||
*/
|
||||
#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLDIV_VALUE)
|
||||
|
||||
/* PLL output frequency range check.*/
|
||||
#if (STM32_PLLCLKOUT < 2000000) || (STM32_PLLCLKOUT > 32000000)
|
||||
#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MSI frequency.
|
||||
* @note Values are taken from the STM8Lxx datasheet.
|
||||
*/
|
||||
#if STM32_MSIRANGE == STM32_MSIRANGE_64K
|
||||
#define STM32_MSICLK 65500
|
||||
#elif STM32_MSIRANGE == STM32_MSIRANGE_128K
|
||||
#define STM32_MSICLK 131000
|
||||
#elif STM32_MSIRANGE == STM32_MSIRANGE_256K
|
||||
#define STM32_MSICLK 262000
|
||||
#elif STM32_MSIRANGE == STM32_MSIRANGE_512K
|
||||
#define STM32_MSICLK 524000
|
||||
#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
|
||||
#define STM32_MSICLK 1050000
|
||||
#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
|
||||
#define STM32_MSICLK 2100000
|
||||
#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
|
||||
#define STM32_MSICLK 4200000
|
||||
#else
|
||||
#error "invalid STM32_MSIRANGE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System clock source.
|
||||
*/
|
||||
#if STM32_NO_INIT || defined(__DOXYGEN__)
|
||||
#define STM32_SYSCLK 2100000
|
||||
#elif (STM32_SW == STM32_SW_MSI)
|
||||
#define STM32_SYSCLK STM32_MSICLK
|
||||
#elif (STM32_SW == STM32_SW_HSI)
|
||||
#define STM32_SYSCLK STM32_HSICLK
|
||||
#elif (STM32_SW == STM32_SW_HSE)
|
||||
#define STM32_SYSCLK STM32_HSECLK
|
||||
#elif (STM32_SW == STM32_SW_PLL)
|
||||
#define STM32_SYSCLK STM32_PLLCLKOUT
|
||||
#else
|
||||
#error "invalid STM32_SW value specified"
|
||||
#endif
|
||||
|
||||
/* Check on the system clock.*/
|
||||
#if STM32_SYSCLK > STM32_SYSCLK_MAX
|
||||
#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief AHB frequency.
|
||||
*/
|
||||
#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_HCLK (STM32_SYSCLK / 1)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV2
|
||||
#define STM32_HCLK (STM32_SYSCLK / 2)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV4
|
||||
#define STM32_HCLK (STM32_SYSCLK / 4)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV8
|
||||
#define STM32_HCLK (STM32_SYSCLK / 8)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV16
|
||||
#define STM32_HCLK (STM32_SYSCLK / 16)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV64
|
||||
#define STM32_HCLK (STM32_SYSCLK / 64)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV128
|
||||
#define STM32_HCLK (STM32_SYSCLK / 128)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV256
|
||||
#define STM32_HCLK (STM32_SYSCLK / 256)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV512
|
||||
#define STM32_HCLK (STM32_SYSCLK / 512)
|
||||
#else
|
||||
#error "invalid STM32_HPRE value specified"
|
||||
#endif
|
||||
|
||||
/* AHB frequency check.*/
|
||||
#if STM32_HCLK > STM32_SYSCLK_MAX
|
||||
#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB1 frequency.
|
||||
*/
|
||||
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_PCLK1 (STM32_HCLK / 1)
|
||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV2
|
||||
#define STM32_PCLK1 (STM32_HCLK / 2)
|
||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV4
|
||||
#define STM32_PCLK1 (STM32_HCLK / 4)
|
||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV8
|
||||
#define STM32_PCLK1 (STM32_HCLK / 8)
|
||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV16
|
||||
#define STM32_PCLK1 (STM32_HCLK / 16)
|
||||
#else
|
||||
#error "invalid STM32_PPRE1 value specified"
|
||||
#endif
|
||||
|
||||
/* APB1 frequency check.*/
|
||||
#if STM32_PCLK1 > STM32_PCLK1_MAX
|
||||
#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB2 frequency.
|
||||
*/
|
||||
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_PCLK2 (STM32_HCLK / 1)
|
||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV2
|
||||
#define STM32_PCLK2 (STM32_HCLK / 2)
|
||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV4
|
||||
#define STM32_PCLK2 (STM32_HCLK / 4)
|
||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV8
|
||||
#define STM32_PCLK2 (STM32_HCLK / 8)
|
||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV16
|
||||
#define STM32_PCLK2 (STM32_HCLK / 16)
|
||||
#else
|
||||
#error "invalid STM32_PPRE2 value specified"
|
||||
#endif
|
||||
|
||||
/* APB2 frequency check.*/
|
||||
#if STM32_PCLK2 > STM32_PCLK2_MAX
|
||||
#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCO divider clock.
|
||||
*/
|
||||
#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
|
||||
#define STM32_MCODIVCLK 0
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_HSI
|
||||
#define STM32_MCODIVCLK STM32_HSICLK
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_MSI
|
||||
#define STM32_MCODIVCLK STM32_MSICLK
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_HSE
|
||||
#define STM32_MCODIVCLK STM32_HSECLK
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_PLL
|
||||
#define STM32_MCODIVCLK STM32_PLLCLKOUT
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_LSI
|
||||
#define STM32_MCODIVCLK STM32_LSICLK
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_LSE
|
||||
#define STM32_MCODIVCLK STM32_LSECLK
|
||||
#else
|
||||
#error "invalid STM32_MCOSEL value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCO output pin clock.
|
||||
*/
|
||||
#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_MCOCLK STM32_MCODIVCLK
|
||||
#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
|
||||
#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
|
||||
#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
|
||||
#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
|
||||
#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
|
||||
#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
|
||||
#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
|
||||
#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
|
||||
#else
|
||||
#error "invalid STM32_MCOPRE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief HSE divider toward RTC clock.
|
||||
*/
|
||||
#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__)
|
||||
#define STM32_HSEDIVCLK (STM32_HSECLK / 2)
|
||||
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__)
|
||||
#define STM32_HSEDIVCLK (STM32_HSECLK / 4)
|
||||
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__)
|
||||
#define STM32_HSEDIVCLK (STM32_HSECLK / 8)
|
||||
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__)
|
||||
#define STM32_HSEDIVCLK (STM32_HSECLK / 16)
|
||||
#else
|
||||
#error "invalid STM32_RTCPRE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief RTC/LCD clock.
|
||||
*/
|
||||
#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
|
||||
#define STM32_RTCCLK 0
|
||||
#elif STM32_RTCSEL == STM32_RTCSEL_LSE
|
||||
#define STM32_RTCCLK STM32_LSECLK
|
||||
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
|
||||
#define STM32_RTCCLK STM32_LSICLK
|
||||
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
|
||||
#define STM32_RTCCLK STM32_HSEDIVCLK
|
||||
#else
|
||||
#error "invalid STM32_RTCSEL value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USB frequency.
|
||||
*/
|
||||
#define STM32_USBCLK (STM32_PLLVCO / 2)
|
||||
|
||||
/**
|
||||
* @brief Timers 2, 3, 4, 6, 7 clock.
|
||||
*/
|
||||
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
|
||||
#else
|
||||
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Timers 9, 10, 11 clock.
|
||||
*/
|
||||
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
|
||||
#else
|
||||
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Flash settings.
|
||||
*/
|
||||
#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
|
||||
#define STM32_FLASHBITS1 0x00000000
|
||||
#else
|
||||
#define STM32_FLASHBITS1 0x00000004
|
||||
#define STM32_FLASHBITS2 0x00000007
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* Various helpers.*/
|
||||
#include "nvic.h"
|
||||
#include "stm32_isr.h"
|
||||
#include "stm32_dma.h"
|
||||
#include "stm32_rcc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void hal_lld_init(void);
|
||||
void stm32_clock_init(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
# List of all the STM32L0xx platform files.
|
||||
ifeq ($(USE_SMART_BUILD),yes)
|
||||
HALCONF := $(strip $(shell cat halconf.h | egrep -e "define"))
|
||||
|
||||
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/stm32_dma.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/hal_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c
|
||||
ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/adc_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/ext_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/can_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
|
||||
endif
|
||||
else
|
||||
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/stm32_dma.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/hal_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/adc_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/can_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/ext_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
|
||||
endif
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/STM32L0xx \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1
|
||||
Loading…
Reference in New Issue