From 95fc35d5f581597d26044733948f21aebf3845ac Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Mon, 14 Dec 2015 14:53:55 +0000
Subject: [PATCH] Fixed some details about ADCv3.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8600 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 demos/STM32/RT-STM32F302R8-NUCLEO/mcuconf.h |  5 ---
 os/hal/ports/STM32/LLD/ADCv3/adc_lld.c      | 50 ++++++++++++++++++++-
 testhal/STM32/STM32L4xx/GPT-ADC/main.c      |  4 +-
 3 files changed, 51 insertions(+), 8 deletions(-)

diff --git a/demos/STM32/RT-STM32F302R8-NUCLEO/mcuconf.h b/demos/STM32/RT-STM32F302R8-NUCLEO/mcuconf.h
index 8560d7306..f7820d2c4 100644
--- a/demos/STM32/RT-STM32F302R8-NUCLEO/mcuconf.h
+++ b/demos/STM32/RT-STM32F302R8-NUCLEO/mcuconf.h
@@ -62,17 +62,12 @@
 /*
  * ADC driver system settings.
  */
-#define STM32_ADC_DUAL_MODE                 FALSE
 #define STM32_ADC_COMPACT_SAMPLES           FALSE
 #define STM32_ADC_USE_ADC1                  FALSE
-#define STM32_ADC_USE_ADC2                  FALSE
 #define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)
-#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
 #define STM32_ADC_ADC1_DMA_PRIORITY         2
-#define STM32_ADC_ADC2_DMA_PRIORITY         2
 #define STM32_ADC_ADC12_IRQ_PRIORITY        5
 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5
-#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5
 #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
 
 /*
diff --git a/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c b/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c
index f186670dd..872fd3afe 100644
--- a/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c
+++ b/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c
@@ -452,6 +452,23 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
 #endif /* STM32_ADC_USE_ADC1 */
 
+#if STM32_ADC_USE_ADC2
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD2);
+#if defined(ADC1_2_COMMON)
+  ADCD2.adcc = ADC1_2_COMMON;
+#elif defined(ADC123_COMMON)
+  ADCD2.adcc = ADC123_COMMON;
+#endif
+  ADCD2.adcm    = ADC2;
+  ADCD2.dmastp  = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
+  ADCD2.dmamode = ADC_DMA_SIZE |
+                  STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+#endif /* STM32_ADC_USE_ADC2 */
+
 #if STM32_ADC_USE_ADC3
   /* Driver initialization.*/
   adcObjectInit(&ADCD3);
@@ -474,6 +491,19 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
 #endif /* STM32_ADC_USE_ADC3 */
 
+#if STM32_ADC_USE_ADC4
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD4);
+  ADCD4.adcc = ADC3_4_COMMON;
+  ADCD4.adcm    = ADC4;
+  ADCD4.dmastp  = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM);
+  ADCD4.dmamode = ADC_DMA_SIZE |
+                  STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+#endif /* STM32_ADC_USE_ADC4 */
+
   /* IRQs setup.*/
 #if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
   nvicEnableVector(STM32_ADC1_NUMBER, STM32_ADC_ADC12_IRQ_PRIORITY);
@@ -650,29 +680,47 @@ void adc_lld_stop(ADCDriver *adcp) {
     adc_lld_analog_off(adcp);
     adc_lld_vreg_off(adcp);
 
+#if defined(STM32L4XX)
     /* Resetting CCR options except default ones.*/
-    adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+    adcp->adcc->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
 
 #if STM32_ADC_USE_ADC1
     if (&ADCD1 == adcp) {
+#if defined(STM32F3XX)
+      /* Resetting CCR options except default ones.*/
+      adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
       clkmask &= ~(1 << 0);
     }
 #endif
 
 #if STM32_ADC_USE_ADC2
     if (&ADCD1 == adcp) {
+#if defined(STM32F3XX)
+      /* Resetting CCR options except default ones.*/
+      adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
       clkmask &= ~(1 << 1);
     }
 #endif
 
 #if STM32_ADC_USE_ADC3
     if (&ADCD1 == adcp) {
+#if defined(STM32F3XX)
+      /* Resetting CCR options except default ones.*/
+      adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
       clkmask &= ~(1 << 2);
     }
 #endif
 
 #if STM32_ADC_USE_ADC4
     if (&ADCD1 == adcp) {
+#if defined(STM32F3XX)
+      /* Resetting CCR options except default ones.*/
+      adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
       clkmask &= ~(1 << 3);
     }
 #endif
diff --git a/testhal/STM32/STM32L4xx/GPT-ADC/main.c b/testhal/STM32/STM32L4xx/GPT-ADC/main.c
index bc695e55a..93d4bcff6 100644
--- a/testhal/STM32/STM32L4xx/GPT-ADC/main.c
+++ b/testhal/STM32/STM32L4xx/GPT-ADC/main.c
@@ -142,8 +142,8 @@ int main(void) {
    * Activates the ADC1 driver and the temperature sensor.
    */
   adcStart(&ADCD1, NULL);
-  adcSTM32EnableVREF();
-  adcSTM32EnableTS();
+  adcSTM32EnableVREF(&ADCD1);
+  adcSTM32EnableTS(&ADCD1);
 
   /*
    * Starts an ADC continuous conversion triggered with a period of