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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6263 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-09-05 10:34:09 +00:00
parent 867c7c95aa
commit 95d85de7d5
26 changed files with 2193 additions and 47 deletions
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213
demos/nil/NIL-STM32F303-DISCOVERY/.cproject Normal file
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demos/nil/NIL-STM32F303-DISCOVERY/Makefile Normal file
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##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Enables the use of FPU on Cortex-M4.
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FPU),)
USE_FPU = no
endif
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files and paths
CHIBIOS = ../../..
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/ports/STM32F30x/platform.mk
include $(CHIBIOS)/os/nil/nil.mk
include $(CHIBIOS)/os/nil/osal/osal.mk
include $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
#include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F303xC.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(PORTSRC) \
$(KERNSRC) \
$(TESTSRC) \
$(HALSRC) \
$(OSALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various/devices_lib/accel \
$(CHIBIOS)/os/various
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m4
#TRGT = arm-elf-
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
OD = $(TRGT)objdump
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
#
# Compiler settings
##############################################################################
##############################################################################
# Start of default section
#
# List all default C defines here, like -D_DEBUG=1
DDEFS =
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
ifeq ($(USE_FPU),yes)
USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
DDEFS += -DCORTEX_USE_FPU=TRUE
DADEFS += -DCORTEX_USE_FPU=TRUE
else
DDEFS += -DCORTEX_USE_FPU=FALSE
DADEFS += -DCORTEX_USE_FPU=FALSE
endif
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
INCDIR += $(STM32INC)
USE_OPT += -DUSE_STDPERIPH_DRIVER
endif
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/rules.mk

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

108
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@ -0,0 +1,108 @@
/*
Nil RTOS - Copyright (C) 2012 Giovanni Di Sirio.
This file is part of Nil RTOS.
Nil RTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Nil RTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "hal.h"
#include "nil.h"
/*
* Thread 1.
*/
THD_WORKING_AREA(waThread1, 128);
THD_FUNCTION(Thread1, arg) {
(void)arg;
while (true) {
palSetPad(GPIOE, GPIOE_LED3_RED);
chThdSleepMilliseconds(250);
palClearPad(GPIOE, GPIOE_LED3_RED);
chThdSleepMilliseconds(250);
}
}
/*
* Thread 2.
*/
THD_WORKING_AREA(waThread2, 128);
THD_FUNCTION(Thread2, arg) {
(void)arg;
while (true) {
palSetPad(GPIOE, GPIOE_LED4_BLUE);
chThdSleepMilliseconds(500);
palClearPad(GPIOE, GPIOE_LED4_BLUE);
chThdSleepMilliseconds(500);
}
}
/*
* Thread 3.
*/
THD_WORKING_AREA(waThread3, 128);
THD_FUNCTION(Thread3, arg) {
(void)arg;
/*
* Activates the serial driver 1 using the driver default configuration.
* PA9 and PA10 are routed to USART1.
*/
sdStart(&SD1, NULL);
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(1)); /* USART1 TX. */
palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(1)); /* USART1 RX. */
while (true) {
chnWrite(&SD1, (const uint8_t *)"Hello World!\r\n", 14);
chThdSleepMilliseconds(2000);
}
}
/*
* Threads static table, one entry per thread. The number of entries must
* match NIL_CFG_NUM_THREADS.
*/
THD_TABLE_BEGIN
THD_TABLE_ENTRY("blinker1", Thread1, NULL, waThread1, sizeof(waThread1))
THD_TABLE_ENTRY("blinker2", Thread2, NULL, waThread2, sizeof(waThread2))
THD_TABLE_ENTRY("hello", Thread3, NULL, waThread3, sizeof(waThread3))
THD_TABLE_END
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/* This is now the idle thread loop, you may perform here a low priority
task but you must never try to sleep or wait in this loop. Note that
this tasks runs at the lowest priority level so any instruction added
here will be executed after all other tasks have been started.*/
while (true) {
}
}

218
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@ -0,0 +1,218 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F30x drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F30x_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PREDIV_VALUE 1
#define STM32_PLLMUL_VALUE 9
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_USART2SW STM32_USART2SW_PCLK
#define STM32_USART3SW STM32_USART3SW_PCLK
#define STM32_UART4SW STM32_UART4SW_PCLK
#define STM32_UART5SW STM32_UART5SW_PCLK
#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
#define STM32_TIM1SW STM32_TIM1SW_PCLK2
#define STM32_TIM8SW STM32_TIM8SW_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_USB_CLOCK_REQUIRED TRUE
#define STM32_USBPRE STM32_USBPRE_DIV1P5
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC34_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC34_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_DUAL_MODE FALSE
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6
#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6
#define STM32_EXT_EXTI33_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_IRQ_PRIORITY 10
#define STM32_I2C_I2C2_IRQ_PRIORITY 10
#define STM32_I2C_I2C1_DMA_PRIORITY 1
#define STM32_I2C_I2C2_DMA_PRIORITY 1
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 TRUE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 FALSE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14

109
demos/nil/NIL-STM32F303-DISCOVERY/nilconf.h Normal file
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@ -0,0 +1,109 @@
/*
Nil RTOS - Copyright (C) 2012 Giovanni Di Sirio.
This file is part of Nil RTOS.
Nil RTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Nil RTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file nilconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _NILCONF_H_
#define _NILCONF_H_
/**
* @brief Number of user threads in the application.
* @note This number is not inclusive of the idle thread which is
* Implicitly handled.
*/
#define NIL_CFG_NUM_THREADS 3
/**
* @brief System tick frequency.
*/
#define NIL_CFG_ST_FREQUENCY 50000
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#define NIL_CFG_TIMEDELTA 2
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(NIL_CFG_USE_EVENTS) || defined(__DOXYGEN__)
#define NIL_CFG_USE_EVENTS TRUE
#endif
/**
* @brief System assertions.
*/
#define NIL_CFG_ENABLE_ASSERTS FALSE
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
#define NIL_CFG_THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
*/
#define NIL_CFG_THREAD_EXT_INIT_HOOK(tr) { \
/* Add custom threads initialization code here.*/ \
}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define NIL_CFG_IDLE_ENTER_HOOK() { \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define NIL_CFG_IDLE_LEAVE_HOOK() { \
}
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in nilcore.h). */
/*===========================================================================*/
#endif /* _NILCONF_H_ */
/** @} */

6
demos/rt/RT-STM32F303-DISCOVERY/main.c
View File

@ -27,7 +27,7 @@ static msg_t Thread1(void *arg) {
(void)arg;
chRegSetThreadName("blinker");
while (TRUE) {
while (true) {
palSetPad(GPIOE, GPIOE_LED3_RED);
chThdSleepMilliseconds(125);
palClearPad(GPIOE, GPIOE_LED3_RED);
@ -61,7 +61,7 @@ static msg_t Thread1(void *arg) {
(void)arg;
chRegSetThreadName("blinker1");
while (TRUE) {
while (true) {
palSetPad(GPIOE, GPIOE_LED3_RED);
chThdSleepMilliseconds(250);
palClearPad(GPIOE, GPIOE_LED3_RED);
@ -74,7 +74,7 @@ static msg_t Thread2(void *arg) {
(void)arg;
chRegSetThreadName("blinker2");
while (TRUE) {
while (true) {
palSetPad(GPIOE, GPIOE_LED4_BLUE);
chThdSleepMilliseconds(500);
palClearPad(GPIOE, GPIOE_LED4_BLUE);

1
os/hal/ports/STM32/RTCv2/rtc_lld.c
View File

@ -26,7 +26,6 @@
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_RTC || defined(__DOXYGEN__)

13
os/nil/include/nil.h
View File

@ -549,6 +549,17 @@ typedef struct {
*/
#define chSysUnlockFromISR() port_unlock_from_isr()
/**
* @brief Evaluates if a reschedule is required.
*
* @retval true if there is a thread that must go in running state
* immediately.
* @retval false if preemption is not required.
*
* @iclass
*/
#define chSchIsRescRequiredI() ((bool)(nil.current != nil.next))
/**
* @brief Delays the invoking thread for the specified number of seconds.
* @note The specified time is rounded up to a value allowed by the real
@ -716,8 +727,8 @@ extern "C" {
syssts_t chSysGetStatusAndLockX(void);
void chSysRestoreStatusX(syssts_t sts);
thread_reference_t chSchReadyI(thread_reference_t trp, msg_t msg);
msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t timeout);
void chSchRescheduleS(void);
msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t timeout);
msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout);
void chThdResumeI(thread_reference_t *trp, msg_t msg);
void chThdSleep(systime_t time);

15
os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk Normal file
View File

@ -0,0 +1,15 @@
# List of the ChibiOS/NIL Cortex-M4 STM32F30x port files.
PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c
PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
${CHIBIOS}/os/ext/CMSIS/ST \
${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F30x \
${CHIBIOS}/os/nil/ports/ARMCMx \
${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
PORTLD = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld

3
os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s
View File

@ -18,7 +18,7 @@
*/
/**
* @file ARMCMx/GCC/nilcoreasm_v6m.s
* @file nilcoreasm_v6m.s
* @brief ARMv6-M architecture port low level code.
*
* @addtogroup ARMCMx_CORE
@ -39,7 +39,6 @@
#if !defined(__DOXYGEN__)
.set CONTEXT_OFFSET, 0
.set SCB_ICSR, 0xE000ED04
.set ICSR_PENDSVSET, 0x10000000

120
os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s Normal file
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@ -0,0 +1,120 @@
/*
ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/NIL.
ChibiOS/NIL is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/NIL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file nilcoreasm_v7m.s
* @brief ARMv7-M architecture port low level code.
*
* @addtogroup ARMCMx_CORE
* @{
*/
#define _FROM_ASM_
#include "nilconf.h"
#include "nilcore.h"
#if !defined(FALSE) || defined(__DOXYGEN__)
#define FALSE 0
#endif
#if !defined(TRUE) || defined(__DOXYGEN__)
#define TRUE 1
#endif
#if !defined(__DOXYGEN__)
.set CONTEXT_OFFSET, 0
.set SCB_ICSR, 0xE000ED04
.set ICSR_PENDSVSET, 0x10000000
.syntax unified
.cpu cortex-m4
#if CORTEX_USE_FPU
.fpu fpv4-sp-d16
#else
.fpu softvfp
#endif
.thumb
.text
/*--------------------------------------------------------------------------*
* Performs a context switch between two threads.
*--------------------------------------------------------------------------*/
.thumb_func
.globl _port_switch
_port_switch:
push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
#if CORTEX_USE_FPU
vpush {s16-s31}
#endif
str sp, [r1, #CONTEXT_OFFSET]
ldr sp, [r0, #CONTEXT_OFFSET]
#if CORTEX_USE_FPU
vpop {s16-s31}
#endif
pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
/*--------------------------------------------------------------------------*
* Start a thread by invoking its work function.
*
* Threads execution starts here, the code leaves the system critical zone
* and then jumps into the thread function passed in register R4. The
* register R5 contains the thread parameter. The function chThdExit() is
* called on thread function return.
*--------------------------------------------------------------------------*/
.thumb_func
.globl _port_thread_start
_port_thread_start:
#if !CORTEX_SIMPLIFIED_PRIORITY
movs r3, #0
msr BASEPRI, r3
#else /* CORTEX_SIMPLIFIED_PRIORITY */
cpsie i
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
mov r0, r5
blx r4
mov r3, #0
bl chSysHalt
/*--------------------------------------------------------------------------*
* Post-IRQ switch code.
*
* Exception handlers return here for context switching.
*--------------------------------------------------------------------------*/
.thumb_func
.globl _port_switch_from_isr
_port_switch_from_isr:
bl chSchRescheduleS
.globl _port_exit_from_isr
_port_exit_from_isr:
#if CORTEX_SIMPLIFIED_PRIORITY
movw r3, #:lower16:SCB_ICSR
movt r3, #:upper16:SCB_ICSR
mov r2, ICSR_PENDSVSET
str r2, [r3, #0]
cpsie i
#else /* !CORTEX_SIMPLIFIED_PRIORITY */
svc #0
#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
.L1: b .L1
#endif /* !defined(__DOXYGEN__) */
/** @} */

15
os/nil/ports/ARMCMx/nilcore_v6m.c
View File

@ -19,7 +19,7 @@
*/
/**
* @file ARMCMx/nilcore_v6m.c
* @file nilcore_v6m.c
* @brief ARMv6-M architecture port code.
*
* @addtogroup ARMCMx_V6M_CORE
@ -124,8 +124,17 @@ void _port_irq_epilogue(regarm_t lr) {
/* Setting up a fake XPSR register value.*/
ctxp->xpsr = (regarm_t)0x01000000;
/* The context switch is handled outside the ISR context..*/
ctxp->pc = (regarm_t)_port_switch_from_isr;
/* The exit sequence is different depending on if a preemption is
required or not.*/
if (chSchIsRescRequiredI()) {
/* Preemption is required we need to enforce a context switch.*/
ctxp->pc = (regarm_t)_port_switch_from_isr;
}
else {
/* Preemption not required, we just need to exit the exception
atomically.*/
ctxp->pc = (regarm_t)_port_exit_from_isr;
}
/* Note, returning without unlocking is intentional, this is done in
order to keep the rest of the context switch atomic.*/

22
os/nil/ports/ARMCMx/nilcore_v6m.h
View File

@ -19,7 +19,7 @@
*/
/**
* @file ARMCMx/chcore_v6m.h
* @file chcore_v6m.h
* @brief ARMv6-M architecture port macros and structures.
*
* @addtogroup ARMCMx_V6M_CORE
@ -183,16 +183,6 @@ struct port_intctx {
#endif /* !defined(__DOXYGEN__) */
/**
* @brief Platform dependent part of the @p thread_t structure.
* @details In this port the structure just holds a pointer to the
* @p port_intctx structure representing the stack pointer
* at context switch time.
*/
struct context {
struct port_intctx *r13;
};
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
@ -259,7 +249,7 @@ struct context {
* @param[in] ntp the thread to be switched in
* @param[in] otp the thread to be switched out
*/
#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
#if !NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
#define port_switch(ntp, otp) _port_switch(ntp, otp)
#else
#define port_switch(ntp, otp) { \
@ -270,10 +260,6 @@ struct context {
}
#endif
#if NIL_CFG_TIMEDELTA > 0
#include "nilcore_timer.h"
#endif
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
@ -290,6 +276,10 @@ extern "C" {
}
#endif
#if NIL_CFG_TIMEDELTA > 0
#include "nilcore_timer.h"
#endif
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/

174
os/nil/ports/ARMCMx/nilcore_v7m.c Normal file
View File

@ -0,0 +1,174 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file nilcore_v7m.c
* @brief ARMv7-M architecture port code.
*
* @addtogroup ARMCMx_V7M_CORE
* @{
*/
#include "nil.h"
/*===========================================================================*/
/* Module local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Module exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Module local types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Module local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Module interrupt handlers. */
/*===========================================================================*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
/**
* @brief SVC vector.
* @details The SVC vector is used for exception mode re-entering after a
* context switch.
* @note The PendSV vector is only used in advanced kernel mode.
*/
void SVC_Handler(void) {
/* The port_extctx structure is pointed by the PSP register.*/
struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
/* Discarding the current exception context and positioning the stack to
point to the real one.*/
ctxp++;
#if CORTEX_USE_FPU
/* Restoring the special register FPCCR.*/
FPU->FPCCR = (uint32_t)ctxp->fpccr;
FPU->FPCAR = FPU->FPCAR + sizeof (struct port_extctx);
#endif
/* Writing back the modified PSP value.*/
__set_PSP((uint32_t)ctxp);
/* Restoring the normal interrupts status.*/
port_unlock_from_isr();
}
#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
/**
* @brief PendSV vector.
* @details The PendSV vector is used for exception mode re-entering after a
* context switch.
* @note The PendSV vector is only used in compact kernel mode.
*/
void PendSV_Handler(void) {
/* The port_extctx structure is pointed by the PSP register.*/
struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
/* Discarding the current exception context and positioning the stack to
point to the real one.*/
ctxp++;
#if CORTEX_USE_FPU
/* Restoring the special register FPCCR.*/
FPU->FPCCR = (uint32_t)ctxp->fpccr;
FPU->FPCAR = FPU->FPCAR + sizeof (struct port_extctx);
#endif
/* Writing back the modified PSP value.*/
__set_PSP((uint32_t)ctxp);
}
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/*===========================================================================*/
/* Module exported functions. */
/*===========================================================================*/
/**
* @brief Exception exit redirection to _port_switch_from_isr().
*/
void _port_irq_epilogue(void) {
port_lock_from_isr();
if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0) {
/* The port_extctx structure is pointed by the PSP register.*/
struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
/* Adding an artificial exception return context, there is no need to
populate it fully.*/
ctxp--;
/* Writing back the modified PSP value.*/
__set_PSP((uint32_t)ctxp);
/* Setting up a fake XPSR register value.*/
ctxp->xpsr = (regarm_t)0x01000000;
/* The exit sequence is different depending on if a preemption is
required or not.*/
if (chSchIsRescRequiredI()) {
/* Preemption is required we need to enforce a context switch.*/
ctxp->pc = (regarm_t)_port_switch_from_isr;
#if CORTEX_USE_FPU
/* Enforcing a lazy FPU state save by accessing the FPCSR register.*/
(void) __get_FPSCR();
#endif
}
else {
/* Preemption not required, we just need to exit the exception
atomically.*/
ctxp->pc = (regarm_t)_port_exit_from_isr;
}
#if CORTEX_USE_FPU
{
uint32_t fpccr;
/* Saving the special register SCB_FPCCR into the reserved offset of
the Cortex-M4 exception frame.*/
(ctxp + 1)->fpccr = (regarm_t)(fpccr = FPU->FPCCR);
/* Now the FPCCR is modified in order to not restore the FPU status
from the artificial return context.*/
FPU->FPCCR = fpccr | FPU_FPCCR_LSPACT_Msk;
}
#endif
/* Note, returning without unlocking is intentional, this is done in
order to keep the rest of the context switch atomic.*/
return;
}
port_unlock_from_isr();
}
/** @} */

563
os/nil/ports/ARMCMx/nilcore_v7m.h Normal file
View File

@ -0,0 +1,563 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file chcore_v7m.h
* @brief ARMv7-M architecture port macros and structures.
*
* @addtogroup ARMCMx_V7M_CORE
* @{
*/
#ifndef _CHCORE_V7M_H_
#define _CHCORE_V7M_H_
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
/**
* @name Architecture and Compiler
* @{
*/
#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
/**
* @brief Macro defining the specific ARM architecture.
*/
#define PORT_ARCHITECTURE_ARM_v7M
/**
* @brief Name of the implemented architecture.
*/
#define PORT_ARCHITECTURE_NAME "ARMv7-M"
/**
* @brief Name of the architecture variant.
*/
#define PORT_CORE_VARIANT_NAME "Cortex-M3"
#elif (CORTEX_MODEL == CORTEX_M4)
#define PORT_ARCHITECTURE_ARM_v7ME
#define PORT_ARCHITECTURE_NAME "ARMv7-ME"
#if CORTEX_USE_FPU
#define PORT_CORE_VARIANT_NAME "Cortex-M4F"
#else
#define PORT_CORE_VARIANT_NAME "Cortex-M4"
#endif
#endif
/**
* @brief Port-specific information string.
*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define PORT_INFO "Advanced kernel mode"
#else
#define PORT_INFO "Compact kernel mode"
#endif
/** @} */
/**
* @brief This port supports a realtime counter.
*/
#define PORT_SUPPORTS_RT FALSE //TRUE
/**
* @brief Disabled value for BASEPRI register.
*/
#define CORTEX_BASEPRI_DISABLED 0
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/**
* @brief Stack size for the system idle thread.
* @details This size depends on the idle thread implementation, usually
* the idle thread should take no more space than those reserved
* by @p PORT_INT_REQUIRED_STACK.
* @note In this port it is set to 16 because the idle thread does have
* a stack frame when compiling without optimizations. You may
* reduce this value to zero when compiling with optimizations.
*/
#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
#define PORT_IDLE_THREAD_STACK_SIZE 16
#endif
/**
* @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
* @note In this port this value is conservatively set to 32 because the
* function @p chSchDoReschedule() can have a stack frame, especially
* with compiler optimizations disabled. The value can be reduced
* when compiler optimizations are enabled.
*/
#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
#define PORT_INT_REQUIRED_STACK 32
#endif
/**
* @brief Enables the use of the WFI instruction in the idle thread loop.
*/
#if !defined(CORTEX_ENABLE_WFI_IDLE)
#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
/**
* @brief FPU support in context switch.
* @details Activating this option activates the FPU support in the kernel.
*/
#if !defined(CORTEX_USE_FPU)
#define CORTEX_USE_FPU CORTEX_HAS_FPU
#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
/* This setting requires an FPU presence check in case it is externally
redefined.*/
#error "the selected core does not have an FPU"
#endif
/**
* @brief Simplified priority handling flag.
* @details Activating this option makes the Kernel work in compact mode.
* In compact mode interrupts are disabled globally instead of
* raising the priority mask to some intermediate level.
*/
#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
#define CORTEX_SIMPLIFIED_PRIORITY FALSE
#endif
/**
* @brief SVCALL handler priority.
* @note The default SVCALL handler priority is defaulted to
* @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
* @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
* priority level.
*/
#if !defined(CORTEX_PRIORITY_SVCALL)
#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
/* If it is externally redefined then better perform a validity check on it.*/
#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
#endif
/**
* @brief NVIC VTOR initialization expression.
*/
#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
#define CORTEX_VTOR_INIT 0x00000000
#endif
/**
* @brief NVIC PRIGROUP initialization expression.
* @details The default assigns all available priority bits as preemption
* priority with no sub-priority.
*/
#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS)
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
/**
* @brief Maximum usable priority for normal ISRs.
*/
#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
/**
* @brief BASEPRI level within kernel lock.
*/
#define CORTEX_BASEPRI_KERNEL \
CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
#else
#define CORTEX_MAX_KERNEL_PRIORITY 0
#endif
/**
* @brief PendSV priority level.
* @note This priority is enforced to be equal to
* @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the
* highest priority that cannot preempt the kernel.
*/
#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
/**
* @brief Generic ARM register.
*/
typedef void *regarm_t;
/* The documentation of the following declarations is in chconf.h in order
to not have duplicated structure names into the documentation.*/
#if !defined(__DOXYGEN__)
typedef uint64_t stkalign_t;
struct port_extctx {
regarm_t r0;
regarm_t r1;
regarm_t r2;
regarm_t r3;
regarm_t r12;
regarm_t lr_thd;
regarm_t pc;
regarm_t xpsr;
#if CORTEX_USE_FPU
regarm_t s0;
regarm_t s1;
regarm_t s2;
regarm_t s3;
regarm_t s4;
regarm_t s5;
regarm_t s6;
regarm_t s7;
regarm_t s8;
regarm_t s9;
regarm_t s10;
regarm_t s11;
regarm_t s12;
regarm_t s13;
regarm_t s14;
regarm_t s15;
regarm_t fpscr;
regarm_t fpccr;
#endif /* CORTEX_USE_FPU */
};
struct port_intctx {
#if CORTEX_USE_FPU
regarm_t s16;
regarm_t s17;
regarm_t s18;
regarm_t s19;
regarm_t s20;
regarm_t s21;
regarm_t s22;
regarm_t s23;
regarm_t s24;
regarm_t s25;
regarm_t s26;
regarm_t s27;
regarm_t s28;
regarm_t s29;
regarm_t s30;
regarm_t s31;
#endif /* CORTEX_USE_FPU */
regarm_t r4;
regarm_t r5;
regarm_t r6;
regarm_t r7;
regarm_t r8;
regarm_t r9;
regarm_t r10;
regarm_t r11;
regarm_t lr;
};
#endif /* !defined(__DOXYGEN__) */
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/**
* @brief Platform dependent part of the @p chThdCreateI() API.
* @details This code usually setup the context switching frame represented
* by an @p port_intctx structure.
*/
#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) { \
(tp)->ctxp = (struct port_intctx *)((uint8_t *)workspace + \
(size_t)wsize - \
sizeof(struct port_intctx)); \
(tp)->ctxp->r4 = (regarm_t)(pf); \
(tp)->ctxp->r5 = (regarm_t)(arg); \
(tp)->ctxp->lr = (regarm_t)(_port_thread_start); \
}
/**
* @brief Computes the thread working area global size.
* @note There is no need to perform alignments in this macro.
*/
#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \
sizeof(struct port_extctx) + \
(n) + (PORT_INT_REQUIRED_STACK))
/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
*/
#define PORT_IRQ_PROLOGUE()
/**
* @brief IRQ epilogue code.
* @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
/**
* @brief IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
#define PORT_IRQ_HANDLER(id) void id(void)
/**
* @brief Fast IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
#define PORT_FAST_IRQ_HANDLER(id) void id(void)
/**
* @brief Performs a context switch between two threads.
* @details This is the most critical code in any port, this function
* is responsible for the context switch between 2 threads.
* @note The implementation of this code affects <b>directly</b> the context
* switch performance so optimize here as much as you can.
*
* @param[in] ntp the thread to be switched in
* @param[in] otp the thread to be switched out
*/
#if !NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
#define port_switch(ntp, otp) _port_switch(ntp, otp)
#else
#define port_switch(ntp, otp) { \
struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \
if ((stkalign_t *)(r13 - 1) < otp->p_stklimit) \
chSysHalt("stack overflow"); \
_port_switch(ntp, otp); \
}
#endif
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void _port_irq_epilogue(void);
void _port_switch(thread_t *ntp, thread_t *otp);
void _port_thread_start(void);
void _port_switch_from_isr(void);
void _port_exit_from_isr(void);
#ifdef __cplusplus
}
#endif
#if NIL_CFG_TIMEDELTA > 0
#include "nilcore_timer.h"
#endif
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
/**
* @brief Port-related initialization code.
*/
static inline void port_init(void) {
/* Initialization of the vector table and priority related settings.*/
SCB->VTOR = CORTEX_VTOR_INIT;
/* Initializing priority grouping.*/
NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
/* DWT cycle counter enable.*/
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
/* Initialization of the system vectors used by the port.*/
#if !CORTEX_SIMPLIFIED_PRIORITY
NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL);
#endif
NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
}
/**
* @brief Returns a word encoding the current interrupts status.
*
* @return The interrupts status.
*/
static inline syssts_t port_get_irq_status(void) {
register uint32_t sts;
#if !CORTEX_SIMPLIFIED_PRIORITY
sts = __get_BASEPRI();
#else /* CORTEX_SIMPLIFIED_PRIORITY */
sts = __get_PRIMASK();
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
return sts;
}
/**
* @brief Checks the interrupt status.
*
* @param[in] sts the interrupt status word
*
* @return The interrupt status.
* @retvel false the word specified a disabled interrupts status.
* @retvel true the word specified an enabled interrupts status.
*/
static inline bool port_irq_enabled(syssts_t sts) {
#if !CORTEX_SIMPLIFIED_PRIORITY
return sts == CORTEX_BASEPRI_DISABLED;
#else /* CORTEX_SIMPLIFIED_PRIORITY */
return (sts & 1) == 0;
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
}
/**
* @brief Determines the current execution context.
*
* @return The execution context.
* @retval false not running in ISR mode.
* @retval true running in ISR mode.
*/
static inline bool port_is_isr_context(void) {
return (bool)((__get_IPSR() & 0x1FF) != 0);
}
/**
* @brief Kernel-lock action.
* @details In this port this function raises the base priority to kernel
* level.
*/
static inline void port_lock(void) {
#if !CORTEX_SIMPLIFIED_PRIORITY
__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
#else /* CORTEX_SIMPLIFIED_PRIORITY */
__disable_irq();
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
}
/**
* @brief Kernel-unlock action.
* @details In this port this function lowers the base priority to user
* level.
*/
static inline void port_unlock(void) {
#if !CORTEX_SIMPLIFIED_PRIORITY
__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
#else /* CORTEX_SIMPLIFIED_PRIORITY */
__enable_irq();
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
}
/**
* @brief Kernel-lock action from an interrupt handler.
* @details In this port this function raises the base priority to kernel
* level.
* @note Same as @p port_lock() in this port.
*/
static inline void port_lock_from_isr(void) {
port_lock();
}
/**
* @brief Kernel-unlock action from an interrupt handler.
* @details In this port this function lowers the base priority to user
* level.
* @note Same as @p port_unlock() in this port.
*/
static inline void port_unlock_from_isr(void) {
port_unlock();
}
/**
* @brief Disables all the interrupt sources.
* @note In this port it disables all the interrupt sources by raising
* the priority mask to level 0.
*/
static inline void port_disable(void) {
__disable_irq();
}
/**
* @brief Disables the interrupt sources below kernel-level priority.
* @note Interrupt sources above kernel level remains enabled.
* @note In this port it raises/lowers the base priority to kernel level.
*/
static inline void port_suspend(void) {
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
__enable_irq();
#else
__disable_irq();
#endif
}
/**
* @brief Enables all the interrupt sources.
* @note In this port it lowers the base priority to user level.
*/
static inline void port_enable(void) {
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
#endif
__enable_irq();
}
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
* @details The function is meant to return when an interrupt becomes pending.
* The simplest implementation is an empty function or macro but this
* would not take advantage of architecture-specific power saving
* modes.
* @note Implemented as an inlined @p WFI instruction.
*/
static inline void port_wait_for_interrupt(void) {
#if CORTEX_ENABLE_WFI_IDLE
__WFI;
#endif
}
static inline rtcnt_t port_rt_get_counter_value(void) {
return DWT->CYCCNT;
}
#endif /* !defined(_FROM_ASM_) */
#endif /* _CHCORE_V7M_H_ */
/** @} */

14
os/nil/src/nil.c
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@ -278,22 +278,22 @@ thread_reference_t chSchReadyI(thread_reference_t tr, msg_t msg) {
}
/**
* @brief Reschedules.
* @brief Reschedules if needed.
*
* @sclass
*/
void chSchRescheduleS() {
thread_reference_t otr = nil.current;
thread_reference_t ntr = nil.next;
void chSchRescheduleS(void) {
if (ntr != otr) {
nil.current = ntr;
if (chSchIsRescRequiredI()) {
thread_reference_t otr = nil.current;
nil.current = nil.next;
#if defined(NIL_CFG_IDLE_LEAVE_HOOK)
if (otr == &nil.threads[NIL_CFG_NUM_THREADS]) {
NIL_CFG_IDLE_LEAVE_HOOK();
}
#endif
port_switch(ntr, otr);
port_switch(nil.next, otr);
}
}

2
os/rt/ports/ARMCMx/chcore_timer.h
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@ -19,7 +19,7 @@
*/
/**
* @file ARMCMx/chcore_timer.h
* @file chcore_timer.h
* @brief System timer header file.
*
* @addtogroup ARMCMx_TIMER

2
os/rt/ports/ARMCMx/chcore_v6m.c
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@ -19,7 +19,7 @@
*/
/**
* @file ARMCMx/chcore_v6m.c
* @file chcore_v6m.c
* @brief ARMv6-M architecture port code.
*
* @addtogroup ARMCMx_V6M_CORE

10
os/rt/ports/ARMCMx/chcore_v6m.h
View File

@ -19,7 +19,7 @@
*/
/**
* @file ARMCMx/chcore_v6m.h
* @file chcore_v6m.h
* @brief ARMv6-M architecture port macros and structures.
*
* @addtogroup ARMCMx_V6M_CORE
@ -270,10 +270,6 @@ struct context {
}
#endif
#if CH_CFG_TIMEDELTA > 0
#include "chcore_timer.h"
#endif
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
@ -290,6 +286,10 @@ extern "C" {
}
#endif
#if CH_CFG_TIMEDELTA > 0
#include "chcore_timer.h"
#endif
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/

2
os/rt/ports/ARMCMx/chcore_v7m.c
View File

@ -19,7 +19,7 @@
*/
/**
* @file ARMCMx/chcore_v7m.c
* @file chcore_v7m.c
* @brief ARMv7-M architecture port code.
*
* @addtogroup ARMCMx_V7M_CORE

2
os/rt/ports/ARMCMx/chcore_v7m.h
View File

@ -19,7 +19,7 @@
*/
/**
* @file ARMCMx/chcore_v7m.h
* @file chcore_v7m.h
* @brief ARMv7-M architecture port macros and structures.
*
* @addtogroup ARMCMx_V7M_CORE

3
os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s
View File

@ -19,7 +19,7 @@
*/
/**
* @file ARMCMx/GCC/chcoreasm_v6m.s
* @file chcoreasm_v6m.s
* @brief ARMv6-M architecture port low level code.
*
* @addtogroup ARMCMx_CORE
@ -40,7 +40,6 @@
#if !defined(__DOXYGEN__)
.set CONTEXT_OFFSET, 12
.set SCB_ICSR, 0xE000ED04
.set ICSR_PENDSVSET, 0x10000000

3
os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s
View File

@ -19,7 +19,7 @@
*/
/**
* @file ARMCMx/GCC/chcoreasm_v7m.s
* @file chcoreasm_v7m.s
* @brief ARMv7-M architecture port low level code.
*
* @addtogroup ARMCMx_CORE
@ -40,7 +40,6 @@
#if !defined(__DOXYGEN__)
.set CONTEXT_OFFSET, 12
.set SCB_ICSR, 0xE000ED04
.set ICSR_PENDSVSET, 0x10000000

2
os/rt/ports/ARMCMx/compilers/GCC/chtypes.h
View File

@ -19,7 +19,7 @@
*/
/**
* @file ARMCMx/GCC/chtypes.h
* @file ARMCMx/compilers/GCC/chtypes.h
* @brief ARM Cortex-Mx port system types.
*
* @addtogroup ARMCMx_CORE