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STM32F4-Discovery demo working. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3516 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
gdisirio 2011-11-20 18:04:07 +00:00
parent d4901e2acc
commit 9369d75516
13 changed files with 166 additions and 45 deletions
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2
demos/ARMCM3-STM32L152-DISCOVERY/readme.txt
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@ -11,7 +11,7 @@ The demo runs on an ST STM32L-Discovery board.
The demo shows how to use the ADC, PWM and SPI drivers using asynchronous
APIs. The ADC samples two channels (temperature sensor and PC0) and modulates
the PWM using the sampled values. The sample data is also transmitted using
the SPI port 1.
the SPI port 2 (NSS=PB12, SCK=PB13, MISO=PB14, MOSI=PB15).
By pressing the button located on the board the test procedure is activated
with output on the serial port COM1 (USART1).

6
demos/ARMCM4-STM32F407-DISCOVERY/main.c
View File

@ -128,11 +128,11 @@ void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
/* Changes the channels pulse width, the change will be effective
starting from the next cycle.*/
pwmEnableChannelI(&PWMD4, 0, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch1));
// pwmEnableChannelI(&PWMD4, 3, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2));
pwmEnableChannelI(&PWMD4, 3, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2));
/* SPI slave selection and transmission start.*/
// spiSelectI(&SPID2);
// spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples);
spiSelectI(&SPID2);
spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples);
chSysUnlockFromIsr();
}

4
demos/ARMCM4-STM32F407-DISCOVERY/readme.txt
View File

@ -9,9 +9,9 @@ The demo runs on an ST STM32F4-Discovery board.
** The Demo **
The demo shows how to use the ADC, PWM and SPI drivers using asynchronous
APIs. The ADC samples two channels (temperature sensor and PC0) and modulates
APIs. The ADC samples two channels (temperature sensor and PC1) and modulates
the PWM using the sampled values. The sample data is also transmitted using
the SPI port 1.
the SPI port 2 (NSS=PB12, SCK=PB13, MISO=PB14, MOSI=PB15).
By pressing the button located on the board the test procedure is activated
with output on the serial port SD2 (USART2).

4
os/hal/platforms/STM32/icu_lld.c
View File

@ -346,8 +346,8 @@ void icu_lld_start(ICUDriver *icup) {
icup->tim->CR1 = 0; /* Timer disabled. */
icup->tim->DIER = 0; /* All IRQs disabled. */
icup->tim->SR = 0; /* Clear eventual pending IRQs. */
icup->tim->CCR1 = 0; /* Comparator 1 disabled. */
icup->tim->CCR2 = 0; /* Comparator 2 disabled. */
icup->tim->CCR[0] = 0; /* Comparator 1 disabled. */
icup->tim->CCR[1] = 0; /* Comparator 2 disabled. */
icup->tim->CNT = 0; /* Counter reset to zero. */
}

4
os/hal/platforms/STM32/icu_lld.h
View File

@ -262,7 +262,7 @@ struct ICUDriver {
*
* @notapi
*/
#define icu_lld_get_width(icup) ((icup)->tim->CCR2 + 1)
#define icu_lld_get_width(icup) ((icup)->tim->CCR[1] + 1)
/**
* @brief Returns the width of the latest cycle.
@ -274,7 +274,7 @@ struct ICUDriver {
*
* @notapi
*/
#define icu_lld_get_period(icup) ((icup)->tim->CCR1 + 1)
#define icu_lld_get_period(icup) ((icup)->tim->CCR[0] + 1)
/*===========================================================================*/
/* External declarations. */

12
os/hal/platforms/STM32/pwm_lld.c
View File

@ -422,10 +422,10 @@ void pwm_lld_start(PWMDriver *pwmp) {
pwmp->tim->CR1 = 0; /* Timer disabled. */
pwmp->tim->DIER = 0; /* All IRQs disabled. */
pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */
pwmp->tim->CCR1 = 0; /* Comparator 1 disabled. */
pwmp->tim->CCR2 = 0; /* Comparator 2 disabled. */
pwmp->tim->CCR3 = 0; /* Comparator 3 disabled. */
pwmp->tim->CCR4 = 0; /* Comparator 4 disabled. */
pwmp->tim->CCR[0] = 0; /* Comparator 1 disabled. */
pwmp->tim->CCR[1] = 0; /* Comparator 2 disabled. */
pwmp->tim->CCR[2] = 0; /* Comparator 3 disabled. */
pwmp->tim->CCR[3] = 0; /* Comparator 4 disabled. */
pwmp->tim->CNT = 0; /* Counter reset to zero. */
}
@ -599,7 +599,7 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
pwmchannel_t channel,
pwmcnt_t width) {
*(&pwmp->tim->CCR1 + (channel * 2)) = width; /* New duty cycle. */
pwmp->tim->CCR[channel] = width; /* New duty cycle. */
/* If there is a callback defined for the channel then the associated
interrupt must be enabled.*/
if (pwmp->config->channels[channel].callback != NULL) {
@ -627,7 +627,7 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
*/
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
*(&pwmp->tim->CCR1 + (channel * 2)) = 0;
pwmp->tim->CCR[channel] = 0;
pwmp->tim->DIER &= ~(2 << channel);
}

59
os/hal/platforms/STM32F1xx/hal_lld.h
View File

@ -43,6 +43,12 @@
#ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
#include "stm32f10x.h"
/* STM32 DMA and RCC helpers.*/
#include "stm32_dma.h"
#include "stm32_rcc.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
@ -100,6 +106,47 @@
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief STM32 TIM registers block.
* @note Removed from the ST headers and redefined because the non uniform
* declaration of the CCR registers among the various sub-families.
*/
typedef struct {
volatile uint16_t CR1;
uint16_t _resvd0;
volatile uint16_t CR2;
uint16_t _resvd1;
volatile uint16_t SMCR;
uint16_t _resvd2;
volatile uint16_t DIER;
uint16_t _resvd3;
volatile uint16_t SR;
uint16_t _resvd4;
volatile uint16_t EGR;
uint16_t _resvd5;
volatile uint16_t CCMR1;
uint16_t _resvd6;
volatile uint16_t CCMR2;
uint16_t _resvd7;
volatile uint16_t CCER;
uint16_t _resvd8;
volatile uint32_t CNT;
volatile uint16_t PSC;
uint16_t _resvd9;
volatile uint32_t ARR;
volatile uint16_t RCR;
uint16_t _resvd10;
volatile uint32_t CCR[4];
volatile uint16_t BDTR;
uint16_t _resvd11;
volatile uint16_t DCR;
uint16_t _resvd12;
volatile uint16_t DMAR;
uint16_t _resvd13;
volatile uint16_t OR;
uint16_t _resvd14;
} TIM_TypeDef;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
@ -108,18 +155,6 @@
/* External declarations. */
/*===========================================================================*/
/* Tricks required to make the TRUE/FALSE declaration inside the library
compatible.*/
#undef FALSE
#undef TRUE
#include "stm32f10x.h"
#define FALSE 0
#define TRUE (!FALSE)
/* STM32 DMA and RCC helpers.*/
#include "stm32_dma.h"
#include "stm32_rcc.h"
#ifdef __cplusplus
extern "C" {
#endif

3
os/hal/platforms/STM32F1xx/stm32f10x.h
View File

@ -1198,6 +1198,8 @@ typedef struct
* @brief TIM
*/
/* CHIBIOS FIX */
#if 0
typedef struct
{
__IO uint16_t CR1;
@ -1241,6 +1243,7 @@ typedef struct
__IO uint16_t DMAR;
uint16_t RESERVED19;
} TIM_TypeDef;
#endif
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter

41
os/hal/platforms/STM32F4xx/hal_lld.h
View File

@ -1262,6 +1262,47 @@
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief STM32 TIM registers block.
* @note Removed from the ST headers and redefined because the non uniform
* declaration of the CCR registers among the various sub-families.
*/
typedef struct {
volatile uint16_t CR1;
uint16_t _resvd0;
volatile uint16_t CR2;
uint16_t _resvd1;
volatile uint16_t SMCR;
uint16_t _resvd2;
volatile uint16_t DIER;
uint16_t _resvd3;
volatile uint16_t SR;
uint16_t _resvd4;
volatile uint16_t EGR;
uint16_t _resvd5;
volatile uint16_t CCMR1;
uint16_t _resvd6;
volatile uint16_t CCMR2;
uint16_t _resvd7;
volatile uint16_t CCER;
uint16_t _resvd8;
volatile uint32_t CNT;
volatile uint16_t PSC;
uint16_t _resvd9;
volatile uint32_t ARR;
volatile uint16_t RCR;
uint16_t _resvd10;
volatile uint32_t CCR[4];
volatile uint16_t BDTR;
uint16_t _resvd11;
volatile uint16_t DCR;
uint16_t _resvd12;
volatile uint16_t DMAR;
uint16_t _resvd13;
volatile uint16_t OR;
uint16_t _resvd14;
} TIM_TypeDef;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/

3
os/hal/platforms/STM32F4xx/stm32f4xx.h
View File

@ -868,6 +868,8 @@ typedef struct
* @brief TIM
*/
/* CHIBIOS FIX */
#if 0
typedef struct
{
__IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
@ -907,6 +909,7 @@ typedef struct
__IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
uint16_t RESERVED14; /*!< Reserved, 0x52 */
} TIM_TypeDef;
#endif
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter

55
os/hal/platforms/STM32L1xx/hal_lld.h
View File

@ -37,13 +37,11 @@
#ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
/* Tricks required to make the TRUE/FALSE declaration inside the library
compatible.*/
#undef FALSE
#undef TRUE
#include "stm32l1xx.h"
#define FALSE 0
#define TRUE (!FALSE)
/* STM32 DMA and RCC helpers.*/
#include "stm32_dma.h"
#include "stm32_rcc.h"
/*===========================================================================*/
/* Driver constants. */
@ -933,6 +931,47 @@
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief STM32 TIM registers block.
* @note Removed from the ST headers and redefined because the non uniform
* declaration of the CCR registers among the various sub-families.
*/
typedef struct {
volatile uint16_t CR1;
uint16_t _resvd0;
volatile uint16_t CR2;
uint16_t _resvd1;
volatile uint16_t SMCR;
uint16_t _resvd2;
volatile uint16_t DIER;
uint16_t _resvd3;
volatile uint16_t SR;
uint16_t _resvd4;
volatile uint16_t EGR;
uint16_t _resvd5;
volatile uint16_t CCMR1;
uint16_t _resvd6;
volatile uint16_t CCMR2;
uint16_t _resvd7;
volatile uint16_t CCER;
uint16_t _resvd8;
volatile uint32_t CNT;
volatile uint16_t PSC;
uint16_t _resvd9;
volatile uint32_t ARR;
volatile uint16_t RCR;
uint16_t _resvd10;
volatile uint32_t CCR[4];
volatile uint16_t BDTR;
uint16_t _resvd11;
volatile uint16_t DCR;
uint16_t _resvd12;
volatile uint16_t DMAR;
uint16_t _resvd13;
volatile uint16_t OR;
uint16_t _resvd14;
} TIM_TypeDef;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
@ -941,10 +980,6 @@
/* External declarations. */
/*===========================================================================*/
/* STM32 DMA and RCC helpers.*/
#include "stm32_dma.h"
#include "stm32_rcc.h"
#ifdef __cplusplus
extern "C" {
#endif

3
os/hal/platforms/STM32L1xx/stm32l1xx.h
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@ -615,6 +615,8 @@ typedef struct
* @brief TIM
*/
/* CHIBIOS FIX */
#if 0
typedef struct
{
__IO uint16_t CR1;
@ -658,6 +660,7 @@ typedef struct
__IO uint16_t OR;
uint16_t RESERVED20;
} TIM_TypeDef;
#endif
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter

1
readme.txt
View File

@ -84,6 +84,7 @@
(backported to 2.2.8).
- FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620).
- FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626).
- NEW: Added demo for the ST STM32F4-Discovery kit.
- NEW: STM32F4xx ADC driver implementation.
TODO: Backport the new solutions implemented in this ADC driver to the
STM32L1xx ADC driver.