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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6781 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2014-03-18 09:42:04 +00:00
parent 55475920fd
commit 93369a9bd2
1 changed files with 4 additions and 4 deletions
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8
os/hal/ports/STM32/STM32F30x/hal_lld.h
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@ -247,10 +247,10 @@
#define STM32_I2C2SW_SYSCLK (1 << 5) /**< I2C2 clock is SYSCLK. */
#define STM32_TIM1SW_MASK (1 << 8) /**< TIM1 clock source mask. */
#define STM32_TIM1SW_PCLK2 (0 << 8) /**< TIM1 clock is PCLK2. */
#define STM32_TIM1SW_PLLX2 (1 << 10) /**< TIM1 clock is PLL*2. */
#define STM32_TIM8SW_MASK (1 << 10) /**< TIM8 clock source mask. */
#define STM32_TIM8SW_PCLK2 (0 << 10) /**< TIM8 clock is PCLK2. */
#define STM32_TIM8SW_PLLX2 (1 << 10) /**< TIM8 clock is PLL*2. */
#define STM32_TIM1SW_PLLX2 (1 << 8) /**< TIM1 clock is PLL*2. */
#define STM32_TIM8SW_MASK (1 << 9) /**< TIM8 clock source mask. */
#define STM32_TIM8SW_PCLK2 (0 << 9) /**< TIM8 clock is PCLK2. */
#define STM32_TIM8SW_PLLX2 (1 << 9) /**< TIM8 clock is PLL*2. */
#define STM32_USART2SW_MASK (3 << 16) /**< USART2 clock source mask. */
#define STM32_USART2SW_PCLK (0 << 16) /**< USART2 clock is PCLK. */
#define STM32_USART2SW_SYSCLK (1 << 16) /**< USART2 clock is SYSCLK. */