git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3432 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
955d10acd8
commit
8cc4b7f2e8
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@ -21,6 +21,5 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \
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PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \
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${CHIBIOS}/os/hal/platforms/STM32 \
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${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \
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${CHIBIOS}/os/hal/platforms/STM32/DMAv1 \
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${CHIBIOS}/os/hal/platforms/STM32/USBv1 \
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${CHIBIOS}/os/hal/platforms/STM32/RTCv1
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@ -19,10 +19,10 @@
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*/
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/**
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* @file DMAv1/stm32_dma.c
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* @file STM32F1xx/stm32_dma.c
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* @brief DMA helper driver code.
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*
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* @addtogroup STM32_DMA
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* @addtogroup STM32F1xx_DMA
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* @details DMA sharing helper driver. In the STM32 the DMA streams are a
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* shared resource, this driver allows to allocate and free DMA
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* streams at runtime in order to allow all the other device
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@ -19,14 +19,13 @@
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*/
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/**
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* @file DMAv1/stm32_dma.h
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* @file STM32F1xx/stm32_dma.h
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* @brief DMA helper driver header.
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* @note This file requires definitions from the ST header files
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* stm32f10x.h or stm32l1xx.h.
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* @note This file requires definitions from the ST header file stm32f10x.h.
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* @note This driver uses the new naming convention used for the STM32F2xx
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* so the "DMA channels" are referred as "DMA streams".
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*
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* @addtogroup STM32_DMA
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* @addtogroup STM32F1xx_DMA
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* @{
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*/
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@ -1,5 +1,6 @@
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# List of all the STM32L1xx platform files.
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PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \
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PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \
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${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32L1xx/adc_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
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@ -9,7 +10,6 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/DMAv1/stm32_dma.c \
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${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
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# Required include directories
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@ -0,0 +1,349 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32L1xx/stm32_dma.c
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* @brief DMA helper driver code.
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*
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* @addtogroup STM32L1xx_DMA
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* @details DMA sharing helper driver. In the STM32 the DMA streams are a
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* shared resource, this driver allows to allocate and free DMA
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* streams at runtime in order to allow all the other device
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* drivers to coordinate the access to the resource.
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* @note The DMA ISR handlers are all declared into this module because
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* sharing, the various device drivers can associate a callback to
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* IRSs when allocating streams.
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/* The following macro is only defined if some driver requiring DMA services
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has been enabled.*/
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#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @brief Mask of the DMA1 streams in @p dma_streams_mask.
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*/
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#define STM32_DMA1_STREAMS_MASK 0x0000007F
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/**
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* @brief Mask of the DMA2 streams in @p dma_streams_mask.
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*/
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#define STM32_DMA2_STREAMS_MASK 0x00000F80
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/**
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* @brief Post-reset value of the stream CCR register.
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*/
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#define STM32_DMA_CCR_RESET_VALUE 0x00000000
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief DMA streams descriptors.
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* @details This table keeps the association between an unique stream
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* identifier and the involved physical registers.
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* @note Don't use this array directly, use the appropriate wrapper macros
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* instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
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*/
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const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
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{DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
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{DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
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{DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
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{DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
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{DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
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{DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
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{DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}
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};
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/**
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* @brief DMA ISR redirector type.
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*/
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typedef struct {
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stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
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void *dma_param; /**< @brief DMA callback parameter. */
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} dma_isr_redir_t;
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/**
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* @brief Mask of the allocated streams.
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*/
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static uint32_t dma_streams_mask;
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/**
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* @brief DMA IRQ redirectors.
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*/
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static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/**
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* @brief DMA1 stream 1 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
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if (dma_isr_redir[0].dma_func)
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dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 2 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
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if (dma_isr_redir[1].dma_func)
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dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 3 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
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if (dma_isr_redir[2].dma_func)
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dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 4 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
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if (dma_isr_redir[3].dma_func)
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dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 5 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
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if (dma_isr_redir[4].dma_func)
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dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 6 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
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if (dma_isr_redir[5].dma_func)
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dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 7 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
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if (dma_isr_redir[6].dma_func)
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dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief STM32 DMA helper initialization.
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*
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* @init
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*/
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void dmaInit(void) {
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int i;
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dma_streams_mask = 0;
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for (i = 0; i < STM32_DMA_STREAMS; i++) {
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_stm32_dma_streams[i].channel->CCR = 0;
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dma_isr_redir[i].dma_func = NULL;
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}
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DMA1->IFCR = 0xFFFFFFFF;
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}
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/**
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* @brief Allocates a DMA stream.
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* @details The stream is allocated and, if required, the DMA clock enabled.
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* The function also enables the IRQ vector associated to the stream
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* and initializes its priority.
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* @pre The stream must not be already in use or an error is returned.
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* @post The stream is allocated and the default ISR handler redirected
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* to the specified function.
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* @post The stream ISR vector is enabled and its priority configured.
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* @post The stream must be freed using @p dmaStreamRelease() before it can
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* be reused with another peripheral.
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* @post The stream is in its post-reset state.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] priority IRQ priority mask for the DMA stream
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* @param[in] func handling function pointer, can be @p NULL
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* @param[in] param a parameter to be passed to the handling function
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* @return The operation status.
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* @retval FALSE no error, stream taken.
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* @retval TRUE error, stream already taken.
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*
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* @special
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*/
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bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
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uint32_t priority,
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stm32_dmaisr_t func,
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void *param) {
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chDbgCheck(dmastp != NULL, "dmaAllocate");
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/* Checks if the stream is already taken.*/
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if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
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return TRUE;
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/* Marks the stream as allocated.*/
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dma_isr_redir[dmastp->selfindex].dma_func = func;
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dma_isr_redir[dmastp->selfindex].dma_param = param;
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dma_streams_mask |= (1 << dmastp->selfindex);
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/* Enabling DMA clocks required by the current streams set.*/
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if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
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rccEnableDMA1(FALSE);
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/* Putting the stream in a safe state.*/
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dmaStreamDisable(dmastp);
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dmaStreamClearInterrupt(dmastp);
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dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
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/* Enables the associated IRQ vector if a callback is defined.*/
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if (func != NULL)
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NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
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return FALSE;
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}
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/**
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* @brief Releases a DMA stream.
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* @details The stream is freed and, if required, the DMA clock disabled.
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* Trying to release a unallocated stream is an illegal operation
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* and is trapped if assertions are enabled.
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* @pre The stream must have been allocated using @p dmaStreamAllocate().
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* @post The stream is again available.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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*
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* @special
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*/
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void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
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chDbgCheck(dmastp != NULL, "dmaRelease");
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/* Check if the streams is not taken.*/
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chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
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"dmaRelease(), #1", "not allocated");
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/* Disables the associated IRQ vector.*/
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NVICDisableVector(dmastp->vector);
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/* Marks the stream as not allocated.*/
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dma_streams_mask &= ~(1 << dmastp->selfindex);
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/* Shutting down clocks that are no more required, if any.*/
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if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
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rccDisableDMA1(FALSE);
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}
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#endif /* STM32_DMA_REQUIRED */
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/** @} */
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@ -0,0 +1,320 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||
2011 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
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/**
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* @file STM32L1xx/stm32_dma.h
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* @brief DMA helper driver header.
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||||
* @note This file requires definitions from the ST header file stm32f10x.h.
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||||
* @note This driver uses the new naming convention used for the STM32F2xx
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* so the "DMA channels" are referred as "DMA streams".
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*
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* @addtogroup STM32L1xx_DMA
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* @{
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*/
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#ifndef _STM32_DMA_H_
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#define _STM32_DMA_H_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Total number of DMA streams.
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* @note This is the total number of streams among all the DMA units.
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*/
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#define STM32_DMA_STREAMS 7
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|
||||
/**
|
||||
* @brief Mask of the ISR bits passed to the DMA callback functions.
|
||||
*/
|
||||
#define STM32_DMA_ISR_MASK 0x0F
|
||||
|
||||
/**
|
||||
* @name DMA streams identifiers
|
||||
* @{
|
||||
*/
|
||||
#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[0])
|
||||
#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[1])
|
||||
#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[2])
|
||||
#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[3])
|
||||
#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[4])
|
||||
#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[5])
|
||||
#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[6])
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CR register constants common to all DMA types
|
||||
*/
|
||||
#define STM32_DMA_CR_EN DMA_CCR1_EN
|
||||
#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE
|
||||
#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE
|
||||
#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE
|
||||
#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM)
|
||||
#define STM32_DMA_CR_DIR_P2M 0
|
||||
#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR
|
||||
#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM
|
||||
#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC
|
||||
#define STM32_DMA_CR_PINC DMA_CCR1_PINC
|
||||
#define STM32_DMA_CR_MINC DMA_CCR1_MINC
|
||||
#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE
|
||||
#define STM32_DMA_CR_PSIZE_BYTE 0
|
||||
#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0
|
||||
#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1
|
||||
#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE
|
||||
#define STM32_DMA_CR_MSIZE_BYTE 0
|
||||
#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0
|
||||
#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1
|
||||
#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL
|
||||
#define STM32_DMA_CR_PL(n) ((n) << 12)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CR register constants only found in enhanced DMA
|
||||
*/
|
||||
#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */
|
||||
#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Status flags passed to the ISR callbacks
|
||||
*/
|
||||
#define STM32_DMA_ISR_FEIF 0
|
||||
#define STM32_DMA_ISR_DMEIF 0
|
||||
#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1
|
||||
#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1
|
||||
#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief STM32 DMA stream descriptor structure.
|
||||
*/
|
||||
typedef struct {
|
||||
DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
|
||||
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
|
||||
uint8_t ishift; /**< @brief Bits offset in xIFCR
|
||||
register. */
|
||||
uint8_t selfindex; /**< @brief Index to self in array. */
|
||||
uint8_t vector; /**< @brief Associated IRQ vector. */
|
||||
} stm32_dma_stream_t;
|
||||
|
||||
/**
|
||||
* @brief STM32 DMA ISR function type.
|
||||
*
|
||||
* @param[in] p parameter for the registered function
|
||||
* @param[in] flags pre-shifted content of the ISR register, the bits
|
||||
* are aligned to bit zero
|
||||
*/
|
||||
typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Associates a peripheral data register to a DMA stream.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] addr value to be written in the CPAR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetPeripheral(dmastp, addr) { \
|
||||
(dmastp)->channel->CPAR = (uint32_t)(addr); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Associates a memory destination to a DMA stream.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] addr value to be written in the CMAR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetMemory0(dmastp, addr) { \
|
||||
(dmastp)->channel->CMAR = (uint32_t)(addr); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the number of transfers to be performed.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] size value to be written in the CNDTR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetTransactionSize(dmastp, size) { \
|
||||
(dmastp)->channel->CNDTR = (uint32_t)(size); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of transfers to be performed.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @return The number of transfers to be performed.
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
|
||||
|
||||
/**
|
||||
* @brief Programs the stream mode settings.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] mode value to be written in the CCR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetMode(dmastp, mode) { \
|
||||
(dmastp)->channel->CCR = (uint32_t)(mode); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream enable.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamEnable(dmastp) { \
|
||||
(dmastp)->channel->CCR |= STM32_DMA_CR_EN; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream disable.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamDisable(dmastp) { \
|
||||
(dmastp)->channel->CCR &= ~STM32_DMA_CR_EN; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream interrupt sources clear.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamClearInterrupt(dmastp) { \
|
||||
*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts a memory to memory operation using the specified stream.
|
||||
* @note The default transfer data mode is "byte to byte" but it can be
|
||||
* changed by specifying extra options in the @p mode parameter.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] mode value to be written in the CCR register, this value
|
||||
* is implicitly ORed with:
|
||||
* - @p STM32_DMA_CR_MINC
|
||||
* - @p STM32_DMA_CR_PINC
|
||||
* - @p STM32_DMA_CR_DIR_M2M
|
||||
* - @p STM32_DMA_CR_EN
|
||||
* .
|
||||
* @param[in] src source address
|
||||
* @param[in] dst destination address
|
||||
* @param[in] n number of data units to copy
|
||||
*/
|
||||
#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
|
||||
dmaStreamSetPeripheral(dmastp, src); \
|
||||
dmaStreamSetMemory0(dmastp, dst); \
|
||||
dmaStreamGetTransactionSize(dmastp, n); \
|
||||
dmaStreamSetMode(dmastp, (mode) | \
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
|
||||
STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polled wait for DMA transfer end.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*/
|
||||
#define dmaWaitCompletion(dmastp) \
|
||||
while (((dmastp)->channel->CNDTR > 0) && \
|
||||
((dmastp)->channel->CCR & STM32_DMA_CR_EN))
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void dmaInit(void);
|
||||
bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
|
||||
uint32_t priority,
|
||||
stm32_dmaisr_t func,
|
||||
void *param);
|
||||
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _STM32_DMA_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -80,7 +80,7 @@
|
|||
- NEW: Implemented new makefile system for ARM GCC ports, now objects,
|
||||
listings and out files are generated into a "build" directory and not
|
||||
together with sources. Also implemented a simplified output log mode.
|
||||
Now makefiles and load stript files are requirements and trigger a
|
||||
Now makefiles and load script files are requirements and trigger a
|
||||
rebuild if touched.
|
||||
|
||||
*** 2.3.3 ***
|
||||
|
|
|
|||
Loading…
Reference in New Issue